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gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simerr

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tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
warn: Sockets disabled, not accepting vnc client connections
warn: Sockets disabled, not accepting terminal connections
warn: Sockets disabled, not accepting gdb connections
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
warn: DTB file specified, but no device tree support in kernel
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
warn: The clidr register always reports 0 caches.
warn: clidr LoUIS field of 0b001 to match current ARM implementations.
warn: The csselr register isn't implemented.
warn: The ccsidr register isn't implemented and always reads as 0.
warn: instruction 'mcr bpiallis' unimplemented
warn: instruction 'mcr icialluis' unimplemented
hack: be nice to actually delete the event here
warn: instruction 'mcr dccimvac' unimplemented
warn: instruction 'mcr dccmvau' unimplemented
warn: instruction 'mcr icimvau' unimplemented
warn: LCD dual screen mode not supported
warn: instruction 'mcr icialluis' unimplemented
warn: instruction 'mcr bpiallis' unimplemented
stats: update regressions for o3 changes in renaming and translation.
2013-02-15 23:40:14 +01:00
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
regressions: update due to cache latency fix
2013-03-28 00:36:21 +01:00
warn: User mode does not have SPSR
warn: User mode does not have SPSR
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