204 lines
9.1 KiB
Python
204 lines
9.1 KiB
Python
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#
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# Copyright (c) 2011-2015 Advanced Micro Devices, Inc.
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# All rights reserved.
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#
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# For use for simulation and test purposes only
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are met:
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#
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# 1. Redistributions of source code must retain the above copyright notice,
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# this list of conditions and the following disclaimer.
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#
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# 2. Redistributions in binary form must reproduce the above copyright notice,
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# this list of conditions and the following disclaimer in the documentation
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# and/or other materials provided with the distribution.
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#
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# 3. Neither the name of the copyright holder nor the names of its contributors
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# may be used to endorse or promote products derived from this software
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# without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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# POSSIBILITY OF SUCH DAMAGE.
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#
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# Author: Lisa Hsu
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#
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# Configure the TLB hierarchy
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# Places which would probably need to be modified if you
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# want a different hierarchy are specified by a <Modify here .. >'
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# comment
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import m5
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from m5.objects import *
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def TLB_constructor(level):
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constructor_call = "X86GPUTLB(size = options.L%(level)dTLBentries, \
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assoc = options.L%(level)dTLBassoc, \
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hitLatency = options.L%(level)dAccessLatency,\
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missLatency2 = options.L%(level)dMissLatency,\
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maxOutstandingReqs = options.L%(level)dMaxOutstandingReqs,\
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accessDistance = options.L%(level)dAccessDistanceStat,\
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clk_domain = SrcClockDomain(\
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clock = options.GPUClock,\
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voltage_domain = VoltageDomain(\
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voltage = options.gpu_voltage)))" % locals()
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return constructor_call
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def Coalescer_constructor(level):
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constructor_call = "TLBCoalescer(probesPerCycle = \
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options.L%(level)dProbesPerCycle, \
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coalescingWindow = options.L%(level)dCoalescingWindow,\
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disableCoalescing = options.L%(level)dDisableCoalescing,\
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clk_domain = SrcClockDomain(\
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clock = options.GPUClock,\
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voltage_domain = VoltageDomain(\
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voltage = options.gpu_voltage)))" % locals()
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return constructor_call
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def create_TLB_Coalescer(options, my_level, my_index, TLB_name, Coalescer_name):
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# arguments: options, TLB level, number of private structures for this Level,
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# TLB name and Coalescer name
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for i in xrange(my_index):
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TLB_name.append(eval(TLB_constructor(my_level)))
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Coalescer_name.append(eval(Coalescer_constructor(my_level)))
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def config_tlb_hierarchy(options, system, shader_idx):
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n_cu = options.num_compute_units
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# Make this configurable now, instead of the hard coded val. The dispatcher
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# is always the last item in the system.cpu list.
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dispatcher_idx = len(system.cpu) - 1
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if options.TLB_config == "perLane":
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num_TLBs = 64 * n_cu
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elif options.TLB_config == "mono":
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num_TLBs = 1
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elif options.TLB_config == "perCU":
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num_TLBs = n_cu
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elif options.TLB_config == "2CU":
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num_TLBs = n_cu >> 1
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else:
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print "Bad option for TLB Configuration."
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sys.exit(1)
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#----------------------------------------------------------------------------------------
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# A visual representation of the TLB hierarchy
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# for ease of configuration
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# < Modify here the width and the number of levels if you want a different configuration >
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# width is the number of TLBs of the given type (i.e., D-TLB, I-TLB etc) for this level
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L1 = [{'name': 'sqc', 'width': options.num_sqc, 'TLBarray': [], 'CoalescerArray': []},
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{'name': 'dispatcher', 'width': 1, 'TLBarray': [], 'CoalescerArray': []},
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{'name': 'l1', 'width': num_TLBs, 'TLBarray': [], 'CoalescerArray': []}]
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L2 = [{'name': 'l2', 'width': 1, 'TLBarray': [], 'CoalescerArray': []}]
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L3 = [{'name': 'l3', 'width': 1, 'TLBarray': [], 'CoalescerArray': []}]
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TLB_hierarchy = [L1, L2, L3]
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#----------------------------------------------------------------------------------------
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# Create the hiearchy
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# Call the appropriate constructors and add objects to the system
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for i in xrange(len(TLB_hierarchy)):
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hierarchy_level = TLB_hierarchy[i]
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level = i+1
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for TLB_type in hierarchy_level:
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TLB_index = TLB_type['width']
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TLB_array = TLB_type['TLBarray']
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Coalescer_array = TLB_type['CoalescerArray']
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# If the sim calls for a fixed L1 TLB size across CUs,
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# override the TLB entries option
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if options.tot_L1TLB_size:
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options.L1TLBentries = options.tot_L1TLB_size / num_TLBs
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if options.L1TLBassoc > options.L1TLBentries:
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options.L1TLBassoc = options.L1TLBentries
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# call the constructors for the TLB and the Coalescer
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create_TLB_Coalescer(options, level, TLB_index,\
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TLB_array, Coalescer_array)
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system_TLB_name = TLB_type['name'] + '_tlb'
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system_Coalescer_name = TLB_type['name'] + '_coalescer'
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# add the different TLB levels to the system
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# Modify here if you want to make the TLB hierarchy a child of
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# the shader.
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exec('system.%s = TLB_array' % system_TLB_name)
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exec('system.%s = Coalescer_array' % system_Coalescer_name)
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#===========================================================
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# Specify the TLB hierarchy (i.e., port connections)
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# All TLBs but the last level TLB need to have a memSidePort (master)
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#===========================================================
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# Each TLB is connected with its Coalescer through a single port.
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# There is a one-to-one mapping of TLBs to Coalescers at a given level
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# This won't be modified no matter what the hierarchy looks like.
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for i in xrange(len(TLB_hierarchy)):
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hierarchy_level = TLB_hierarchy[i]
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level = i+1
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for TLB_type in hierarchy_level:
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name = TLB_type['name']
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for index in range(TLB_type['width']):
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exec('system.%s_coalescer[%d].master[0] = \
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system.%s_tlb[%d].slave[0]' % \
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(name, index, name, index))
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# Connect the cpuSidePort (slave) of all the coalescers in level 1
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# < Modify here if you want a different configuration >
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for TLB_type in L1:
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name = TLB_type['name']
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num_TLBs = TLB_type['width']
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if name == 'l1': # L1 D-TLBs
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tlb_per_cu = num_TLBs / n_cu
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for cu_idx in range(n_cu):
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if tlb_per_cu:
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for tlb in range(tlb_per_cu):
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exec('system.cpu[%d].CUs[%d].translation_port[%d] = \
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system.l1_coalescer[%d].slave[%d]' % \
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(shader_idx, cu_idx, tlb, cu_idx*tlb_per_cu+tlb, 0))
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else:
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exec('system.cpu[%d].CUs[%d].translation_port[%d] = \
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system.l1_coalescer[%d].slave[%d]' % \
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(shader_idx, cu_idx, tlb_per_cu, cu_idx / (n_cu / num_TLBs), cu_idx % (n_cu / num_TLBs)))
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elif name == 'dispatcher': # Dispatcher TLB
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for index in range(TLB_type['width']):
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exec('system.cpu[%d].translation_port = \
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system.dispatcher_coalescer[%d].slave[0]' % \
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(dispatcher_idx, index))
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elif name == 'sqc': # I-TLB
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for index in range(n_cu):
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sqc_tlb_index = index / options.cu_per_sqc
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sqc_tlb_port_id = index % options.cu_per_sqc
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exec('system.cpu[%d].CUs[%d].sqc_tlb_port = \
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system.sqc_coalescer[%d].slave[%d]' % \
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(shader_idx, index, sqc_tlb_index, sqc_tlb_port_id))
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# Connect the memSidePorts (masters) of all the TLBs with the
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# cpuSidePorts (slaves) of the Coalescers of the next level
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# < Modify here if you want a different configuration >
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# L1 <-> L2
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l2_coalescer_index = 0
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for TLB_type in L1:
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name = TLB_type['name']
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for index in range(TLB_type['width']):
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exec('system.%s_tlb[%d].master[0] = \
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system.l2_coalescer[0].slave[%d]' % \
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(name, index, l2_coalescer_index))
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l2_coalescer_index += 1
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# L2 <-> L3
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system.l2_tlb[0].master[0] = system.l3_coalescer[0].slave[0]
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return system
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