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gem5/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout

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stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
Redirecting stdout to build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/inorder-timing/simout
Redirecting stderr to build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/inorder-timing/simerr
inorder-regress: add hello MIPS_SE
2009-05-13 07:55:04 +02:00
M5 Simulator System
Copyright (c) 2001-2008
The Regents of The University of Michigan
All Rights Reserved
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
M5 compiled Aug 26 2010 12:56:28
M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
M5 started Aug 26 2010 12:56:32
M5 executing on zizzer
command line: build/MIPS_SE/m5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/inorder-timing -re tests/run.py build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/inorder-timing
inorder-regress: add hello MIPS_SE
2009-05-13 07:55:04 +02:00
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello World!
stats: update stats for preceding coherence changes Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
2010-09-09 20:40:19 +02:00
Exiting @ tick 28659500 because target called exit()
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