sanchayanmaity/gem5
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity
gem5/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt

504 lines
56 KiB
Text
Raw Normal View History

Stats: Back out broken update.
2011-02-08 04:23:11 +01:00
---------- Begin Simulation Statistics ----------
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
sim_seconds 2.591442 # Number of seconds simulated
sim_ticks 2591441692000 # Number of ticks simulated
Stats: Back out broken update.
2011-02-08 04:23:11 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
host_inst_rate 610490 # Simulator instruction rate (inst/s)
host_tick_rate 20960550015 # Simulator tick rate (ticks/s)
host_mem_usage 417836 # Number of bytes of host memory used
host_seconds 123.63 # Real time elapsed on the host
sim_insts 75477515 # Number of instructions simulated
system.l2c.replacements 117809 # number of replacements
system.l2c.tagsinuse 24928.376904 # Cycle average of tags in use
system.l2c.total_refs 1535240 # Total number of references to valid blocks.
system.l2c.sampled_refs 146709 # Sample count of references to valid blocks.
system.l2c.avg_refs 10.464525 # Average number of references to valid blocks.
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.l2c.occ_blocks::0 10331.534348 # Average occupied blocks per context
system.l2c.occ_blocks::1 14596.842556 # Average occupied blocks per context
system.l2c.occ_percent::0 0.157647 # Average percentage of cache occupancy
system.l2c.occ_percent::1 0.222730 # Average percentage of cache occupancy
system.l2c.ReadReq_hits::0 1198360 # number of ReadReq hits
system.l2c.ReadReq_hits::1 12495 # number of ReadReq hits
system.l2c.ReadReq_hits::total 1210855 # number of ReadReq hits
system.l2c.Writeback_hits::0 610049 # number of Writeback hits
system.l2c.Writeback_hits::total 610049 # number of Writeback hits
system.l2c.UpgradeReq_hits::0 26 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 26 # number of UpgradeReq hits
system.l2c.ReadExReq_hits::0 106473 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 106473 # number of ReadExReq hits
system.l2c.demand_hits::0 1304833 # number of demand (read+write) hits
system.l2c.demand_hits::1 12495 # number of demand (read+write) hits
system.l2c.demand_hits::total 1317328 # number of demand (read+write) hits
system.l2c.overall_hits::0 1304833 # number of overall hits
system.l2c.overall_hits::1 12495 # number of overall hits
system.l2c.overall_hits::total 1317328 # number of overall hits
system.l2c.ReadReq_misses::0 31685 # number of ReadReq misses
system.l2c.ReadReq_misses::1 37 # number of ReadReq misses
system.l2c.ReadReq_misses::total 31722 # number of ReadReq misses
system.l2c.UpgradeReq_misses::0 2875 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 2875 # number of UpgradeReq misses
system.l2c.ReadExReq_misses::0 140928 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 140928 # number of ReadExReq misses
system.l2c.demand_misses::0 172613 # number of demand (read+write) misses
system.l2c.demand_misses::1 37 # number of demand (read+write) misses
system.l2c.demand_misses::total 172650 # number of demand (read+write) misses
system.l2c.overall_misses::0 172613 # number of overall misses
system.l2c.overall_misses::1 37 # number of overall misses
system.l2c.overall_misses::total 172650 # number of overall misses
system.l2c.ReadReq_miss_latency 1654516000 # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency 1040000 # number of UpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency 7338006500 # number of ReadExReq miss cycles
system.l2c.demand_miss_latency 8992522500 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency 8992522500 # number of overall miss cycles
system.l2c.ReadReq_accesses::0 1230045 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::1 12532 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 1242577 # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::0 610049 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 610049 # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::0 2901 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 2901 # number of UpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::0 247401 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 247401 # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::0 1477446 # number of demand (read+write) accesses
system.l2c.demand_accesses::1 12532 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 1489978 # number of demand (read+write) accesses
system.l2c.overall_accesses::0 1477446 # number of overall (read+write) accesses
system.l2c.overall_accesses::1 12532 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 1489978 # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::0 0.025759 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::1 0.002952 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total 0.028712 # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::0 0.991038 # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::0 0.569634 # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::0 0.116832 # miss rate for demand accesses
system.l2c.demand_miss_rate::1 0.002952 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.119784 # miss rate for demand accesses
system.l2c.overall_miss_rate::0 0.116832 # miss rate for overall accesses
system.l2c.overall_miss_rate::1 0.002952 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.119784 # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::0 52217.642418 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::1 44716648.648649 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 44768866.291066 # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::0 361.739130 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::0 52069.187812 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::0 52096.438275 # average overall miss latency
system.l2c.demand_avg_miss_latency::1 243041148.648649 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 243093245.086924 # average overall miss latency
system.l2c.overall_avg_miss_latency::0 52096.438275 # average overall miss latency
system.l2c.overall_avg_miss_latency::1 243041148.648649 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 243093245.086924 # average overall miss latency
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
system.l2c.writebacks 103410 # number of writebacks
system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits 0 # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses 31722 # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses 2875 # number of UpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses 140928 # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses 172650 # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses 172650 # number of overall MSHR misses
system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.l2c.ReadReq_mshr_miss_latency 1273844000 # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency 115156000 # number of UpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency 5646870000 # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency 6920714000 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency 6920714000 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency 131817513000 # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency 31206766500 # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency 163024279500 # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::0 0.025789 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::1 2.531280 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total 2.557069 # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::0 0.991038 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::0 0.569634 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::0 0.116857 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::1 13.776732 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 13.893589 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::0 0.116857 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::1 13.776732 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 13.893589 # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency 40156.484459 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency 40054.260870 # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency 40069.184264 # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency 40085.224443 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency 40085.224443 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 14970647 # DTB read hits
system.cpu.dtb.read_misses 7343 # DTB read misses
system.cpu.dtb.write_hits 11215605 # DTB write hits
system.cpu.dtb.write_misses 2208 # DTB write misses
Stats: Back out broken update.
2011-02-08 04:23:11 +01:00
system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 3488 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 183 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 14977990 # DTB read accesses
system.cpu.dtb.write_accesses 11217813 # DTB write accesses
Stats: Back out broken update.
2011-02-08 04:23:11 +01:00
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu.dtb.hits 26186252 # DTB hits
system.cpu.dtb.misses 9551 # DTB misses
system.cpu.dtb.accesses 26195803 # DTB accesses
system.cpu.itb.inst_hits 60357722 # ITB inst hits
system.cpu.itb.inst_misses 4471 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 2343 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 60362193 # ITB inst accesses
system.cpu.itb.hits 60357722 # DTB hits
system.cpu.itb.misses 4471 # DTB misses
system.cpu.itb.accesses 60362193 # DTB accesses
system.cpu.numCycles 5182883384 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.num_insts 75477515 # Number of instructions executed
system.cpu.num_int_alu_accesses 68255270 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses
system.cpu.num_func_calls 1975579 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 7580611 # number of instructions that are conditional controls
system.cpu.num_int_insts 68255270 # number of integer instructions
system.cpu.num_fp_insts 10269 # number of float instructions
system.cpu.num_int_register_reads 390835391 # number of times the integer registers were read
system.cpu.num_int_register_writes 72984158 # number of times the integer registers were written
system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read
system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written
system.cpu.num_mem_refs 27351734 # number of memory refs
system.cpu.num_load_insts 15632521 # Number of load instructions
system.cpu.num_store_insts 11719213 # Number of store instructions
system.cpu.num_idle_cycles 4574345772.482235 # Number of idle cycles
system.cpu.num_busy_cycles 608537611.517765 # Number of busy cycles
system.cpu.not_idle_fraction 0.117413 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.882587 # Percentage of idle cycles
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 82953 # number of quiesce instructions executed
system.cpu.icache.replacements 852971 # number of replacements
system.cpu.icache.tagsinuse 510.943281 # Cycle average of tags in use
system.cpu.icache.total_refs 59504239 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 853483 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 69.719302 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 18512998000 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::0 510.943281 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.997936 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::0 59504239 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 59504239 # number of ReadReq hits
system.cpu.icache.demand_hits::0 59504239 # number of demand (read+write) hits
system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 59504239 # number of demand (read+write) hits
system.cpu.icache.overall_hits::0 59504239 # number of overall hits
system.cpu.icache.overall_hits::1 0 # number of overall hits
system.cpu.icache.overall_hits::total 59504239 # number of overall hits
system.cpu.icache.ReadReq_misses::0 853483 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 853483 # number of ReadReq misses
system.cpu.icache.demand_misses::0 853483 # number of demand (read+write) misses
system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 853483 # number of demand (read+write) misses
system.cpu.icache.overall_misses::0 853483 # number of overall misses
system.cpu.icache.overall_misses::1 0 # number of overall misses
system.cpu.icache.overall_misses::total 853483 # number of overall misses
system.cpu.icache.ReadReq_miss_latency 12547128000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency 12547128000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency 12547128000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::0 60357722 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 60357722 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::0 60357722 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 60357722 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::0 60357722 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 60357722 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::0 0.014140 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::0 0.014140 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::0 0.014140 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::0 14701.087192 # average ReadReq miss latency
Stats: Back out broken update.
2011-02-08 04:23:11 +01:00
system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu.icache.demand_avg_miss_latency::0 14701.087192 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::0 14701.087192 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency
Stats: Back out broken update.
2011-02-08 04:23:11 +01:00
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
Stats: Back out broken update.
2011-02-08 04:23:11 +01:00
system.cpu.icache.cache_copies 0 # number of cache copies performed
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu.icache.writebacks 45661 # number of writebacks
Stats: Back out broken update.
2011-02-08 04:23:11 +01:00
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses 853483 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses 853483 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses 853483 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.ReadReq_mshr_miss_latency 9984295500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 9984295500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 9984295500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency 350913000 # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency 350913000 # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate::0 0.014140 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::0 0.014140 # mshr miss rate for demand accesses
Stats: Back out broken update.
2011-02-08 04:23:11 +01:00
system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu.icache.overall_mshr_miss_rate::0 0.014140 # mshr miss rate for overall accesses
Stats: Back out broken update.
2011-02-08 04:23:11 +01:00
system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu.icache.ReadReq_avg_mshr_miss_latency 11698.294518 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 11698.294518 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 11698.294518 # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
Stats: Back out broken update.
2011-02-08 04:23:11 +01:00
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 626903 # number of replacements
system.cpu.dcache.tagsinuse 511.875592 # Cycle average of tags in use
system.cpu.dcache.total_refs 23615096 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 627415 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 37.638718 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 660309000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::0 511.875592 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.999757 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::0 13170367 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 13170367 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::0 9958094 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 9958094 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::0 236142 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 236142 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::0 247592 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 247592 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::0 23128461 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 23128461 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::0 23128461 # number of overall hits
system.cpu.dcache.overall_hits::1 0 # number of overall hits
system.cpu.dcache.overall_hits::total 23128461 # number of overall hits
system.cpu.dcache.ReadReq_misses::0 368563 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 368563 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::0 250302 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 250302 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::0 11451 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 11451 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::0 618865 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 618865 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::0 618865 # number of overall misses
system.cpu.dcache.overall_misses::1 0 # number of overall misses
system.cpu.dcache.overall_misses::total 618865 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency 5846897000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 9551170500 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency 186076500 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency 15398067500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency 15398067500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::0 13538930 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 13538930 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::0 10208396 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 10208396 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::0 247593 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 247593 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::0 247592 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 247592 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::0 23747326 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 23747326 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::0 23747326 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 23747326 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::0 0.027222 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::0 0.024519 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::0 0.046249 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::0 0.026060 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::0 0.026060 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::0 15864.036813 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::0 38158.586428 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 16249.803511 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::0 24881.141283 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::0 24881.141283 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks 564388 # number of writebacks
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses 368563 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses 250302 # number of WriteReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses 11451 # number of LoadLockedReq MSHR misses
system.cpu.dcache.demand_mshr_misses 618865 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses 618865 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency 4741074500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency 8800219500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency 151723500 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 13541294000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 13541294000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency 146946835000 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency 40367455500 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency 187314290500 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.027222 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.024519 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.046249 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_mshr_miss_rate::0 0.026060 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::0 0.026060 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12863.674596 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35158.406645 # average WriteReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 13249.803511 # average LoadLockedReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 21880.852852 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 21880.852852 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.iocache.replacements 0 # number of replacements
system.iocache.tagsinuse 0 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks.
system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
Stats: Back out broken update.
2011-02-08 04:23:11 +01:00
system.iocache.avg_refs no_value # Average number of references to valid blocks.
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
Stats: Back out broken update.
2011-02-08 04:23:11 +01:00
system.iocache.demand_hits::0 0 # number of demand (read+write) hits
system.iocache.demand_hits::1 0 # number of demand (read+write) hits
system.iocache.demand_hits::total 0 # number of demand (read+write) hits
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.iocache.overall_hits::0 0 # number of overall hits
system.iocache.overall_hits::1 0 # number of overall hits
system.iocache.overall_hits::total 0 # number of overall hits
Stats: Back out broken update.
2011-02-08 04:23:11 +01:00
system.iocache.demand_misses::0 0 # number of demand (read+write) misses
system.iocache.demand_misses::1 0 # number of demand (read+write) misses
system.iocache.demand_misses::total 0 # number of demand (read+write) misses
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.iocache.overall_misses::0 0 # number of overall misses
system.iocache.overall_misses::1 0 # number of overall misses
system.iocache.overall_misses::total 0 # number of overall misses
system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency 0 # number of overall miss cycles
system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses
system.iocache.demand_accesses::1 0 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 0 # number of demand (read+write) accesses
Stats: Back out broken update.
2011-02-08 04:23:11 +01:00
system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses
system.iocache.overall_accesses::1 0 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 0 # number of overall (read+write) accesses
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses
system.iocache.demand_miss_rate::1 no_value # miss rate for demand accesses
system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses
Stats: Back out broken update.
2011-02-08 04:23:11 +01:00
system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses
system.iocache.overall_miss_rate::1 no_value # miss rate for overall accesses
system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.iocache.demand_avg_miss_latency::0 no_value # average overall miss latency
system.iocache.demand_avg_miss_latency::1 no_value # average overall miss latency
system.iocache.demand_avg_miss_latency::total no_value # average overall miss latency
system.iocache.overall_avg_miss_latency::0 no_value # average overall miss latency
system.iocache.overall_avg_miss_latency::1 no_value # average overall miss latency
system.iocache.overall_avg_miss_latency::total no_value # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.writebacks 0 # number of writebacks
system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
Stats: Back out broken update.
2011-02-08 04:23:11 +01:00
system.iocache.overall_mshr_hits 0 # number of overall MSHR hits
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses 0 # number of overall MSHR misses
system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
Stats: Back out broken update.
2011-02-08 04:23:11 +01:00
system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.iocache.ReadReq_mshr_uncacheable_latency 1341941439938 # number of ReadReq MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency 1341941439938 # number of overall MSHR uncacheable cycles
system.iocache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses
Stats: Back out broken update.
2011-02-08 04:23:11 +01:00
system.iocache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.iocache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated
Stats: Back out broken update.
2011-02-08 04:23:11 +01:00
system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
ARM: Add some MP regressions and clean up the disk images and kernels a bit
2011-08-19 22:08:09 +02:00
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
Stats: Back out broken update.
2011-02-08 04:23:11 +01:00
---------- End Simulation Statistics ----------
Reference in a new issue Copy permalink