2016-01-19 20:28:22 +01:00
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/*
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* Copyright (c) 2015 Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* For use for simulation and test purposes only
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* Author: Anthony Gutierrez
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*/
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#ifndef __GPU_STATIC_INST_HH__
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#define __GPU_STATIC_INST_HH__
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/*
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* @file gpu_static_inst.hh
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*
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* Defines the base class representing static instructions for the GPU. The
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* instructions are "static" because they contain no dynamic instruction
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* information. GPUStaticInst corresponds to the StaticInst class for the CPU
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* models.
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*/
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#include <cstdint>
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#include <string>
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#include "enums/OpType.hh"
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#include "enums/StorageClassType.hh"
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#include "gpu-compute/gpu_dyn_inst.hh"
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#include "gpu-compute/misc.hh"
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class BaseOperand;
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class BaseRegOperand;
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class Wavefront;
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class GPUStaticInst
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{
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public:
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GPUStaticInst(const std::string &opcode);
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void instNum(int num) { _instNum = num; }
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int instNum() { return _instNum; }
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void ipdInstNum(int num) { _ipdInstNum = num; }
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int ipdInstNum() const { return _ipdInstNum; }
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virtual void execute(GPUDynInstPtr gpuDynInst) = 0;
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virtual void generateDisassembly() = 0;
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2016-10-27 04:47:05 +02:00
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const std::string& disassemble();
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2016-01-19 20:28:22 +01:00
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virtual int getNumOperands() = 0;
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virtual bool isCondRegister(int operandIndex) = 0;
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virtual bool isScalarRegister(int operandIndex) = 0;
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virtual bool isVectorRegister(int operandIndex) = 0;
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virtual bool isSrcOperand(int operandIndex) = 0;
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virtual bool isDstOperand(int operandIndex) = 0;
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virtual int getOperandSize(int operandIndex) = 0;
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virtual int getRegisterIndex(int operandIndex) = 0;
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virtual int numDstRegOperands() = 0;
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virtual int numSrcRegOperands() = 0;
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2016-10-27 04:47:01 +02:00
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virtual bool isValid() const = 0;
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2016-01-19 20:28:22 +01:00
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/*
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* Most instructions (including all HSAIL instructions)
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* are vector ops, so _scalarOp will be false by default.
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* Derived instruction objects that are scalar ops must
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* set _scalarOp to true in their constructors.
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*/
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bool scalarOp() const { return _scalarOp; }
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virtual bool isLocalMem() const
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{
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fatal("calling isLocalMem() on non-memory instruction.\n");
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return false;
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}
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bool isArgLoad() { return false; }
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virtual uint32_t instSize() = 0;
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// only used for memory instructions
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virtual void
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initiateAcc(GPUDynInstPtr gpuDynInst)
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{
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fatal("calling initiateAcc() on a non-memory instruction.\n");
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}
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2016-10-27 04:47:01 +02:00
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// only used for memory instructions
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virtual void
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completeAcc(GPUDynInstPtr gpuDynInst)
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{
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fatal("calling completeAcc() on a non-memory instruction.\n");
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}
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2016-01-19 20:28:22 +01:00
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virtual uint32_t getTargetPc() { return 0; }
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/**
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* Query whether the instruction is an unconditional jump i.e., the jump
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* is always executed because there is no condition to be evaluated.
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*
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* If the instruction is not of branch type, the result is always false.
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*
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* @return True if the instruction is an unconditional jump.
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*/
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virtual bool unconditionalJumpInstruction() { return false; }
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static uint64_t dynamic_id_count;
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Enums::OpType o_type;
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// For flat memory accesses
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Enums::StorageClassType executed_as;
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protected:
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virtual void
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execLdAcq(GPUDynInstPtr gpuDynInst)
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{
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fatal("calling execLdAcq() on a non-load instruction.\n");
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}
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virtual void
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execSt(GPUDynInstPtr gpuDynInst)
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{
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fatal("calling execLdAcq() on a non-load instruction.\n");
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}
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virtual void
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execAtomic(GPUDynInstPtr gpuDynInst)
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{
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fatal("calling execAtomic() on a non-atomic instruction.\n");
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}
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virtual void
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execAtomicAcq(GPUDynInstPtr gpuDynInst)
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{
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fatal("calling execAtomicAcq() on a non-atomic instruction.\n");
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}
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const std::string opcode;
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std::string disassembly;
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int _instNum;
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/**
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* Identifier of the immediate post-dominator instruction.
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*/
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int _ipdInstNum;
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bool _scalarOp;
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};
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#endif // __GPU_STATIC_INST_HH__
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