390 lines
13 KiB
C++
390 lines
13 KiB
C++
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/*
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* Copyright (c) 2008 Princeton University
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* Copyright (c) 2016 Georgia Institute of Technology
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Niket Agarwal
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* Tushar Krishna
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*/
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#include "mem/ruby/network/garnet2.0/SwitchAllocator.hh"
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#include "debug/RubyNetwork.hh"
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#include "mem/ruby/network/garnet2.0/GarnetNetwork.hh"
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#include "mem/ruby/network/garnet2.0/InputUnit.hh"
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#include "mem/ruby/network/garnet2.0/OutputUnit.hh"
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#include "mem/ruby/network/garnet2.0/Router.hh"
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SwitchAllocator::SwitchAllocator(Router *router)
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: Consumer(router)
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{
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m_router = router;
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m_num_vcs = m_router->get_num_vcs();
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m_vc_per_vnet = m_router->get_vc_per_vnet();
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m_input_arbiter_activity = 0;
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m_output_arbiter_activity = 0;
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}
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void
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SwitchAllocator::init()
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{
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m_input_unit = m_router->get_inputUnit_ref();
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m_output_unit = m_router->get_outputUnit_ref();
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m_num_inports = m_router->get_num_inports();
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m_num_outports = m_router->get_num_outports();
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m_round_robin_inport.resize(m_num_outports);
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m_round_robin_invc.resize(m_num_inports);
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m_port_requests.resize(m_num_outports);
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m_vc_winners.resize(m_num_outports);
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for (int i = 0; i < m_num_inports; i++) {
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m_round_robin_invc[i] = 0;
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}
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for (int i = 0; i < m_num_outports; i++) {
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m_port_requests[i].resize(m_num_inports);
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m_vc_winners[i].resize(m_num_inports);
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m_round_robin_inport[i] = 0;
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for (int j = 0; j < m_num_inports; j++) {
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m_port_requests[i][j] = false; // [outport][inport]
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}
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}
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}
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/*
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* The wakeup function of the SwitchAllocator performs a 2-stage
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* seperable switch allocation. At the end of the 2nd stage, a free
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* output VC is assigned to the winning flits of each output port.
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* There is no separate VCAllocator stage like the one in garnet1.0.
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* At the end of this function, the router is rescheduled to wakeup
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* next cycle for peforming SA for any flits ready next cycle.
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*/
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void
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SwitchAllocator::wakeup()
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{
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arbitrate_inports(); // First stage of allocation
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arbitrate_outports(); // Second stage of allocation
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clear_request_vector();
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check_for_wakeup();
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}
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/*
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* SA-I (or SA-i) loops through all input VCs at every input port,
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* and selects one in a round robin manner.
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* - For HEAD/HEAD_TAIL flits only selects an input VC whose output port
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* has at least one free output VC.
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* - For BODY/TAIL flits, only selects an input VC that has credits
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* in its output VC.
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* Places a request for the output port from this input VC.
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*/
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void
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SwitchAllocator::arbitrate_inports()
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{
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// Select a VC from each input in a round robin manner
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// Independent arbiter at each input port
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for (int inport = 0; inport < m_num_inports; inport++) {
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int invc = m_round_robin_invc[inport];
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// Select next round robin vc candidate within valid vnet
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int next_round_robin_invc = invc;
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next_round_robin_invc++;
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if (next_round_robin_invc >= m_num_vcs)
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next_round_robin_invc = 0;
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m_round_robin_invc[inport] = next_round_robin_invc;
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for (int invc_iter = 0; invc_iter < m_num_vcs; invc_iter++) {
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if (m_input_unit[inport]->need_stage(invc, SA_,
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m_router->curCycle())) {
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// This flit is in SA stage
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int outport = m_input_unit[inport]->get_outport(invc);
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int outvc = m_input_unit[inport]->get_outvc(invc);
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// check if the flit in this InputVC is allowed to be sent
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// send_allowed conditions described in that function.
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bool make_request =
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send_allowed(inport, invc, outport, outvc);
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if (make_request) {
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m_input_arbiter_activity++;
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m_port_requests[outport][inport] = true;
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m_vc_winners[outport][inport]= invc;
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break; // got one vc winner for this port
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}
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}
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invc++;
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if (invc >= m_num_vcs)
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invc = 0;
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}
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}
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}
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/*
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* SA-II (or SA-o) loops through all output ports,
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* and selects one input VC (that placed a request during SA-I)
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* as the winner for this output port in a round robin manner.
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* - For HEAD/HEAD_TAIL flits, performs simplified outvc allocation.
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* (i.e., select a free VC from the output port).
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* - For BODY/TAIL flits, decrement a credit in the output vc.
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* The winning flit is read out from the input VC and sent to the
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* CrossbarSwitch.
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* An increment_credit signal is sent from the InputUnit
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* to the upstream router. For HEAD_TAIL/TAIL flits, is_free_signal in the
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* credit is set to true.
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*/
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void
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SwitchAllocator::arbitrate_outports()
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{
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// Now there are a set of input vc requests for output vcs.
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// Again do round robin arbitration on these requests
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// Independent arbiter at each output port
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for (int outport = 0; outport < m_num_outports; outport++) {
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int inport = m_round_robin_inport[outport];
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m_round_robin_inport[outport]++;
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if (m_round_robin_inport[outport] >= m_num_inports)
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m_round_robin_inport[outport] = 0;
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for (int inport_iter = 0; inport_iter < m_num_inports;
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inport_iter++) {
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// inport has a request this cycle for outport
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if (m_port_requests[outport][inport]) {
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// grant this outport to this inport
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int invc = m_vc_winners[outport][inport];
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int outvc = m_input_unit[inport]->get_outvc(invc);
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if (outvc == -1) {
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// VC Allocation - select any free VC from outport
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outvc = vc_allocate(outport, inport, invc);
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}
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// remove flit from Input VC
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flit *t_flit = m_input_unit[inport]->getTopFlit(invc);
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DPRINTF(RubyNetwork, "SwitchAllocator at Router %d "
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"granted outvc %d at outport %d "
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"to invc %d at inport %d to flit %s at "
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"time: %lld\n",
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m_router->get_id(), outvc,
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m_router->getPortDirectionName(
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m_output_unit[outport]->get_direction()),
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invc,
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m_router->getPortDirectionName(
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m_input_unit[inport]->get_direction()),
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*t_flit,
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m_router->curCycle());
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// Update outport field in the flit since this is
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// used by CrossbarSwitch code to send it out of
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// correct outport.
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// Note: post route compute in InputUnit,
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// outport is updated in VC, but not in flit
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t_flit->set_outport(outport);
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// set outvc (i.e., invc for next hop) in flit
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// (This was updated in VC by vc_allocate, but not in flit)
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t_flit->set_vc(outvc);
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// decrement credit in outvc
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m_output_unit[outport]->decrement_credit(outvc);
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// flit ready for Switch Traversal
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t_flit->advance_stage(ST_, m_router->curCycle());
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m_router->grant_switch(inport, t_flit);
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m_output_arbiter_activity++;
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if ((t_flit->get_type() == TAIL_) ||
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t_flit->get_type() == HEAD_TAIL_) {
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// This Input VC should now be empty
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assert(!(m_input_unit[inport]->isReady(invc,
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m_router->curCycle())));
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// Free this VC
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m_input_unit[inport]->set_vc_idle(invc,
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m_router->curCycle());
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// Send a credit back
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// along with the information that this VC is now idle
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m_input_unit[inport]->increment_credit(invc, true,
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m_router->curCycle());
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} else {
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// Send a credit back
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// but do not indicate that the VC is idle
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m_input_unit[inport]->increment_credit(invc, false,
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m_router->curCycle());
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}
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// remove this request
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m_port_requests[outport][inport] = false;
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break; // got a input winner for this outport
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}
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inport++;
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if (inport >= m_num_inports)
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inport = 0;
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}
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}
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}
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/*
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* A flit can be sent only if
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* (1) there is at least one free output VC at the
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* output port (for HEAD/HEAD_TAIL),
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* or
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* (2) if there is at least one credit (i.e., buffer slot)
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* within the VC for BODY/TAIL flits of multi-flit packets.
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* and
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* (3) pt-to-pt ordering is not violated in ordered vnets, i.e.,
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* there should be no other flit in this input port
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* within an ordered vnet
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* that arrived before this flit and is requesting the same output port.
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*/
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bool
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SwitchAllocator::send_allowed(int inport, int invc, int outport, int outvc)
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{
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// Check if outvc needed
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// Check if credit needed (for multi-flit packet)
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// Check if ordering violated (in ordered vnet)
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int vnet = get_vnet(invc);
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bool has_outvc = (outvc != -1);
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bool has_credit = false;
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if (!has_outvc) {
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// needs outvc
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// this is only true for HEAD and HEAD_TAIL flits.
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if (m_output_unit[outport]->has_free_vc(vnet)) {
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has_outvc = true;
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// each VC has at least one buffer,
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// so no need for additional credit check
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has_credit = true;
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}
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} else {
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has_credit = m_output_unit[outport]->has_credit(outvc);
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}
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// cannot send if no outvc or no credit.
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if (!has_outvc || !has_credit)
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return false;
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// protocol ordering check
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if ((m_router->get_net_ptr())->isVNetOrdered(vnet)) {
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// enqueue time of this flit
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Cycles t_enqueue_time = m_input_unit[inport]->get_enqueue_time(invc);
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// check if any other flit is ready for SA and for same output port
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// and was enqueued before this flit
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int vc_base = vnet*m_vc_per_vnet;
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for (int vc_offset = 0; vc_offset < m_vc_per_vnet; vc_offset++) {
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int temp_vc = vc_base + vc_offset;
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if (m_input_unit[inport]->need_stage(temp_vc, SA_,
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m_router->curCycle()) &&
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(m_input_unit[inport]->get_outport(temp_vc) == outport) &&
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(m_input_unit[inport]->get_enqueue_time(temp_vc) <
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t_enqueue_time)) {
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return false;
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}
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}
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}
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return true;
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}
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// Assign a free VC to the winner of the output port.
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int
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SwitchAllocator::vc_allocate(int outport, int inport, int invc)
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{
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// Select a free VC from the output port
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int outvc = m_output_unit[outport]->select_free_vc(get_vnet(invc));
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// has to get a valid VC since it checked before performing SA
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assert(outvc != -1);
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m_input_unit[inport]->grant_outvc(invc, outvc);
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return outvc;
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}
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// Wakeup the router next cycle to perform SA again
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// if there are flits ready.
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void
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SwitchAllocator::check_for_wakeup()
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{
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Cycles nextCycle = m_router->curCycle() + Cycles(1);
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||
|
|
|
||
|
|
for (int i = 0; i < m_num_inports; i++) {
|
||
|
|
for (int j = 0; j < m_num_vcs; j++) {
|
||
|
|
if (m_input_unit[i]->need_stage(j, SA_, nextCycle)) {
|
||
|
|
m_router->schedule_wakeup(Cycles(1));
|
||
|
|
return;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
int
|
||
|
|
SwitchAllocator::get_vnet(int invc)
|
||
|
|
{
|
||
|
|
int vnet = invc/m_vc_per_vnet;
|
||
|
|
assert(vnet < m_router->get_num_vnets());
|
||
|
|
return vnet;
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
// Clear the request vector within the allocator at end of SA-II.
|
||
|
|
// Was populated by SA-I.
|
||
|
|
void
|
||
|
|
SwitchAllocator::clear_request_vector()
|
||
|
|
{
|
||
|
|
for (int i = 0; i < m_num_outports; i++) {
|
||
|
|
for (int j = 0; j < m_num_inports; j++) {
|
||
|
|
m_port_requests[i][j] = false;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|