system.cpu.iew.wb_sent 23102 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 22607 # cumulative count of insts written-back
system.cpu.iew.wb_producers 10530 # num instructions producing a value
system.cpu.iew.wb_consumers 13790 # num instructions consuming a value
system.cpu.iew.wb_rate 0.391857 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.763597 # average fanout of values written-back
system.cpu.commit.commitSquashedInsts 15914 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 1475 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 32556 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.465721 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.244675 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 25812 79.28% 79.28% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 3638 11.17% 90.46% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 1209 3.71% 94.17% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 603 1.85% 96.03% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 337 1.04% 97.06% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 302 0.93% 97.99% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 374 1.15% 99.14% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 53 0.16% 99.30% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 228 0.70% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 32556 # Number of insts commited each cycle
system.cpu.commit.committedInsts 15162 # Number of instructions committed
system.cpu.commit.committedOps 15162 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 3673 # Number of memory references committed
system.cpu.commit.loads 2225 # Number of loads committed
system.cpu.commit.membars 0 # Number of memory barriers committed
system.cpu.commit.branches 3358 # Number of branches committed
system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
system.cpu.commit.int_insts 12174 # Number of committed integer instructions.
system.cpu.commit.function_calls 187 # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass 726 4.79% 4.79% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu 10763 70.99% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 75.77% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead 2225 14.67% 90.45% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite 1448 9.55% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 15162 # Class of committed instruction
system.cpu.commit.bw_lim_events 228 # number cycles where commit BW limit reached
system.cpu.rob.rob_reads 62581 # The number of ROB reads
system.cpu.rob.rob_writes 65380 # The number of ROB writes
system.cpu.timesIdled 195 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 21997 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 14436 # Number of Instructions Simulated
system.cpu.committedOps 14436 # Number of Ops (including micro ops) Simulated
system.cpu.cpi 3.996398 # CPI: Cycles Per Instruction
system.cpu.cpi_total 3.996398 # CPI: Total CPI of All Threads
system.cpu.ipc 0.250225 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.250225 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 36850 # number of integer regfile reads
system.cpu.int_regfile_writes 20548 # number of integer regfile writes
system.cpu.misc_regfile_reads 8142 # number of misc regfile reads
system.cpu.misc_regfile_writes 569 # number of misc regfile writes
system.cpu.dcache.tags.replacements 0 # number of replacements
system.cpu.dcache.tags.tagsinuse 99.867537 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 4648 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 31.835616 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 99.867537 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.024382 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.024382 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 21 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 125 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 10540 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 10540 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 3609 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 3609 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 1033 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 1033 # number of WriteReq hits
system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits
system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits
system.cpu.dcache.demand_hits::cpu.data 4642 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 4642 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 4642 # number of overall hits
system.cpu.dcache.overall_hits::total 4642 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 140 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 140 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 409 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 409 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 549 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 549 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 549 # number of overall misses
system.cpu.dcache.overall_misses::total 549 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 9339500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 9339500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 27134481 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 27134481 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 36473981 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 36473981 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 36473981 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 36473981 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 3749 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 3749 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses)
system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 5191 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 5191 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 5191 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 5191 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.037343 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.037343 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.283634 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.283634 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.105760 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.105760 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.105760 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.105760 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66710.714286 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 66710.714286 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 66343.474328 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 66343.474328 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 66437.123862 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 66437.123862 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 66437.123862 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 66437.123862 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 1313 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 23 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 57.086957 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 75 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 75 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 326 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 326 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 401 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 401 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 401 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 401 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 65 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 65 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 83 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 83 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 148 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 148 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 148 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 148 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5108500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 5108500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6578000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 6578000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11686500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 11686500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11686500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 11686500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017338 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017338 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.057559 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.057559 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028511 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.028511 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028511 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.028511 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78592.307692 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78592.307692 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79253.012048 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79253.012048 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78962.837838 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 78962.837838 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78962.837838 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 78962.837838 # average overall mshr miss latency
system.cpu.icache.tags.replacements 0 # number of replacements
system.cpu.icache.tags.tagsinuse 206.414108 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 6949 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 365 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 19.038356 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 206.414108 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.100788 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.100788 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 365 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 274 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.178223 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 15425 # Number of tag accesses
system.cpu.icache.tags.data_accesses 15425 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 6949 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 6949 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 6949 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 6949 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 6949 # number of overall hits
system.cpu.icache.overall_hits::total 6949 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 581 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 581 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 581 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 581 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 581 # number of overall misses
system.cpu.icache.overall_misses::total 581 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 40819000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 40819000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 40819000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 40819000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 40819000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 40819000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 7530 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 7530 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 7530 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 7530 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 7530 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 7530 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.077158 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.077158 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.077158 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.077158 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.077158 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.077158 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70256.454389 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 70256.454389 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 70256.454389 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 70256.454389 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 70256.454389 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 70256.454389 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 190 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs 95 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 216 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 216 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 216 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 216 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 216 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 216 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 365 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 365 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 365 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 365 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 365 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 365 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27746500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 27746500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27746500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 27746500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27746500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 27746500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.048473 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.048473 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.048473 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.048473 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.048473 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.048473 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76017.808219 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76017.808219 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76017.808219 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 76017.808219 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76017.808219 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 76017.808219 # average overall mshr miss latency
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 240.923513 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 426 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 0.004695 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::cpu.inst 205.773852 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 35.149660 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.006280 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001073 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.007352 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 426 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 318 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.013000 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 4613 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 4613 # Number of data accesses
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 2 # number of ReadCleanReq hits
system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits
system.cpu.l2cache.overall_hits::total 2 # number of overall hits
system.cpu.l2cache.ReadExReq_misses::cpu.data 83 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 83 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 363 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 363 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 65 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 65 # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst 363 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 148 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 511 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 363 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 148 # number of overall misses
system.cpu.l2cache.overall_misses::total 511 # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6452500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 6452500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 27176000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 27176000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5013500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 5013500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 27176000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 11466000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 38642000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 27176000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 11466000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 38642000 # number of overall miss cycles
system.cpu.l2cache.ReadExReq_accesses::cpu.data 83 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 83 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 365 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 365 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 65 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 65 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 365 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 148 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 513 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 365 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 148 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 513 # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.994521 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.994521 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.994521 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.996101 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.994521 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.996101 # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77740.963855 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77740.963855 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74865.013774 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74865.013774 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77130.769231 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77130.769231 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74865.013774 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77472.972973 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 75620.352250 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74865.013774 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77472.972973 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 75620.352250 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 83 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 83 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 363 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 363 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 65 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 65 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 363 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 148 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 511 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 363 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 148 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 511 # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5622500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5622500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 23546000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 23546000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4383500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4383500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23546000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10006000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 33552000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23546000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10006000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 33552000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.994521 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.994521 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.994521 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.996101 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994521 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.996101 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67740.963855 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67740.963855 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64865.013774 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64865.013774 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67438.461538 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67438.461538 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64865.013774 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67608.108108 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65659.491194 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64865.013774 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67608.108108 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65659.491194 # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests 513 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadResp 428 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 83 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 83 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 365 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 65 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 730 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 294 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 1024 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23360 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 32704 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)