system.cpu.iew.wb_sent 2549313271 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 2519490941 # cumulative count of insts written-back
system.cpu.iew.wb_producers 1487485532 # num instructions producing a value
system.cpu.iew.wb_consumers 1918368513 # num instructions consuming a value
system.cpu.iew.wb_rate 1.881375 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.775391 # average fanout of values written-back
system.cpu.commit.commitSquashedInsts 998632615 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 15962246 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 1201120469 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.515069 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.548329 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 712379439 59.31% 59.31% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 159650119 13.29% 72.60% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 79517213 6.62% 79.22% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 52024602 4.33% 83.55% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 28479101 2.37% 85.92% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 19489140 1.62% 87.55% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 19970906 1.66% 89.21% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 23045357 1.92% 91.13% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 106564592 8.87% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 1201120469 # Number of insts commited each cycle
system.cpu.commit.committedInsts 1819780126 # Number of instructions committed
system.cpu.commit.committedOps 1819780126 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 605324165 # Number of memory references committed
system.cpu.commit.loads 444595663 # Number of loads committed
system.cpu.commit.membars 0 # Number of memory barriers committed
system.cpu.commit.branches 214632552 # Number of branches committed
system.cpu.commit.fp_insts 805525 # Number of committed floating point instructions.
system.cpu.commit.int_insts 1718967519 # Number of committed integer instructions.
system.cpu.commit.function_calls 16767440 # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass 83736345 4.60% 4.60% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu 1129914149 62.09% 66.69% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult 75 0.00% 66.69% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv 0 0.00% 66.69% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd 805244 0.04% 66.74% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp 13 0.00% 66.74% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt 100 0.00% 66.74% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult 11 0.00% 66.74% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv 24 0.00% 66.74% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 66.74% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 66.74% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 66.74% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 66.74% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 66.74% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 66.74% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 66.74% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult 0 0.00% 66.74% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 66.74% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift 0 0.00% 66.74% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 66.74% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 66.74% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 66.74% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 66.74% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 66.74% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 66.74% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 66.74% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 66.74% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 66.74% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.74% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.74% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead 444595663 24.43% 91.17% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite 160728502 8.83% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 1819780126 # Class of committed instruction
system.cpu.commit.bw_lim_events 106564592 # number cycles where commit BW limit reached
system.cpu.rob.rob_reads 3827189418 # The number of ROB reads
system.cpu.rob.rob_writes 5774940551 # The number of ROB writes
system.cpu.timesIdled 705 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 74487 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 1736043781 # Number of Instructions Simulated
system.cpu.committedOps 1736043781 # Number of Ops (including micro ops) Simulated
system.cpu.cpi 0.771395 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.771395 # CPI: Total CPI of All Threads
system.cpu.ipc 1.296353 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.296353 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 3463571137 # number of integer regfile reads
system.cpu.int_regfile_writes 2019338951 # number of integer regfile writes
system.cpu.fp_regfile_reads 39668 # number of floating regfile reads
system.cpu.fp_regfile_writes 612 # number of floating regfile writes
system.cpu.misc_regfile_reads 25 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
system.cpu.dcache.tags.replacements 9207202 # number of replacements
system.cpu.dcache.tags.tagsinuse 4087.451175 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 712346624 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 9211298 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 77.334011 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 5127954500 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 4087.451175 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.997913 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.997913 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 699 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 2968 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 425 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 1470154674 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 1470154674 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 556848448 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 556848448 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 155498172 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 155498172 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 4 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 4 # number of LoadLockedReq hits
system.cpu.dcache.demand_hits::cpu.data 712346620 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 712346620 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 712346620 # number of overall hits
system.cpu.dcache.overall_hits::total 712346620 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 12894733 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 12894733 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 5230330 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 5230330 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data 18125063 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 18125063 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 18125063 # number of overall misses
system.cpu.dcache.overall_misses::total 18125063 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 412093066500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 412093066500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 315139193599 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 315139193599 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 85500 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 85500 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 727232260099 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 727232260099 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 727232260099 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 727232260099 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 569743181 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 569743181 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 5 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 730471683 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 730471683 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 730471683 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 730471683 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022633 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.022633 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032541 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.032541 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.200000 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.200000 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.024813 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.024813 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.024813 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.024813 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31958.247332 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 31958.247332 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60252.258194 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 60252.258194 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 85500 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 85500 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 40123.019716 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 40123.019716 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 40123.019716 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 40123.019716 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 15672953 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 9573691 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 1104455 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 68040 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 14.190667 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 140.706805 # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks 3727750 # number of writebacks
system.cpu.dcache.writebacks::total 3727750 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5562625 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 5562625 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3351141 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 3351141 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 8913766 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 8913766 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 8913766 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 8913766 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7332108 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 7332108 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1879189 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 1879189 # number of WriteReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 9211297 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 9211297 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 9211297 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 9211297 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 182971511500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 182971511500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 84313777567 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 84313777567 # number of WriteReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 84500 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 84500 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 267285289067 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 267285289067 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 267285289067 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 267285289067 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.012869 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.012869 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011692 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011692 # mshr miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.200000 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.200000 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012610 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.012610 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012610 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.012610 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24954.830384 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24954.830384 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44867.108932 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44867.108932 # average WriteReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 84500 # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 84500 # average LoadLockedReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29017.117684 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 29017.117684 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29017.117684 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 29017.117684 # average overall mshr miss latency
system.cpu.icache.tags.replacements 1 # number of replacements
system.cpu.icache.tags.tagsinuse 753.790798 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 420611422 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 949 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 443215.407798 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 753.790798 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.368062 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.368062 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 948 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 882 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.462891 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 841226771 # Number of tag accesses
system.cpu.icache.tags.data_accesses 841226771 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 420611422 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 420611422 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 420611422 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 420611422 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 420611422 # number of overall hits
system.cpu.icache.overall_hits::total 420611422 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 1489 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 1489 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 1489 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 1489 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 1489 # number of overall misses
system.cpu.icache.overall_misses::total 1489 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 114620499 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 114620499 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 114620499 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 114620499 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 114620499 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 114620499 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 420612911 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 420612911 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 420612911 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 420612911 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 420612911 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 420612911 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76978.172599 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 76978.172599 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 76978.172599 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 76978.172599 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 76978.172599 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 76978.172599 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 274 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs 68.500000 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks 1 # number of writebacks
system.cpu.icache.writebacks::total 1 # number of writebacks
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 540 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 540 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 540 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 540 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 540 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 540 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 949 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 949 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 949 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 949 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 949 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 949 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 79774499 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 79774499 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 79774499 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 79774499 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 79774499 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 79774499 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 84061.642782 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 84061.642782 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 84061.642782 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 84061.642782 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 84061.642782 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 84061.642782 # average overall mshr miss latency
system.cpu.l2cache.tags.replacements 1929018 # number of replacements
system.cpu.l2cache.tags.tagsinuse 31408.626842 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 14580161 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 1958805 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 7.443396 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 28140218000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 14352.619403 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 25.692409 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 17030.315030 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.438007 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000784 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.519724 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.958515 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 29787 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 157 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 977 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 615 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 17550 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 10488 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.909027 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 151193610 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 151193610 # Number of data accesses
system.cpu.l2cache.WritebackDirty_hits::writebacks 3727750 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 3727750 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 1 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 1 # number of WritebackClean hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 1106786 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 1106786 # number of ReadExReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6143738 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 6143738 # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.data 7250524 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 7250524 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.data 7250524 # number of overall hits
system.cpu.l2cache.overall_hits::total 7250524 # number of overall hits
system.cpu.l2cache.ReadExReq_misses::cpu.data 772419 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 772419 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 949 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 949 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1188355 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 1188355 # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst 949 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 1960774 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 1961723 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 949 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 1960774 # number of overall misses
system.cpu.l2cache.overall_misses::total 1961723 # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 69313632000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 69313632000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 78342500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 78342500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 106514273500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 106514273500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 78342500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 175827905500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 175906248000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 78342500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 175827905500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 175906248000 # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks 3727750 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total 3727750 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks 1 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 1 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1879205 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 1879205 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 949 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 949 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7332093 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 7332093 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 949 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 9211298 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 9212247 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 949 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 9211298 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 9212247 # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.411035 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.411035 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 1 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 1 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.162076 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.162076 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.212866 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.212947 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.212866 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.212947 # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 89735.793656 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 89735.793656 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82552.687039 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82552.687039 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 89631.695495 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 89631.695495 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82552.687039 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 89672.703483 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 89669.259116 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82552.687039 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 89672.703483 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 89669.259116 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.writebacks::writebacks 1024304 # number of writebacks
system.cpu.l2cache.writebacks::total 1024304 # number of writebacks
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 240 # number of CleanEvict MSHR misses
system.cpu.l2cache.CleanEvict_mshr_misses::total 240 # number of CleanEvict MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 772419 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 772419 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 949 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 949 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1188355 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1188355 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 949 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 1960774 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 1961723 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 949 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 1960774 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 1961723 # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 61589442000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 61589442000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 68852500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 68852500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 94630723500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 94630723500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 68852500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 156220165500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 156289018000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 68852500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 156220165500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 156289018000 # number of overall MSHR miss cycles
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.411035 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.411035 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.162076 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.162076 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.212866 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.212947 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.212866 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.212947 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79735.793656 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79735.793656 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72552.687039 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72552.687039 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79631.695495 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79631.695495 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72552.687039 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 79672.703483 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 79669.259116 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72552.687039 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 79672.703483 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 79669.259116 # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests 18419450 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 9207203 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 1275 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1275 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadResp 7333042 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 4752054 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 6384166 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 1879205 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 1879205 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 949 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 7332093 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1899 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27629798 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 27631697 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 60800 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 828099072 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 828159872 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 1929018 # Total snoops (count)