system.cpu.workload.num_syscalls 548 # Number of system calls
system.cpu.numCycles 725263657 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 506579366 # Number of instructions committed
system.cpu.committedOps 548692589 # Number of ops (including micro ops) committed
system.cpu.discardedOps 12911806 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
system.cpu.cpi 1.431688 # CPI: cycles per instruction
system.cpu.ipc 0.698476 # IPC: instructions per cycle
system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
system.cpu.op_class_0::IntAlu 375609862 68.46% 68.46% # Class of committed instruction
system.cpu.op_class_0::IntMult 339219 0.06% 68.52% # Class of committed instruction
system.cpu.op_class_0::IntDiv 0 0.00% 68.52% # Class of committed instruction
system.cpu.op_class_0::FloatAdd 0 0.00% 68.52% # Class of committed instruction
system.cpu.op_class_0::FloatCmp 0 0.00% 68.52% # Class of committed instruction
system.cpu.op_class_0::FloatCvt 0 0.00% 68.52% # Class of committed instruction
system.cpu.op_class_0::FloatMult 0 0.00% 68.52% # Class of committed instruction
system.cpu.op_class_0::FloatDiv 0 0.00% 68.52% # Class of committed instruction
system.cpu.op_class_0::FloatSqrt 0 0.00% 68.52% # Class of committed instruction
system.cpu.op_class_0::SimdAdd 0 0.00% 68.52% # Class of committed instruction
system.cpu.op_class_0::SimdAddAcc 0 0.00% 68.52% # Class of committed instruction
system.cpu.op_class_0::SimdAlu 0 0.00% 68.52% # Class of committed instruction
system.cpu.op_class_0::SimdCmp 0 0.00% 68.52% # Class of committed instruction
system.cpu.op_class_0::SimdCvt 0 0.00% 68.52% # Class of committed instruction
system.cpu.op_class_0::SimdMisc 0 0.00% 68.52% # Class of committed instruction
system.cpu.op_class_0::SimdMult 0 0.00% 68.52% # Class of committed instruction
system.cpu.op_class_0::SimdMultAcc 0 0.00% 68.52% # Class of committed instruction
system.cpu.op_class_0::SimdShift 0 0.00% 68.52% # Class of committed instruction
system.cpu.op_class_0::SimdShiftAcc 0 0.00% 68.52% # Class of committed instruction
system.cpu.op_class_0::SimdSqrt 0 0.00% 68.52% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAdd 0 0.00% 68.52% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAlu 0 0.00% 68.52% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCmp 0 0.00% 68.52% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCvt 0 0.00% 68.52% # Class of committed instruction
system.cpu.op_class_0::SimdFloatDiv 0 0.00% 68.52% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMisc 3 0.00% 68.52% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMult 0 0.00% 68.52% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 68.52% # Class of committed instruction
system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 68.52% # Class of committed instruction
system.cpu.op_class_0::MemRead 115883283 21.12% 89.64% # Class of committed instruction
system.cpu.op_class_0::MemWrite 56860222 10.36% 100.00% # Class of committed instruction
system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::total 548692589 # Class of committed instruction
system.cpu.tickCycles 688919604 # Number of cycles that the object actually ticked
system.cpu.idleCycles 36344053 # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.replacements 1141477 # number of replacements
system.cpu.dcache.tags.tagsinuse 4070.722142 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 170992714 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 1145573 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 149.263918 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 4896334500 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 4070.722142 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.993829 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.993829 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 553 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3 3497 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 346245015 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 346245015 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 114475063 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 114475063 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 53537828 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 53537828 # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data 2741 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 2741 # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 168012891 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 168012891 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 168015632 # number of overall hits
system.cpu.dcache.overall_hits::total 168015632 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 855770 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 855770 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 701221 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 701221 # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data 16 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 16 # number of SoftPFReq misses
system.cpu.dcache.demand_misses::cpu.data 1556991 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 1556991 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 1557007 # number of overall misses
system.cpu.dcache.overall_misses::total 1557007 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 14058873500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 14058873500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 21921294000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 21921294000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 35980167500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 35980167500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 35980167500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 35980167500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 115330833 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 115330833 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 54239049 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 54239049 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data 2757 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 2757 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488541 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 169569882 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 169569882 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 169572639 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 169572639 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.007420 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.007420 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.012928 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.012928 # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.005803 # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total 0.005803 # miss rate for SoftPFReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.009182 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.009182 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.009182 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.009182 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16428.331795 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 16428.331795 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31261.605115 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 31261.605115 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 23108.783224 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 23108.783224 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 23108.545755 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 23108.545755 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks 1069336 # number of writebacks
system.cpu.dcache.writebacks::total 1069336 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 66650 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 66650 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 344781 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 344781 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 411431 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 411431 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 411431 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 411431 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 789120 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 789120 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356440 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 356440 # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 13 # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total 13 # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 1145560 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 1145560 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 1145573 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 1145573 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12372328000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 12372328000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11135047500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 11135047500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1042000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1042000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23507375500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 23507375500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23508417500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 23508417500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006842 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006842 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006572 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006572 # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.004715 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.004715 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006756 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.006756 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006756 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.006756 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15678.639497 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15678.639497 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31239.612558 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31239.612558 # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 80153.846154 # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 80153.846154 # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20520.422763 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 20520.422763 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20521.099485 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 20521.099485 # average overall mshr miss latency
system.cpu.icache.tags.replacements 18130 # number of replacements
system.cpu.icache.tags.tagsinuse 1186.413401 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 198770599 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 20001 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 9938.033048 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 1186.413401 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.579303 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.579303 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 1871 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 63 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 58 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 312 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 1397 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.913574 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 397601201 # Number of tag accesses
system.cpu.icache.tags.data_accesses 397601201 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 198770599 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 198770599 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 198770599 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 198770599 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 198770599 # number of overall hits
system.cpu.icache.overall_hits::total 198770599 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 20001 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 20001 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 20001 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 20001 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 20001 # number of overall misses
system.cpu.icache.overall_misses::total 20001 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 455038500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 455038500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 455038500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 455038500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 455038500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 455038500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 198790600 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 198790600 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 198790600 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 198790600 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 198790600 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 198790600 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000101 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000101 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000101 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000101 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000101 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000101 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22750.787461 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 22750.787461 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 22750.787461 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 22750.787461 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 22750.787461 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 22750.787461 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks 18130 # number of writebacks
system.cpu.icache.writebacks::total 18130 # number of writebacks
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 20001 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 20001 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 20001 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 20001 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 20001 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 20001 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 435037500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 435037500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 435037500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 435037500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 435037500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 435037500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000101 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000101 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000101 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000101 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000101 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000101 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21750.787461 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21750.787461 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21750.787461 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 21750.787461 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21750.787461 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 21750.787461 # average overall mshr miss latency
system.cpu.l2cache.tags.replacements 112376 # number of replacements
system.cpu.l2cache.tags.tagsinuse 27628.930561 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 1772118 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 143588 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 12.341686 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 163251686000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 23500.584340 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 308.787313 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 3819.558908 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.717181 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.009423 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.116564 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.843168 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 31212 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 324 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4939 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 25849 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.952515 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 19061751 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 19061751 # Number of data accesses
system.cpu.l2cache.WritebackDirty_hits::writebacks 1069336 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 1069336 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 17893 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 17893 # number of WritebackClean hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 255742 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 255742 # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 17196 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 17196 # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 748691 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 748691 # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst 17196 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 1004433 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 1021629 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 17196 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 1004433 # number of overall hits
system.cpu.l2cache.overall_hits::total 1021629 # number of overall hits
system.cpu.l2cache.ReadExReq_misses::cpu.data 100949 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 100949 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2805 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 2805 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 40191 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 40191 # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst 2805 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 141140 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 143945 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 2805 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 141140 # number of overall misses
system.cpu.l2cache.overall_misses::total 143945 # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7917540500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 7917540500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 223778500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 223778500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3305085000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 3305085000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 223778500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 11222625500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 11446404000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 223778500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 11222625500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 11446404000 # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks 1069336 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total 1069336 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks 17893 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 17893 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 356691 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 356691 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 20001 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 20001 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 788882 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 788882 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 20001 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 1145573 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 1165574 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 20001 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 1145573 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 1165574 # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.283015 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.283015 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.140243 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.140243 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.050947 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.050947 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.140243 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.123205 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.123497 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.140243 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.123205 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.123497 # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78431.093919 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78431.093919 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79778.431373 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79778.431373 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82234.455475 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82234.455475 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79778.431373 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79514.138444 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 79519.288617 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79778.431373 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79514.138444 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 79519.288617 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.writebacks::writebacks 97210 # number of writebacks
system.cpu.l2cache.writebacks::total 97210 # number of writebacks
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 14 # number of ReadSharedReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::total 14 # number of ReadSharedReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data 14 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 15 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data 14 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 15 # number of overall MSHR hits
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 100949 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 100949 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2804 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2804 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 40177 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 40177 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 2804 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 141126 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 143930 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2804 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 141126 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 143930 # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6908050500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6908050500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 195670500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 195670500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2902356000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2902356000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 195670500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9810406500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 10006077000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 195670500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9810406500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 10006077000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.283015 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.283015 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.140193 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.140193 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.050929 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.050929 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.140193 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.123192 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.123484 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.140193 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.123192 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.123484 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68431.093919 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68431.093919 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69782.631954 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69782.631954 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72239.241357 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72239.241357 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69782.631954 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69515.231070 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69520.440492 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69782.631954 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69515.231070 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69520.440492 # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests 2325181 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 1159677 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4997 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 2608 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2605 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 3 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadResp 808883 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 1166546 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 18130 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 87307 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 356691 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 356691 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 20001 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 788882 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 58132 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3432623 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 3490755 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2440384 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141754176 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 144194560 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 112376 # Total snoops (count)