system.cpu.workload.num_syscalls 442 # Number of system calls
system.cpu.numCycles 122469595 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 90602850 # Number of instructions committed
system.cpu.committedOps 91054081 # Number of ops (including micro ops) committed
system.cpu.discardedOps 2175024 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
system.cpu.cpi 1.351719 # CPI: cycles per instruction
system.cpu.ipc 0.739799 # IPC: instructions per cycle
system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
system.cpu.op_class_0::IntAlu 63822829 70.09% 70.09% # Class of committed instruction
system.cpu.op_class_0::IntMult 10474 0.01% 70.10% # Class of committed instruction
system.cpu.op_class_0::IntDiv 0 0.00% 70.10% # Class of committed instruction
system.cpu.op_class_0::FloatAdd 0 0.00% 70.10% # Class of committed instruction
system.cpu.op_class_0::FloatCmp 0 0.00% 70.10% # Class of committed instruction
system.cpu.op_class_0::FloatCvt 0 0.00% 70.10% # Class of committed instruction
system.cpu.op_class_0::FloatMult 0 0.00% 70.10% # Class of committed instruction
system.cpu.op_class_0::FloatDiv 0 0.00% 70.10% # Class of committed instruction
system.cpu.op_class_0::FloatSqrt 0 0.00% 70.10% # Class of committed instruction
system.cpu.op_class_0::SimdAdd 0 0.00% 70.10% # Class of committed instruction
system.cpu.op_class_0::SimdAddAcc 0 0.00% 70.10% # Class of committed instruction
system.cpu.op_class_0::SimdAlu 0 0.00% 70.10% # Class of committed instruction
system.cpu.op_class_0::SimdCmp 0 0.00% 70.10% # Class of committed instruction
system.cpu.op_class_0::SimdCvt 0 0.00% 70.10% # Class of committed instruction
system.cpu.op_class_0::SimdMisc 0 0.00% 70.10% # Class of committed instruction
system.cpu.op_class_0::SimdMult 0 0.00% 70.10% # Class of committed instruction
system.cpu.op_class_0::SimdMultAcc 0 0.00% 70.10% # Class of committed instruction
system.cpu.op_class_0::SimdShift 0 0.00% 70.10% # Class of committed instruction
system.cpu.op_class_0::SimdShiftAcc 0 0.00% 70.10% # Class of committed instruction
system.cpu.op_class_0::SimdSqrt 0 0.00% 70.10% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAdd 0 0.00% 70.10% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAlu 0 0.00% 70.10% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCmp 0 0.00% 70.10% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCvt 6 0.00% 70.10% # Class of committed instruction
system.cpu.op_class_0::SimdFloatDiv 0 0.00% 70.10% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMisc 15 0.00% 70.10% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMult 0 0.00% 70.10% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMultAcc 2 0.00% 70.10% # Class of committed instruction
system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 70.10% # Class of committed instruction
system.cpu.op_class_0::MemRead 22475911 24.68% 94.79% # Class of committed instruction
system.cpu.op_class_0::MemWrite 4744844 5.21% 100.00% # Class of committed instruction
system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::total 91054081 # Class of committed instruction
system.cpu.tickCycles 109245506 # Number of cycles that the object actually ticked
system.cpu.idleCycles 13224089 # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.replacements 946097 # number of replacements
system.cpu.dcache.tags.tagsinuse 3616.804007 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 26262686 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 950193 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 27.639317 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 20511782500 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 3616.804007 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.883009 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.883009 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 260 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 2253 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 1583 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 55454003 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 55454003 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 21593712 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 21593712 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 4660692 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 4660692 # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data 508 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 508 # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 3887 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 26254404 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 26254404 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 26254912 # number of overall hits
system.cpu.dcache.overall_hits::total 26254912 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 914926 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 914926 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 74289 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 74289 # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data 4 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 4 # number of SoftPFReq misses
system.cpu.dcache.demand_misses::cpu.data 989215 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 989215 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 989219 # number of overall misses
system.cpu.dcache.overall_misses::total 989219 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 11919140000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 11919140000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 2539899500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 2539899500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 14459039500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 14459039500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 14459039500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 14459039500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 22508638 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 22508638 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data 512 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 512 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 27243619 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 27243619 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 27244131 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 27244131 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040648 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.040648 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015689 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.015689 # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.007812 # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total 0.007812 # miss rate for SoftPFReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.036310 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.036310 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.036309 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.036309 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13027.436099 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 13027.436099 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34189.442582 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 34189.442582 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 14616.680398 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 14616.680398 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 14616.621294 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 14616.621294 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks 943278 # number of writebacks
system.cpu.dcache.writebacks::total 943278 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 11500 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 11500 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 27525 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 27525 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 39025 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 39025 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 39025 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 39025 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903426 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 903426 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46764 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 46764 # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 3 # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 950190 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 950190 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 950193 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 950193 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10865506000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 10865506000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1480423500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1480423500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 156500 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 156500 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12345929500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 12345929500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12346086000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 12346086000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040137 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040137 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009876 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009876 # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.005859 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.005859 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034878 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.034878 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034877 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.034877 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12027.001658 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12027.001658 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31657.332564 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31657.332564 # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 52166.666667 # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 52166.666667 # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12993.116640 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 12993.116640 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12993.240321 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 12993.240321 # average overall mshr miss latency
system.cpu.icache.tags.replacements 5 # number of replacements
system.cpu.icache.tags.tagsinuse 689.102041 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 27766889 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 801 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 34665.279650 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 689.102041 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.336476 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.336476 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 796 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 13 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 740 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.388672 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 55536181 # Number of tag accesses
system.cpu.icache.tags.data_accesses 55536181 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 27766889 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 27766889 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 27766889 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 27766889 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 27766889 # number of overall hits
system.cpu.icache.overall_hits::total 27766889 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 801 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 801 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 801 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 801 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 801 # number of overall misses
system.cpu.icache.overall_misses::total 801 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 60228000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 60228000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 60228000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 60228000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 60228000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 60228000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 27767690 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 27767690 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 27767690 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 27767690 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 27767690 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 27767690 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000029 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000029 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000029 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000029 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000029 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000029 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75191.011236 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 75191.011236 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 75191.011236 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 75191.011236 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 75191.011236 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 75191.011236 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks 5 # number of writebacks
system.cpu.icache.writebacks::total 5 # number of writebacks
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 801 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 801 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 801 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 801 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 801 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 801 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 59427000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 59427000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 59427000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 59427000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 59427000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 59427000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000029 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000029 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000029 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74191.011236 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74191.011236 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74191.011236 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 74191.011236 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74191.011236 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 74191.011236 # average overall mshr miss latency
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 10244.686315 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 1833993 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 15556 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 117.896182 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 9355.125797 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.107024 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 215.453494 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.285496 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020572 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.006575 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.312643 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 15556 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 524 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1096 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13876 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.474731 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 15237888 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 15237888 # Number of data accesses
system.cpu.l2cache.WritebackDirty_hits::writebacks 943278 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 943278 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 4 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 4 # number of WritebackClean hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 32220 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 32220 # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 26 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 26 # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 903167 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 903167 # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst 26 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 935387 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 935413 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 26 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 935387 # number of overall hits
system.cpu.l2cache.overall_hits::total 935413 # number of overall hits
system.cpu.l2cache.ReadExReq_misses::cpu.data 14544 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 14544 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 775 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 775 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 262 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 262 # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst 775 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 14806 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 15581 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 775 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 14806 # number of overall misses
system.cpu.l2cache.overall_misses::total 15581 # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1066480500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 1066480500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 57929500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 57929500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 22043500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 22043500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 57929500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 1088524000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 1146453500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 57929500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 1088524000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 1146453500 # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks 943278 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total 943278 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks 4 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 4 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 46764 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 46764 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 801 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 801 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 903429 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 903429 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 801 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 950193 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 950994 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 801 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 950193 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 950994 # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.311008 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.311008 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.967541 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.967541 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000290 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000290 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.967541 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.015582 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.016384 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.967541 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.015582 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.016384 # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73327.867162 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73327.867162 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74747.741935 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74747.741935 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 84135.496183 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 84135.496183 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74747.741935 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73519.113873 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 73580.225916 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74747.741935 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73519.113873 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 73580.225916 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 2 # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::total 2 # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 6 # number of ReadSharedReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::total 6 # number of ReadSharedReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data 6 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 8 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data 6 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 8 # number of overall MSHR hits
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14544 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 14544 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 773 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 773 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 256 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 256 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 773 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 14800 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 15573 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 773 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 14800 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 15573 # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 921040500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 921040500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 50052500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 50052500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 19092500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 19092500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 50052500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 940133000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 990185500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 50052500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 940133000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 990185500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.311008 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.311008 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.965044 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.965044 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000283 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000283 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965044 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015576 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.016375 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965044 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015576 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.016375 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63327.867162 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63327.867162 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64750.970246 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64750.970246 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 74580.078125 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 74580.078125 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64750.970246 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63522.500000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63583.477814 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64750.970246 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63522.500000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63583.477814 # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests 1897096 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 946118 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 150 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadResp 904230 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 943278 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 5 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 2819 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 46764 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 46764 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 801 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 903429 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1607 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2846483 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 2848090 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51584 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 121182144 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 121233728 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)