796 lines
19 KiB
Text
796 lines
19 KiB
Text
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================ Begin RubySystem Configuration Print ================
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Ruby Configuration
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------------------
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protocol: MOSI_SMP_bcast
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compiled_at: 22:51:11, May 4 2009
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RUBY_DEBUG: false
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hostname: piton
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g_RANDOM_SEED: 1
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g_DEADLOCK_THRESHOLD: 500000
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RANDOMIZATION: false
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g_SYNTHETIC_DRIVER: false
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g_DETERMINISTIC_DRIVER: false
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g_FILTERING_ENABLED: false
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g_DISTRIBUTED_PERSISTENT_ENABLED: true
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g_DYNAMIC_TIMEOUT_ENABLED: true
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g_RETRY_THRESHOLD: 1
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g_FIXED_TIMEOUT_LATENCY: 300
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g_trace_warmup_length: 1000000
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g_bash_bandwidth_adaptive_threshold: 0.75
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g_tester_length: 0
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g_synthetic_locks: 2048
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g_deterministic_addrs: 1
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g_SpecifiedGenerator: DetermInvGenerator
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g_callback_counter: 0
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g_NUM_COMPLETIONS_BEFORE_PASS: 0
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g_NUM_SMT_THREADS: 1
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g_think_time: 5
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g_hold_time: 5
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g_wait_time: 5
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PROTOCOL_DEBUG_TRACE: true
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DEBUG_FILTER_STRING: none
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DEBUG_VERBOSITY_STRING: none
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DEBUG_START_TIME: 0
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DEBUG_OUTPUT_FILENAME: none
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SIMICS_RUBY_MULTIPLIER: 4
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OPAL_RUBY_MULTIPLIER: 1
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TRANSACTION_TRACE_ENABLED: false
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USER_MODE_DATA_ONLY: false
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PROFILE_HOT_LINES: false
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PROFILE_ALL_INSTRUCTIONS: false
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PRINT_INSTRUCTION_TRACE: false
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g_DEBUG_CYCLE: 0
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BLOCK_STC: false
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PERFECT_MEMORY_SYSTEM: false
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PERFECT_MEMORY_SYSTEM_LATENCY: 0
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DATA_BLOCK: false
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REMOVE_SINGLE_CYCLE_DCACHE_FAST_PATH: false
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L1_CACHE_ASSOC: 4
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L1_CACHE_NUM_SETS_BITS: 8
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L2_CACHE_ASSOC: 4
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L2_CACHE_NUM_SETS_BITS: 16
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g_MEMORY_SIZE_BYTES: 4294967296
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g_DATA_BLOCK_BYTES: 64
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g_PAGE_SIZE_BYTES: 4096
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g_REPLACEMENT_POLICY: PSEDUO_LRU
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g_NUM_PROCESSORS: 1
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g_NUM_L2_BANKS: 1
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g_NUM_MEMORIES: 1
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g_PROCS_PER_CHIP: 1
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g_NUM_CHIPS: 1
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g_NUM_CHIP_BITS: 0
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g_MEMORY_SIZE_BITS: 32
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g_DATA_BLOCK_BITS: 6
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g_PAGE_SIZE_BITS: 12
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g_NUM_PROCESSORS_BITS: 0
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g_PROCS_PER_CHIP_BITS: 0
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g_NUM_L2_BANKS_BITS: 0
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g_NUM_L2_BANKS_PER_CHIP_BITS: 0
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g_NUM_L2_BANKS_PER_CHIP: 1
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g_NUM_MEMORIES_BITS: 0
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g_NUM_MEMORIES_PER_CHIP: 1
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g_MEMORY_MODULE_BITS: 26
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g_MEMORY_MODULE_BLOCKS: 67108864
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MAP_L2BANKS_TO_LOWEST_BITS: false
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DIRECTORY_CACHE_LATENCY: 6
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NULL_LATENCY: 1
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ISSUE_LATENCY: 2
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CACHE_RESPONSE_LATENCY: 12
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L2_RESPONSE_LATENCY: 6
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L2_TAG_LATENCY: 6
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L1_RESPONSE_LATENCY: 3
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MEMORY_RESPONSE_LATENCY_MINUS_2: 158
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DIRECTORY_LATENCY: 80
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NETWORK_LINK_LATENCY: 1
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COPY_HEAD_LATENCY: 4
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ON_CHIP_LINK_LATENCY: 1
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RECYCLE_LATENCY: 10
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L2_RECYCLE_LATENCY: 5
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TIMER_LATENCY: 10000
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TBE_RESPONSE_LATENCY: 1
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PERIODIC_TIMER_WAKEUPS: true
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PROFILE_EXCEPTIONS: false
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PROFILE_XACT: true
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PROFILE_NONXACT: false
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XACT_DEBUG: true
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XACT_DEBUG_LEVEL: 1
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XACT_MEMORY: false
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XACT_ENABLE_TOURMALINE: false
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XACT_NUM_CURRENT: 0
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XACT_LAST_UPDATE: 0
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XACT_ISOLATION_CHECK: false
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PERFECT_FILTER: true
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READ_WRITE_FILTER: Perfect_
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PERFECT_VIRTUAL_FILTER: true
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VIRTUAL_READ_WRITE_FILTER: Perfect_
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PERFECT_SUMMARY_FILTER: true
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SUMMARY_READ_WRITE_FILTER: Perfect_
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XACT_EAGER_CD: true
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XACT_LAZY_VM: false
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XACT_CONFLICT_RES: BASE
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XACT_VISUALIZER: false
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XACT_COMMIT_TOKEN_LATENCY: 0
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XACT_NO_BACKOFF: false
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XACT_LOG_BUFFER_SIZE: 0
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XACT_STORE_PREDICTOR_HISTORY: 256
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XACT_STORE_PREDICTOR_ENTRIES: 256
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XACT_STORE_PREDICTOR_THRESHOLD: 4
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XACT_FIRST_ACCESS_COST: 0
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XACT_FIRST_PAGE_ACCESS_COST: 0
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ENABLE_MAGIC_WAITING: false
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ENABLE_WATCHPOINT: false
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XACT_ENABLE_VIRTUALIZATION_LOGTM_SE: false
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ATMTP_ENABLED: false
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ATMTP_ABORT_ON_NON_XACT_INST: false
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ATMTP_ALLOW_SAVE_RESTORE_IN_XACT: false
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ATMTP_XACT_MAX_STORES: 32
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ATMTP_DEBUG_LEVEL: 0
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L1_REQUEST_LATENCY: 2
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L2_REQUEST_LATENCY: 4
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SINGLE_ACCESS_L2_BANKS: true
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SEQUENCER_TO_CONTROLLER_LATENCY: 4
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L1CACHE_TRANSITIONS_PER_RUBY_CYCLE: 32
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L2CACHE_TRANSITIONS_PER_RUBY_CYCLE: 32
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DIRECTORY_TRANSITIONS_PER_RUBY_CYCLE: 32
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g_SEQUENCER_OUTSTANDING_REQUESTS: 16
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NUMBER_OF_TBES: 128
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NUMBER_OF_L1_TBES: 32
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NUMBER_OF_L2_TBES: 32
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FINITE_BUFFERING: false
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FINITE_BUFFER_SIZE: 3
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PROCESSOR_BUFFER_SIZE: 10
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PROTOCOL_BUFFER_SIZE: 32
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TSO: false
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g_NETWORK_TOPOLOGY: HIERARCHICAL_SWITCH
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g_CACHE_DESIGN: NUCA
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g_endpoint_bandwidth: 10000
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g_adaptive_routing: true
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NUMBER_OF_VIRTUAL_NETWORKS: 4
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FAN_OUT_DEGREE: 4
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g_PRINT_TOPOLOGY: true
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XACT_LENGTH: 0
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XACT_SIZE: 0
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ABORT_RETRY_TIME: 0
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g_GARNET_NETWORK: false
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g_DETAIL_NETWORK: false
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g_NETWORK_TESTING: false
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g_FLIT_SIZE: 16
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g_NUM_PIPE_STAGES: 4
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g_VCS_PER_CLASS: 4
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g_BUFFER_SIZE: 4
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MEM_BUS_CYCLE_MULTIPLIER: 10
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BANKS_PER_RANK: 8
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RANKS_PER_DIMM: 2
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DIMMS_PER_CHANNEL: 2
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BANK_BIT_0: 8
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RANK_BIT_0: 11
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DIMM_BIT_0: 12
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BANK_QUEUE_SIZE: 12
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BANK_BUSY_TIME: 11
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RANK_RANK_DELAY: 1
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READ_WRITE_DELAY: 2
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BASIC_BUS_BUSY_TIME: 2
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MEM_CTL_LATENCY: 12
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REFRESH_PERIOD: 1560
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TFAW: 0
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MEM_RANDOM_ARBITRATE: 0
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MEM_FIXED_DELAY: 0
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Chip Config
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-----------
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Total_Chips: 1
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L1Cache_TBEs numberPerChip: 1
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TBEs_per_TBETable: 128
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L1Cache_L1IcacheMemory numberPerChip: 1
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Cache config: L1Cache_0_L1I
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cache_associativity: 4
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num_cache_sets_bits: 8
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num_cache_sets: 256
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cache_set_size_bytes: 16384
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cache_set_size_Kbytes: 16
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cache_set_size_Mbytes: 0.015625
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cache_size_bytes: 65536
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cache_size_Kbytes: 64
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cache_size_Mbytes: 0.0625
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L1Cache_L1DcacheMemory numberPerChip: 1
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Cache config: L1Cache_0_L1D
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cache_associativity: 4
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num_cache_sets_bits: 8
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num_cache_sets: 256
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cache_set_size_bytes: 16384
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cache_set_size_Kbytes: 16
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cache_set_size_Mbytes: 0.015625
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cache_size_bytes: 65536
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cache_size_Kbytes: 64
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cache_size_Mbytes: 0.0625
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L1Cache_L2cacheMemory numberPerChip: 1
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Cache config: L1Cache_0_L2
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cache_associativity: 4
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num_cache_sets_bits: 16
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num_cache_sets: 65536
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cache_set_size_bytes: 4194304
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cache_set_size_Kbytes: 4096
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cache_set_size_Mbytes: 4
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cache_size_bytes: 16777216
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cache_size_Kbytes: 16384
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cache_size_Mbytes: 16
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L1Cache_mandatoryQueue numberPerChip: 1
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L1Cache_sequencer numberPerChip: 1
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sequencer: Sequencer - SC
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max_outstanding_requests: 16
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L1Cache_storeBuffer numberPerChip: 1
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Store buffer entries: 128 (Only valid if TSO is enabled)
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Directory_directory numberPerChip: 1
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Memory config:
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memory_bits: 32
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memory_size_bytes: 4294967296
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memory_size_Kbytes: 4.1943e+06
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memory_size_Mbytes: 4096
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memory_size_Gbytes: 4
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module_bits: 26
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module_size_lines: 67108864
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module_size_bytes: 4294967296
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module_size_Kbytes: 4.1943e+06
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module_size_Mbytes: 4096
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Network Configuration
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---------------------
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network: SIMPLE_NETWORK
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topology: HIERARCHICAL_SWITCH
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virtual_net_0: active, ordered
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virtual_net_1: active, unordered
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virtual_net_2: inactive
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virtual_net_3: inactive
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--- Begin Topology Print ---
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Topology print ONLY indicates the _NETWORK_ latency between two machines
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It does NOT include the latency within the machines
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L1Cache-0 Network Latencies
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L1Cache-0 -> Directory-0 net_lat: 5
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Directory-0 Network Latencies
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Directory-0 -> L1Cache-0 net_lat: 5
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--- End Topology Print ---
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Profiler Configuration
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----------------------
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periodic_stats_period: 1000000
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================ End RubySystem Configuration Print ================
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Real time: May/05/2009 07:34:03
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Profiler Stats
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--------------
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Elapsed_time_in_seconds: 0
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Elapsed_time_in_minutes: 0
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Elapsed_time_in_hours: 0
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Elapsed_time_in_days: 0
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Virtual_time_in_seconds: 0.15
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Virtual_time_in_minutes: 0.0025
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Virtual_time_in_hours: 4.16667e-05
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Virtual_time_in_days: 4.16667e-05
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Ruby_current_time: 3215001
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Ruby_start_time: 1
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Ruby_cycles: 3215000
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mbytes_resident: 34.6523
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mbytes_total: 195.43
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resident_ratio: 0.177334
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Total_misses: 0
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total_misses: 0 [ 0 ]
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user_misses: 0 [ 0 ]
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supervisor_misses: 0 [ 0 ]
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instruction_executed: 1 [ 1 ]
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cycles_executed: 1 [ 1 ]
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cycles_per_instruction: 3.215e+06 [ 3.215e+06 ]
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misses_per_thousand_instructions: 0 [ 0 ]
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transactions_started: 0 [ 0 ]
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transactions_ended: 0 [ 0 ]
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instructions_per_transaction: 0 [ 0 ]
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cycles_per_transaction: 0 [ 0 ]
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misses_per_transaction: 0 [ 0 ]
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L1D_cache cache stats:
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L1D_cache_total_misses: 0
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L1D_cache_total_demand_misses: 0
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L1D_cache_total_prefetches: 0
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L1D_cache_total_sw_prefetches: 0
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L1D_cache_total_hw_prefetches: 0
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L1D_cache_misses_per_transaction: 0
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L1D_cache_misses_per_instruction: 0
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L1D_cache_instructions_per_misses: NaN
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L1D_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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L1I_cache cache stats:
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L1I_cache_total_misses: 0
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L1I_cache_total_demand_misses: 0
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L1I_cache_total_prefetches: 0
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L1I_cache_total_sw_prefetches: 0
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L1I_cache_total_hw_prefetches: 0
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L1I_cache_misses_per_transaction: 0
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L1I_cache_misses_per_instruction: 0
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L1I_cache_instructions_per_misses: NaN
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L1I_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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L2_cache cache stats:
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L2_cache_total_misses: 0
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L2_cache_total_demand_misses: 0
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L2_cache_total_prefetches: 0
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L2_cache_total_sw_prefetches: 0
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L2_cache_total_hw_prefetches: 0
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L2_cache_misses_per_transaction: 0
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L2_cache_misses_per_instruction: 0
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L2_cache_instructions_per_misses: NaN
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L2_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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Busy Controller Counts:
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L1Cache-0:0
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||
|
|
Directory-0:0
|
||
|
|
|
||
|
|
Busy Bank Count:0
|
||
|
|
|
||
|
|
L1TBE_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||
|
|
L2TBE_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||
|
|
StopTable_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||
|
|
sequencer_requests_outstanding: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||
|
|
store_buffer_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||
|
|
unique_blocks_in_store_buffer: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||
|
|
|
||
|
|
All Non-Zero Cycle Demand Cache Accesses
|
||
|
|
----------------------------------------
|
||
|
|
miss_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||
|
|
miss_latency_L2Miss: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||
|
|
|
||
|
|
All Non-Zero Cycle SW Prefetch Requests
|
||
|
|
------------------------------------
|
||
|
|
prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||
|
|
prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||
|
|
multicast_retries: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||
|
|
gets_mask_prediction_count: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||
|
|
getx_mask_prediction_count: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||
|
|
explicit_training_mask: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||
|
|
|
||
|
|
Request vs. RubySystem State Profile
|
||
|
|
--------------------------------
|
||
|
|
|
||
|
|
|
||
|
|
filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||
|
|
|
||
|
|
Message Delayed Cycles
|
||
|
|
----------------------
|
||
|
|
Total_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||
|
|
Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||
|
|
virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||
|
|
virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||
|
|
virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||
|
|
virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||
|
|
|
||
|
|
Resource Usage
|
||
|
|
--------------
|
||
|
|
page_size: 4096
|
||
|
|
user_time: 0
|
||
|
|
system_time: 0
|
||
|
|
page_reclaims: 9071
|
||
|
|
page_faults: 0
|
||
|
|
swaps: 0
|
||
|
|
block_inputs: 0
|
||
|
|
block_outputs: 56
|
||
|
|
MessageBuffer: [Chip 0 0, L1Cache, mandatoryQueue_in] stats - msgs:0 full:0
|
||
|
|
|
||
|
|
Network Stats
|
||
|
|
-------------
|
||
|
|
|
||
|
|
switch_0_inlinks: 1
|
||
|
|
switch_0_outlinks: 1
|
||
|
|
links_utilized_percent_switch_0: 0
|
||
|
|
links_utilized_percent_switch_0_link_0: 0 bw: 10000 base_latency: 1
|
||
|
|
|
||
|
|
|
||
|
|
switch_1_inlinks: 1
|
||
|
|
switch_1_outlinks: 1
|
||
|
|
links_utilized_percent_switch_1: 0
|
||
|
|
links_utilized_percent_switch_1_link_0: 0 bw: 10000 base_latency: 1
|
||
|
|
|
||
|
|
|
||
|
|
switch_2_inlinks: 2
|
||
|
|
switch_2_outlinks: 2
|
||
|
|
links_utilized_percent_switch_2: 0
|
||
|
|
links_utilized_percent_switch_2_link_0: 0 bw: 10000 base_latency: 1
|
||
|
|
links_utilized_percent_switch_2_link_1: 0 bw: 10000 base_latency: 1
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
Chip Stats
|
||
|
|
----------
|
||
|
|
|
||
|
|
--- L1Cache ---
|
||
|
|
- Event Counts -
|
||
|
|
Load 0
|
||
|
|
Ifetch 0
|
||
|
|
Store 0
|
||
|
|
L1_to_L2 0
|
||
|
|
L2_to_L1D 0
|
||
|
|
L2_to_L1I 0
|
||
|
|
L2_Replacement 0
|
||
|
|
Own_GETS 0
|
||
|
|
Own_GET_INSTR 0
|
||
|
|
Own_GETX 0
|
||
|
|
Own_PUTX 0
|
||
|
|
Other_GETS 0
|
||
|
|
Other_GET_INSTR 0
|
||
|
|
Other_GETX 0
|
||
|
|
Other_PUTX 0
|
||
|
|
Data 0
|
||
|
|
|
||
|
|
- Transitions -
|
||
|
|
NP Load 0 <--
|
||
|
|
NP Ifetch 0 <--
|
||
|
|
NP Store 0 <--
|
||
|
|
NP Other_GETS 0 <--
|
||
|
|
NP Other_GET_INSTR 0 <--
|
||
|
|
NP Other_GETX 0 <--
|
||
|
|
NP Other_PUTX 0 <--
|
||
|
|
|
||
|
|
I Load 0 <--
|
||
|
|
I Ifetch 0 <--
|
||
|
|
I Store 0 <--
|
||
|
|
I L1_to_L2 0 <--
|
||
|
|
I L2_to_L1D 0 <--
|
||
|
|
I L2_to_L1I 0 <--
|
||
|
|
I L2_Replacement 0 <--
|
||
|
|
I Other_GETS 0 <--
|
||
|
|
I Other_GET_INSTR 0 <--
|
||
|
|
I Other_GETX 0 <--
|
||
|
|
I Other_PUTX 0 <--
|
||
|
|
|
||
|
|
S Load 0 <--
|
||
|
|
S Ifetch 0 <--
|
||
|
|
S Store 0 <--
|
||
|
|
S L1_to_L2 0 <--
|
||
|
|
S L2_to_L1D 0 <--
|
||
|
|
S L2_to_L1I 0 <--
|
||
|
|
S L2_Replacement 0 <--
|
||
|
|
S Other_GETS 0 <--
|
||
|
|
S Other_GET_INSTR 0 <--
|
||
|
|
S Other_GETX 0 <--
|
||
|
|
S Other_PUTX 0 <--
|
||
|
|
|
||
|
|
O Load 0 <--
|
||
|
|
O Ifetch 0 <--
|
||
|
|
O Store 0 <--
|
||
|
|
O L1_to_L2 0 <--
|
||
|
|
O L2_to_L1D 0 <--
|
||
|
|
O L2_to_L1I 0 <--
|
||
|
|
O L2_Replacement 0 <--
|
||
|
|
O Other_GETS 0 <--
|
||
|
|
O Other_GET_INSTR 0 <--
|
||
|
|
O Other_GETX 0 <--
|
||
|
|
O Other_PUTX 0 <--
|
||
|
|
|
||
|
|
M Load 0 <--
|
||
|
|
M Ifetch 0 <--
|
||
|
|
M Store 0 <--
|
||
|
|
M L1_to_L2 0 <--
|
||
|
|
M L2_to_L1D 0 <--
|
||
|
|
M L2_to_L1I 0 <--
|
||
|
|
M L2_Replacement 0 <--
|
||
|
|
M Other_GETS 0 <--
|
||
|
|
M Other_GET_INSTR 0 <--
|
||
|
|
M Other_GETX 0 <--
|
||
|
|
M Other_PUTX 0 <--
|
||
|
|
|
||
|
|
IS_AD Load 0 <--
|
||
|
|
IS_AD Ifetch 0 <--
|
||
|
|
IS_AD Store 0 <--
|
||
|
|
IS_AD L1_to_L2 0 <--
|
||
|
|
IS_AD L2_to_L1D 0 <--
|
||
|
|
IS_AD L2_to_L1I 0 <--
|
||
|
|
IS_AD L2_Replacement 0 <--
|
||
|
|
IS_AD Own_GETS 0 <--
|
||
|
|
IS_AD Own_GET_INSTR 0 <--
|
||
|
|
IS_AD Other_GETS 0 <--
|
||
|
|
IS_AD Other_GET_INSTR 0 <--
|
||
|
|
IS_AD Other_GETX 0 <--
|
||
|
|
IS_AD Other_PUTX 0 <--
|
||
|
|
IS_AD Data 0 <--
|
||
|
|
|
||
|
|
IM_AD Load 0 <--
|
||
|
|
IM_AD Ifetch 0 <--
|
||
|
|
IM_AD Store 0 <--
|
||
|
|
IM_AD L1_to_L2 0 <--
|
||
|
|
IM_AD L2_to_L1D 0 <--
|
||
|
|
IM_AD L2_to_L1I 0 <--
|
||
|
|
IM_AD L2_Replacement 0 <--
|
||
|
|
IM_AD Own_GETX 0 <--
|
||
|
|
IM_AD Other_GETS 0 <--
|
||
|
|
IM_AD Other_GET_INSTR 0 <--
|
||
|
|
IM_AD Other_GETX 0 <--
|
||
|
|
IM_AD Other_PUTX 0 <--
|
||
|
|
IM_AD Data 0 <--
|
||
|
|
|
||
|
|
SM_AD Load 0 <--
|
||
|
|
SM_AD Ifetch 0 <--
|
||
|
|
SM_AD Store 0 <--
|
||
|
|
SM_AD L1_to_L2 0 <--
|
||
|
|
SM_AD L2_to_L1D 0 <--
|
||
|
|
SM_AD L2_to_L1I 0 <--
|
||
|
|
SM_AD L2_Replacement 0 <--
|
||
|
|
SM_AD Own_GETX 0 <--
|
||
|
|
SM_AD Other_GETS 0 <--
|
||
|
|
SM_AD Other_GET_INSTR 0 <--
|
||
|
|
SM_AD Other_GETX 0 <--
|
||
|
|
SM_AD Other_PUTX 0 <--
|
||
|
|
SM_AD Data 0 <--
|
||
|
|
|
||
|
|
OM_A Load 0 <--
|
||
|
|
OM_A Ifetch 0 <--
|
||
|
|
OM_A Store 0 <--
|
||
|
|
OM_A L1_to_L2 0 <--
|
||
|
|
OM_A L2_to_L1D 0 <--
|
||
|
|
OM_A L2_to_L1I 0 <--
|
||
|
|
OM_A L2_Replacement 0 <--
|
||
|
|
OM_A Own_GETX 0 <--
|
||
|
|
OM_A Other_GETS 0 <--
|
||
|
|
OM_A Other_GET_INSTR 0 <--
|
||
|
|
OM_A Other_GETX 0 <--
|
||
|
|
OM_A Other_PUTX 0 <--
|
||
|
|
OM_A Data 0 <--
|
||
|
|
|
||
|
|
IS_A Load 0 <--
|
||
|
|
IS_A Ifetch 0 <--
|
||
|
|
IS_A Store 0 <--
|
||
|
|
IS_A L1_to_L2 0 <--
|
||
|
|
IS_A L2_to_L1D 0 <--
|
||
|
|
IS_A L2_to_L1I 0 <--
|
||
|
|
IS_A L2_Replacement 0 <--
|
||
|
|
IS_A Own_GETS 0 <--
|
||
|
|
IS_A Own_GET_INSTR 0 <--
|
||
|
|
IS_A Other_GETS 0 <--
|
||
|
|
IS_A Other_GET_INSTR 0 <--
|
||
|
|
IS_A Other_GETX 0 <--
|
||
|
|
IS_A Other_PUTX 0 <--
|
||
|
|
|
||
|
|
IM_A Load 0 <--
|
||
|
|
IM_A Ifetch 0 <--
|
||
|
|
IM_A Store 0 <--
|
||
|
|
IM_A L1_to_L2 0 <--
|
||
|
|
IM_A L2_to_L1D 0 <--
|
||
|
|
IM_A L2_to_L1I 0 <--
|
||
|
|
IM_A L2_Replacement 0 <--
|
||
|
|
IM_A Own_GETX 0 <--
|
||
|
|
IM_A Other_GETS 0 <--
|
||
|
|
IM_A Other_GET_INSTR 0 <--
|
||
|
|
IM_A Other_GETX 0 <--
|
||
|
|
IM_A Other_PUTX 0 <--
|
||
|
|
|
||
|
|
SM_A Load 0 <--
|
||
|
|
SM_A Ifetch 0 <--
|
||
|
|
SM_A Store 0 <--
|
||
|
|
SM_A L1_to_L2 0 <--
|
||
|
|
SM_A L2_to_L1D 0 <--
|
||
|
|
SM_A L2_to_L1I 0 <--
|
||
|
|
SM_A L2_Replacement 0 <--
|
||
|
|
SM_A Own_GETX 0 <--
|
||
|
|
SM_A Other_GETS 0 <--
|
||
|
|
SM_A Other_GET_INSTR 0 <--
|
||
|
|
SM_A Other_GETX 0 <--
|
||
|
|
SM_A Other_PUTX 0 <--
|
||
|
|
|
||
|
|
MI_A Load 0 <--
|
||
|
|
MI_A Ifetch 0 <--
|
||
|
|
MI_A Store 0 <--
|
||
|
|
MI_A L1_to_L2 0 <--
|
||
|
|
MI_A L2_to_L1D 0 <--
|
||
|
|
MI_A L2_to_L1I 0 <--
|
||
|
|
MI_A L2_Replacement 0 <--
|
||
|
|
MI_A Own_PUTX 0 <--
|
||
|
|
MI_A Other_GETS 0 <--
|
||
|
|
MI_A Other_GET_INSTR 0 <--
|
||
|
|
MI_A Other_GETX 0 <--
|
||
|
|
MI_A Other_PUTX 0 <--
|
||
|
|
|
||
|
|
OI_A Load 0 <--
|
||
|
|
OI_A Ifetch 0 <--
|
||
|
|
OI_A Store 0 <--
|
||
|
|
OI_A L1_to_L2 0 <--
|
||
|
|
OI_A L2_to_L1D 0 <--
|
||
|
|
OI_A L2_to_L1I 0 <--
|
||
|
|
OI_A L2_Replacement 0 <--
|
||
|
|
OI_A Own_PUTX 0 <--
|
||
|
|
OI_A Other_GETS 0 <--
|
||
|
|
OI_A Other_GET_INSTR 0 <--
|
||
|
|
OI_A Other_GETX 0 <--
|
||
|
|
OI_A Other_PUTX 0 <--
|
||
|
|
|
||
|
|
II_A Load 0 <--
|
||
|
|
II_A Ifetch 0 <--
|
||
|
|
II_A Store 0 <--
|
||
|
|
II_A L1_to_L2 0 <--
|
||
|
|
II_A L2_to_L1D 0 <--
|
||
|
|
II_A L2_to_L1I 0 <--
|
||
|
|
II_A L2_Replacement 0 <--
|
||
|
|
II_A Own_PUTX 0 <--
|
||
|
|
II_A Other_GETS 0 <--
|
||
|
|
II_A Other_GET_INSTR 0 <--
|
||
|
|
II_A Other_GETX 0 <--
|
||
|
|
II_A Other_PUTX 0 <--
|
||
|
|
|
||
|
|
IS_D Load 0 <--
|
||
|
|
IS_D Ifetch 0 <--
|
||
|
|
IS_D Store 0 <--
|
||
|
|
IS_D L1_to_L2 0 <--
|
||
|
|
IS_D L2_to_L1D 0 <--
|
||
|
|
IS_D L2_to_L1I 0 <--
|
||
|
|
IS_D L2_Replacement 0 <--
|
||
|
|
IS_D Other_GETS 0 <--
|
||
|
|
IS_D Other_GET_INSTR 0 <--
|
||
|
|
IS_D Other_GETX 0 <--
|
||
|
|
IS_D Other_PUTX 0 <--
|
||
|
|
IS_D Data 0 <--
|
||
|
|
|
||
|
|
IS_D_I Load 0 <--
|
||
|
|
IS_D_I Ifetch 0 <--
|
||
|
|
IS_D_I Store 0 <--
|
||
|
|
IS_D_I L1_to_L2 0 <--
|
||
|
|
IS_D_I L2_to_L1D 0 <--
|
||
|
|
IS_D_I L2_to_L1I 0 <--
|
||
|
|
IS_D_I L2_Replacement 0 <--
|
||
|
|
IS_D_I Other_GETS 0 <--
|
||
|
|
IS_D_I Other_GET_INSTR 0 <--
|
||
|
|
IS_D_I Other_GETX 0 <--
|
||
|
|
IS_D_I Other_PUTX 0 <--
|
||
|
|
IS_D_I Data 0 <--
|
||
|
|
|
||
|
|
IM_D Load 0 <--
|
||
|
|
IM_D Ifetch 0 <--
|
||
|
|
IM_D Store 0 <--
|
||
|
|
IM_D L1_to_L2 0 <--
|
||
|
|
IM_D L2_to_L1D 0 <--
|
||
|
|
IM_D L2_to_L1I 0 <--
|
||
|
|
IM_D L2_Replacement 0 <--
|
||
|
|
IM_D Other_GETS 0 <--
|
||
|
|
IM_D Other_GET_INSTR 0 <--
|
||
|
|
IM_D Other_GETX 0 <--
|
||
|
|
IM_D Other_PUTX 0 <--
|
||
|
|
IM_D Data 0 <--
|
||
|
|
|
||
|
|
IM_D_O Load 0 <--
|
||
|
|
IM_D_O Ifetch 0 <--
|
||
|
|
IM_D_O Store 0 <--
|
||
|
|
IM_D_O L1_to_L2 0 <--
|
||
|
|
IM_D_O L2_to_L1D 0 <--
|
||
|
|
IM_D_O L2_to_L1I 0 <--
|
||
|
|
IM_D_O L2_Replacement 0 <--
|
||
|
|
IM_D_O Other_GETS 0 <--
|
||
|
|
IM_D_O Other_GET_INSTR 0 <--
|
||
|
|
IM_D_O Other_GETX 0 <--
|
||
|
|
IM_D_O Other_PUTX 0 <--
|
||
|
|
IM_D_O Data 0 <--
|
||
|
|
|
||
|
|
IM_D_I Load 0 <--
|
||
|
|
IM_D_I Ifetch 0 <--
|
||
|
|
IM_D_I Store 0 <--
|
||
|
|
IM_D_I L1_to_L2 0 <--
|
||
|
|
IM_D_I L2_to_L1D 0 <--
|
||
|
|
IM_D_I L2_to_L1I 0 <--
|
||
|
|
IM_D_I L2_Replacement 0 <--
|
||
|
|
IM_D_I Other_GETS 0 <--
|
||
|
|
IM_D_I Other_GET_INSTR 0 <--
|
||
|
|
IM_D_I Other_GETX 0 <--
|
||
|
|
IM_D_I Other_PUTX 0 <--
|
||
|
|
IM_D_I Data 0 <--
|
||
|
|
|
||
|
|
IM_D_OI Load 0 <--
|
||
|
|
IM_D_OI Ifetch 0 <--
|
||
|
|
IM_D_OI Store 0 <--
|
||
|
|
IM_D_OI L1_to_L2 0 <--
|
||
|
|
IM_D_OI L2_to_L1D 0 <--
|
||
|
|
IM_D_OI L2_to_L1I 0 <--
|
||
|
|
IM_D_OI L2_Replacement 0 <--
|
||
|
|
IM_D_OI Other_GETS 0 <--
|
||
|
|
IM_D_OI Other_GET_INSTR 0 <--
|
||
|
|
IM_D_OI Other_GETX 0 <--
|
||
|
|
IM_D_OI Other_PUTX 0 <--
|
||
|
|
IM_D_OI Data 0 <--
|
||
|
|
|
||
|
|
SM_D Load 0 <--
|
||
|
|
SM_D Ifetch 0 <--
|
||
|
|
SM_D Store 0 <--
|
||
|
|
SM_D L1_to_L2 0 <--
|
||
|
|
SM_D L2_to_L1D 0 <--
|
||
|
|
SM_D L2_to_L1I 0 <--
|
||
|
|
SM_D L2_Replacement 0 <--
|
||
|
|
SM_D Other_GETS 0 <--
|
||
|
|
SM_D Other_GET_INSTR 0 <--
|
||
|
|
SM_D Other_GETX 0 <--
|
||
|
|
SM_D Other_PUTX 0 <--
|
||
|
|
SM_D Data 0 <--
|
||
|
|
|
||
|
|
SM_D_O Load 0 <--
|
||
|
|
SM_D_O Ifetch 0 <--
|
||
|
|
SM_D_O Store 0 <--
|
||
|
|
SM_D_O L1_to_L2 0 <--
|
||
|
|
SM_D_O L2_to_L1D 0 <--
|
||
|
|
SM_D_O L2_to_L1I 0 <--
|
||
|
|
SM_D_O L2_Replacement 0 <--
|
||
|
|
SM_D_O Other_GETS 0 <--
|
||
|
|
SM_D_O Other_GET_INSTR 0 <--
|
||
|
|
SM_D_O Other_GETX 0 <--
|
||
|
|
SM_D_O Other_PUTX 0 <--
|
||
|
|
SM_D_O Data 0 <--
|
||
|
|
|
||
|
|
--- Directory ---
|
||
|
|
- Event Counts -
|
||
|
|
OtherAddress 0
|
||
|
|
GETS 0
|
||
|
|
GET_INSTR 0
|
||
|
|
GETX 0
|
||
|
|
PUTX_Owner 0
|
||
|
|
PUTX_NotOwner 0
|
||
|
|
|
||
|
|
- Transitions -
|
||
|
|
C OtherAddress 0 <--
|
||
|
|
C GETS 0 <--
|
||
|
|
C GET_INSTR 0 <--
|
||
|
|
C GETX 0 <--
|
||
|
|
|
||
|
|
I GETS 0 <--
|
||
|
|
I GET_INSTR 0 <--
|
||
|
|
I GETX 0 <--
|
||
|
|
I PUTX_NotOwner 0 <--
|
||
|
|
|
||
|
|
S GETS 0 <--
|
||
|
|
S GET_INSTR 0 <--
|
||
|
|
S GETX 0 <--
|
||
|
|
S PUTX_NotOwner 0 <--
|
||
|
|
|
||
|
|
SS GETS 0 <--
|
||
|
|
SS GET_INSTR 0 <--
|
||
|
|
SS GETX 0 <--
|
||
|
|
SS PUTX_NotOwner 0 <--
|
||
|
|
|
||
|
|
OS GETS 0 <--
|
||
|
|
OS GET_INSTR 0 <--
|
||
|
|
OS GETX 0 <--
|
||
|
|
OS PUTX_Owner 0 <--
|
||
|
|
OS PUTX_NotOwner 0 <--
|
||
|
|
|
||
|
|
OSS GETS 0 <--
|
||
|
|
OSS GET_INSTR 0 <--
|
||
|
|
OSS GETX 0 <--
|
||
|
|
OSS PUTX_Owner 0 <--
|
||
|
|
OSS PUTX_NotOwner 0 <--
|
||
|
|
|
||
|
|
M GETS 0 <--
|
||
|
|
M GET_INSTR 0 <--
|
||
|
|
M GETX 0 <--
|
||
|
|
M PUTX_Owner 0 <--
|
||
|
|
M PUTX_NotOwner 0 <--
|
||
|
|
|