426 lines
13 KiB
C++
426 lines
13 KiB
C++
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/*
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* Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* $Id$
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*/
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#ifndef COMPONENTMAPPINGFNS_H
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#define COMPONENTMAPPINGFNS_H
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#include "Global.hh"
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#include "RubyConfig.hh"
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#include "NodeID.hh"
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#include "MachineID.hh"
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#include "Address.hh"
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#include "Set.hh"
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#include "NetDest.hh"
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#include "GenericMachineType.hh"
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#ifdef MACHINETYPE_L1Cache
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#define MACHINETYPE_L1CACHE_ENUM MachineType_L1Cache
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#else
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#define MACHINETYPE_L1CACHE_ENUM MachineType_NUM
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#endif
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#ifdef MACHINETYPE_L2Cache
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#define MACHINETYPE_L2CACHE_ENUM MachineType_L2Cache
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#else
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#define MACHINETYPE_L2CACHE_ENUM MachineType_NUM
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#endif
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#ifdef MACHINETYPE_L3Cache
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#define MACHINETYPE_L3CACHE_ENUM MachineType_L3Cache
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#else
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#define MACHINETYPE_L3CACHE_ENUM MachineType_NUM
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#endif
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#ifdef MACHINETYPE_PersistentArbiter
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#define MACHINETYPE_PERSISTENTARBITER_ENUM MachineType_PersistentArbiter
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#else
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#define MACHINETYPE_PERSISTENTARBITER_ENUM MachineType_NUM
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#endif
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#ifdef MACHINETYPE_Collector
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#define MACHINETYPE_COLLECTOR_ENUM MachineType_Collector
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#else
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#define MACHINETYPE_COLLECTOR_ENUM MachineType_NUM
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#endif
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// used to determine the correct L1 set
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// input parameters are the address and number of set bits for the L1 cache
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// returns a value between 0 and the total number of L1 cache sets
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inline
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int map_address_to_L1CacheSet(const Address& addr, int cache_num_set_bits)
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{
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return addr.bitSelect(RubyConfig::dataBlockBits(),
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RubyConfig::dataBlockBits()+cache_num_set_bits-1);
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}
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// used to determine the correct L2 set
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// input parameters are the address and number of set bits for the L2 cache
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// returns a value between 0 and the total number of L2 cache sets
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inline
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int map_address_to_L2CacheSet(const Address& addr, int cache_num_set_bits)
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{
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assert(cache_num_set_bits == L2_CACHE_NUM_SETS_BITS); // ensure the l2 bank mapping functions agree with l2 set bits
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if (MAP_L2BANKS_TO_LOWEST_BITS) {
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return addr.bitSelect(RubyConfig::dataBlockBits()+RubyConfig::L2CachePerChipBits(),
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RubyConfig::dataBlockBits()+RubyConfig::L2CachePerChipBits()+cache_num_set_bits-1);
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} else {
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return addr.bitSelect(RubyConfig::dataBlockBits(),
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RubyConfig::dataBlockBits()+cache_num_set_bits-1);
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}
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}
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// input parameter is the base ruby node of the L1 cache
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// returns a value between 0 and total_L2_Caches_within_the_system
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inline
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MachineID map_L1CacheMachId_to_L2Cache(const Address& addr, MachineID L1CacheMachId)
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{
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int L2bank = 0;
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MachineID mach = {MACHINETYPE_L2CACHE_ENUM, 0};
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if (RubyConfig::L2CachePerChipBits() > 0) {
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if (MAP_L2BANKS_TO_LOWEST_BITS) {
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L2bank = addr.bitSelect(RubyConfig::dataBlockBits(),
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RubyConfig::dataBlockBits()+RubyConfig::L2CachePerChipBits()-1);
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} else {
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L2bank = addr.bitSelect(RubyConfig::dataBlockBits()+L2_CACHE_NUM_SETS_BITS,
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RubyConfig::dataBlockBits()+L2_CACHE_NUM_SETS_BITS+RubyConfig::L2CachePerChipBits()-1);
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}
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}
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assert(L2bank < RubyConfig::numberOfL2CachePerChip());
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assert(L2bank >= 0);
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mach.num = RubyConfig::L1CacheNumToL2Base(L1CacheMachId.num)*RubyConfig::numberOfL2CachePerChip() // base #
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+ L2bank; // bank #
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assert(mach.num < RubyConfig::numberOfL2Cache());
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return mach;
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}
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// used to determine the correct L2 bank
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// input parameter is the base ruby node of the L2 cache
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// returns a value between 0 and total_L2_Caches_within_the_system
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inline
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MachineID map_L2ChipId_to_L2Cache(const Address& addr, NodeID L2ChipId)
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{
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assert(L2ChipId < RubyConfig::numberOfChips());
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int L2bank = 0;
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MachineID mach = {MACHINETYPE_L2CACHE_ENUM, 0};
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if (RubyConfig::L2CachePerChipBits() > 0) {
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if (MAP_L2BANKS_TO_LOWEST_BITS) {
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L2bank = addr.bitSelect(RubyConfig::dataBlockBits(),
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RubyConfig::dataBlockBits()+RubyConfig::L2CachePerChipBits()-1);
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} else {
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L2bank = addr.bitSelect(RubyConfig::dataBlockBits()+L2_CACHE_NUM_SETS_BITS,
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RubyConfig::dataBlockBits()+L2_CACHE_NUM_SETS_BITS+RubyConfig::L2CachePerChipBits()-1);
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}
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}
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assert(L2bank < RubyConfig::numberOfL2CachePerChip());
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assert(L2bank >= 0);
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mach.num = L2ChipId*RubyConfig::numberOfL2CachePerChip() // base #
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+ L2bank; // bank #
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assert(mach.num < RubyConfig::numberOfL2Cache());
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return mach;
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}
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// used to determine the home directory
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// returns a value between 0 and total_directories_within_the_system
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inline
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NodeID map_Address_to_DirectoryNode(const Address& addr)
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{
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NodeID dirNode = 0;
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if (RubyConfig::memoryBits() > 0) {
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dirNode = addr.bitSelect(RubyConfig::dataBlockBits(),
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RubyConfig::dataBlockBits()+RubyConfig::memoryBits()-1);
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}
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// Index indexHighPortion = address.bitSelect(MEMORY_SIZE_BITS-1, PAGE_SIZE_BITS+NUMBER_OF_MEMORY_MODULE_BITS);
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// Index indexLowPortion = address.bitSelect(DATA_BLOCK_BITS, PAGE_SIZE_BITS-1);
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//Index index = indexLowPortion | (indexHighPortion << (PAGE_SIZE_BITS - DATA_BLOCK_BITS));
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/*
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ADDRESS_WIDTH MEMORY_SIZE_BITS PAGE_SIZE_BITS DATA_BLOCK_BITS
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\ / \ / \ / \ / 0
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-----------------------------------------------------------------------
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| unused |xxxxxxxxxxxxxxx| |xxxxxxxxxxxxxxx| |
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| |xxxxxxxxxxxxxxx| |xxxxxxxxxxxxxxx| |
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-----------------------------------------------------------------------
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indexHighPortion indexLowPortion
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<------->
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NUMBER_OF_MEMORY_MODULE_BITS
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*/
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assert(dirNode < RubyConfig::numberOfMemories());
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assert(dirNode >= 0);
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return dirNode;
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}
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// used to determine the home directory
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// returns a value between 0 and total_directories_within_the_system
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inline
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MachineID map_Address_to_Directory(const Address &addr)
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{
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MachineID mach = {MachineType_Directory, map_Address_to_DirectoryNode(addr)};
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return mach;
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}
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inline
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MachineID map_Address_to_CentralArbiterNode(const Address& addr)
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{
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MachineType t = MACHINETYPE_PERSISTENTARBITER_ENUM;
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MachineID mach = {t, map_Address_to_DirectoryNode(addr)};
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assert(mach.num < RubyConfig::numberOfMemories());
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assert(mach.num >= 0);
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return mach;
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}
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inline
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NetDest getMultiStaticL2BankNetDest(const Address& addr, const Set& sharers) // set of L2RubyNodes
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{
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NetDest dest;
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for (int i = 0; i < sharers.getSize(); i++) {
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if (sharers.isElement(i)) {
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dest.add(map_L2ChipId_to_L2Cache(addr,i));
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}
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}
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return dest;
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}
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inline
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NetDest getOtherLocalL1IDs(MachineID L1)
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{
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int start = (L1.num / RubyConfig::numberOfProcsPerChip()) * RubyConfig::numberOfProcsPerChip();
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NetDest ret;
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assert(MACHINETYPE_L1CACHE_ENUM != MachineType_NUM);
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for (int i = start; i < (start + RubyConfig::numberOfProcsPerChip()); i++) {
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if (i != L1.num) {
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MachineID mach = { MACHINETYPE_L1CACHE_ENUM, i };
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ret.add( mach );
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}
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}
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return ret;
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}
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inline
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NetDest getLocalL1IDs(MachineID mach)
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{
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assert(MACHINETYPE_L1CACHE_ENUM != MachineType_NUM);
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NetDest ret;
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if (mach.type == MACHINETYPE_L1CACHE_ENUM) {
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int start = (mach.num / RubyConfig::numberOfL1CachePerChip()) * RubyConfig::numberOfProcsPerChip();
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for (int i = start; i < (start + RubyConfig::numberOfProcsPerChip()); i++) {
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MachineID mach = { MACHINETYPE_L1CACHE_ENUM, i };
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ret.add( mach );
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}
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}
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else if (mach.type == MACHINETYPE_L2CACHE_ENUM) {
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int chip = mach.num/RubyConfig::numberOfL2CachePerChip();
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int start = ( chip*RubyConfig::numberOfL1CachePerChip());
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for (int i = start; i < (start + RubyConfig::numberOfL1CachePerChip()); i++) {
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MachineID mach = { MACHINETYPE_L1CACHE_ENUM, i };
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ret.add( mach );
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}
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}
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return ret;
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}
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inline
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NetDest getExternalL1IDs(MachineID L1)
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{
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NetDest ret;
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assert(MACHINETYPE_L1CACHE_ENUM != MachineType_NUM);
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for (int i = 0; i < RubyConfig::numberOfProcessors(); i++) {
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// ret.add( (NodeID) i);
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MachineID mach = { MACHINETYPE_L1CACHE_ENUM, i };
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ret.add( mach );
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}
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ret.removeNetDest(getLocalL1IDs(L1));
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return ret;
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}
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inline
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bool isLocalProcessor(MachineID thisId, MachineID tarID)
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{
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int start = (thisId.num / RubyConfig::numberOfProcsPerChip()) * RubyConfig::numberOfProcsPerChip();
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for (int i = start; i < (start + RubyConfig::numberOfProcsPerChip()); i++) {
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if (i == tarID.num) {
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return true;
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}
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}
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return false;
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}
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inline
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NetDest getAllPertinentL2Banks(const Address& addr) // set of L2RubyNodes
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{
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NetDest dest;
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for (int i = 0; i < RubyConfig::numberOfChips(); i++) {
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dest.add(map_L2ChipId_to_L2Cache(addr,i));
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}
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return dest;
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}
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inline
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bool isL1OnChip(MachineID L1machID, NodeID L2NodeID)
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{
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if (L1machID.type == MACHINETYPE_L1CACHE_ENUM) {
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return (L1machID.num == L2NodeID);
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} else {
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return false;
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}
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}
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inline
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bool isL2OnChip(MachineID L2machID, NodeID L2NodeID)
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{
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if (L2machID.type == MACHINETYPE_L2CACHE_ENUM) {
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return (L2machID.num == L2NodeID);
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} else {
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return false;
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}
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}
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inline
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NodeID closest_clockwise_distance(NodeID this_node, NodeID next_node)
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{
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if (this_node <= next_node) {
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return (next_node - this_node);
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} else {
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return (next_node - this_node + RubyConfig::numberOfChips());
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}
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}
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inline
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bool closer_clockwise_processor(NodeID this_node, NodeID newer, NodeID older)
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{
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return (closest_clockwise_distance(this_node, newer) < closest_clockwise_distance(this_node, older));
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}
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extern inline NodeID getChipID(MachineID L2machID)
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{
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return (L2machID.num%RubyConfig::numberOfChips())/RubyConfig::numberOfProcsPerChip();
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}
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extern inline NodeID machineIDToNodeID(MachineID machID)
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{
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// return machID.num%RubyConfig::numberOfChips();
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||
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|
return machID.num;
|
||
|
|
}
|
||
|
|
|
||
|
|
extern inline NodeID machineIDToVersion(MachineID machID)
|
||
|
|
{
|
||
|
|
return machID.num/RubyConfig::numberOfChips();
|
||
|
|
}
|
||
|
|
|
||
|
|
extern inline MachineType machineIDToMachineType(MachineID machID)
|
||
|
|
{
|
||
|
|
return machID.type;
|
||
|
|
}
|
||
|
|
|
||
|
|
extern inline NodeID L1CacheMachIDToProcessorNum(MachineID machID)
|
||
|
|
{
|
||
|
|
assert(machID.type == MachineType_L1Cache);
|
||
|
|
return machID.num;
|
||
|
|
}
|
||
|
|
|
||
|
|
extern inline NodeID L2CacheMachIDToChipID(MachineID machID)
|
||
|
|
{
|
||
|
|
assert(machID.type == MACHINETYPE_L2CACHE_ENUM);
|
||
|
|
return machID.num/RubyConfig::numberOfL2CachePerChip();
|
||
|
|
}
|
||
|
|
|
||
|
|
extern inline MachineID getCollectorDest(MachineID L1MachID)
|
||
|
|
{
|
||
|
|
MachineID mach = {MACHINETYPE_COLLECTOR_ENUM, L1MachID.num};
|
||
|
|
return mach;
|
||
|
|
}
|
||
|
|
|
||
|
|
extern inline MachineID getCollectorL1Cache(MachineID colID)
|
||
|
|
{
|
||
|
|
MachineID mach = {MACHINETYPE_L1CACHE_ENUM, colID.num};
|
||
|
|
return mach;
|
||
|
|
}
|
||
|
|
|
||
|
|
extern inline MachineID getL1MachineID(NodeID L1RubyNode)
|
||
|
|
{
|
||
|
|
MachineID mach = {MACHINETYPE_L1CACHE_ENUM, L1RubyNode};
|
||
|
|
return mach;
|
||
|
|
}
|
||
|
|
|
||
|
|
extern inline GenericMachineType ConvertMachToGenericMach(MachineType machType) {
|
||
|
|
if (machType == MACHINETYPE_L1CACHE_ENUM) {
|
||
|
|
return GenericMachineType_L1Cache;
|
||
|
|
} else if (machType == MACHINETYPE_L2CACHE_ENUM) {
|
||
|
|
return GenericMachineType_L2Cache;
|
||
|
|
} else if (machType == MACHINETYPE_L3CACHE_ENUM) {
|
||
|
|
return GenericMachineType_L3Cache;
|
||
|
|
} else if (machType == MachineType_Directory) {
|
||
|
|
return GenericMachineType_Directory;
|
||
|
|
} else if (machType == MACHINETYPE_COLLECTOR_ENUM) {
|
||
|
|
return GenericMachineType_Collector;
|
||
|
|
} else {
|
||
|
|
ERROR_MSG("cannot convert to a GenericMachineType");
|
||
|
|
return GenericMachineType_NULL;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
#endif // COMPONENTMAPPINGFNS_H
|