158 lines
6 KiB
C++
158 lines
6 KiB
C++
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/*
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* Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* SimpleNetwork.h
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*
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* Description: The SimpleNetwork class implements the interconnection
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* SimpleNetwork between components (processor/cache components and
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* memory/directory components). The interconnection network as
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* described here is not a physical network, but a programming concept
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* used to implement all communication between components. Thus parts
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* of this 'network' may model the on-chip connections between cache
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* controllers and directory controllers as well as the links between
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* chip and network switches.
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*
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* Two conceptual networks, an address and data network, are modeled.
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* The data network is unordered, where the address network provides
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* and conforms to a global ordering of all transactions.
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*
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* Currently the data network is point-to-point and the address
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* network is a broadcast network. These two distinct conceptual
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* network can be modeled as physically separate networks or
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* multiplexed over a single physical network.
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*
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* The network encapsulates all notion of virtual global time and is
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* responsible for ordering the network transactions received. This
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* hides all of these ordering details from the processor/cache and
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* directory/memory modules.
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*
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* FIXME: Various flavor of networks are provided as a compiler time
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* configurable. We currently include this SimpleNetwork in the
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* makefile's vpath, so that SimpleNetwork.C can provide an alternative
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* version constructor for the abstract Network class. It is easy to
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* modify this to make network a runtime configuable. Just make the
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* abstract Network class take a enumeration parameter, and based on
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* that to initial proper network. Or even better, just make the ruby
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* system initializer choose the proper network to initiate.
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*
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* $Id$
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*
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*/
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#ifndef SIMPLENETWORK_H
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#define SIMPLENETWORK_H
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#include "Global.hh"
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#include "Vector.hh"
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#include "Network.hh"
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#include "NodeID.hh"
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class NetDest;
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class MessageBuffer;
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class Throttle;
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class Switch;
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class Topology;
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class SimpleNetwork : public Network {
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public:
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// Constructors
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SimpleNetwork(int nodes);
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// Destructor
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~SimpleNetwork();
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// Public Methods
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void printStats(ostream& out) const;
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void clearStats();
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void printConfig(ostream& out) const;
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void reset();
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// returns the queue requested for the given component
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MessageBuffer* getToNetQueue(NodeID id, bool ordered, int network_num);
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MessageBuffer* getFromNetQueue(NodeID id, bool ordered, int network_num);
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virtual const Vector<Throttle*>* getThrottles(NodeID id) const;
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bool isVNetOrdered(int vnet) { return m_ordered[vnet]; }
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bool validVirtualNetwork(int vnet) { return m_in_use[vnet]; }
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int getNumNodes() {return m_nodes; }
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// Methods used by Topology to setup the network
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void makeOutLink(SwitchID src, NodeID dest, const NetDest& routing_table_entry, int link_latency, int link_weight, int bw_multiplier, bool isReconfiguration);
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void makeInLink(SwitchID src, NodeID dest, const NetDest& routing_table_entry, int link_latency, int bw_multiplier, bool isReconfiguration);
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void makeInternalLink(SwitchID src, NodeID dest, const NetDest& routing_table_entry, int link_latency, int link_weight, int bw_multiplier, bool isReconfiguration);
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void print(ostream& out) const;
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private:
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void checkNetworkAllocation(NodeID id, bool ordered, int network_num);
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void addLink(SwitchID src, SwitchID dest, int link_latency);
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void makeLink(SwitchID src, SwitchID dest, const NetDest& routing_table_entry, int link_latency);
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SwitchID createSwitch();
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void makeTopology();
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void linkTopology();
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// Private copy constructor and assignment operator
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SimpleNetwork(const SimpleNetwork& obj);
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SimpleNetwork& operator=(const SimpleNetwork& obj);
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// Data Members (m_ prefix)
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// vector of queues from the components
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Vector<Vector<MessageBuffer*> > m_toNetQueues;
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Vector<Vector<MessageBuffer*> > m_fromNetQueues;
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int m_nodes;
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int m_virtual_networks;
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Vector<bool> m_in_use;
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Vector<bool> m_ordered;
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Vector<Switch*> m_switch_ptr_vector;
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Vector<MessageBuffer*> m_buffers_to_free;
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Vector<Switch*> m_endpoint_switches;
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Topology* m_topology_ptr;
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};
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// Output operator declaration
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ostream& operator<<(ostream& out, const SimpleNetwork& obj);
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// ******************* Definitions *******************
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// Output operator definition
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extern inline
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ostream& operator<<(ostream& out, const SimpleNetwork& obj)
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{
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obj.print(out);
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out << flush;
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return out;
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}
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#endif //SIMPLENETWORK_H
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