2007-11-13 03:06:57 +01:00
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/*
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* Copyright (c) 2007 The Hewlett-Packard Development Company
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* All rights reserved.
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*
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2010-05-24 07:44:15 +02:00
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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2007-11-13 03:06:57 +01:00
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*
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2010-05-24 07:44:15 +02:00
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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2007-11-13 03:06:57 +01:00
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* contributors may be used to endorse or promote products derived from
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2010-05-24 07:44:15 +02:00
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* this software without specific prior written permission.
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2007-11-13 03:06:57 +01:00
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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*/
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#ifndef __ARCH_X86_PAGE_TABLE_WALKER_HH__
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#define __ARCH_X86_PAGE_TABLE_WALKER_HH__
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#include <vector>
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#include "arch/x86/pagetable.hh"
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#include "arch/x86/tlb.hh"
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2011-02-07 07:14:18 +01:00
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#include "base/fast_alloc.hh"
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2011-04-15 19:44:06 +02:00
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#include "base/types.hh"
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2007-11-13 03:06:57 +01:00
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#include "mem/mem_object.hh"
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#include "mem/packet.hh"
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#include "params/X86PagetableWalker.hh"
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2011-02-07 07:14:17 +01:00
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#include "sim/faults.hh"
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2012-02-12 23:07:38 +01:00
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#include "sim/system.hh"
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2007-11-13 03:06:57 +01:00
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class ThreadContext;
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namespace X86ISA
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{
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class Walker : public MemObject
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{
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protected:
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2011-02-07 07:14:18 +01:00
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// Port for accessing memory
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MEM: Introduce the master/slave port sub-classes in C++
This patch introduces the notion of a master and slave port in the C++
code, thus bringing the previous classification from the Python
classes into the corresponding simulation objects and memory objects.
The patch enables us to classify behaviours into the two bins and add
assumptions and enfore compliance, also simplifying the two
interfaces. As a starting point, isSnooping is confined to a master
port, and getAddrRanges to slave ports. More of these specilisations
are to come in later patches.
The getPort function is not getMasterPort and getSlavePort, and
returns a port reference rather than a pointer as NULL would never be
a valid return value. The default implementation of these two
functions is placed in MemObject, and calls fatal.
The one drawback with this specific patch is that it requires some
code duplication, e.g. QueuedPort becomes QueuedMasterPort and
QueuedSlavePort, and BusPort becomes BusMasterPort and BusSlavePort
(avoiding multiple inheritance). With the later introduction of the
port interfaces, moving the functionality outside the port itself, a
lot of the duplicated code will disappear again.
2012-03-30 15:40:11 +02:00
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class WalkerPort : public MasterPort
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2007-11-13 03:06:57 +01:00
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{
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public:
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WalkerPort(const std::string &_name, Walker * _walker) :
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MEM: Introduce the master/slave port sub-classes in C++
This patch introduces the notion of a master and slave port in the C++
code, thus bringing the previous classification from the Python
classes into the corresponding simulation objects and memory objects.
The patch enables us to classify behaviours into the two bins and add
assumptions and enfore compliance, also simplifying the two
interfaces. As a starting point, isSnooping is confined to a master
port, and getAddrRanges to slave ports. More of these specilisations
are to come in later patches.
The getPort function is not getMasterPort and getSlavePort, and
returns a port reference rather than a pointer as NULL would never be
a valid return value. The default implementation of these two
functions is placed in MemObject, and calls fatal.
The one drawback with this specific patch is that it requires some
code duplication, e.g. QueuedPort becomes QueuedMasterPort and
QueuedSlavePort, and BusPort becomes BusMasterPort and BusSlavePort
(avoiding multiple inheritance). With the later introduction of the
port interfaces, moving the functionality outside the port itself, a
lot of the duplicated code will disappear again.
2012-03-30 15:40:11 +02:00
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MasterPort(_name, _walker), walker(_walker)
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2007-11-13 03:06:57 +01:00
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{}
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protected:
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2012-02-12 23:07:38 +01:00
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Walker *walker;
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2007-11-13 03:06:57 +01:00
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MEM: Separate requests and responses for timing accesses
This patch moves send/recvTiming and send/recvTimingSnoop from the
Port base class to the MasterPort and SlavePort, and also splits them
into separate member functions for requests and responses:
send/recvTimingReq, send/recvTimingResp, and send/recvTimingSnoopReq,
send/recvTimingSnoopResp. A master port sends requests and receives
responses, and also receives snoop requests and sends snoop
responses. A slave port has the reciprocal behaviour as it receives
requests and sends responses, and sends snoop requests and receives
snoop responses.
For all MemObjects that have only master ports or slave ports (but not
both), e.g. a CPU, or a PIO device, this patch merely adds more
clarity to what kind of access is taking place. For example, a CPU
port used to call sendTiming, and will now call
sendTimingReq. Similarly, a response previously came back through
recvTiming, which is now recvTimingResp. For the modules that have
both master and slave ports, e.g. the bus, the behaviour was
previously relying on branches based on pkt->isRequest(), and this is
now replaced with a direct call to the apprioriate member function
depending on the type of access. Please note that send/recvRetry is
still shared by all the timing accessors and remains in the Port base
class for now (to maintain the current bus functionality and avoid
changing the statistics of all regressions).
The packet queue is split into a MasterPort and SlavePort version to
facilitate the use of the new timing accessors. All uses of the
PacketQueue are updated accordingly.
With this patch, the type of packet (request or response) is now well
defined for each type of access, and asserts on pkt->isRequest() and
pkt->isResponse() are now moved to the appropriate send member
functions. It is also worth noting that sendTimingSnoopReq no longer
returns a boolean, as the semantics do not alow snoop requests to be
rejected or stalled. All these assumptions are now excplicitly part of
the port interface itself.
2012-05-01 19:40:42 +02:00
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bool recvTimingResp(PacketPtr pkt);
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MEM: Separate snoops and normal memory requests/responses
This patch introduces port access methods that separates snoop
request/responses from normal memory request/responses. The
differentiation is made for functional, atomic and timing accesses and
builds on the introduction of master and slave ports.
Before the introduction of this patch, the packets belonging to the
different phases of the protocol (request -> [forwarded snoop request
-> snoop response]* -> response) all use the same port access
functions, even though the snoop packets flow in the opposite
direction to the normal packet. That is, a coherent master sends
normal request and receives responses, but receives snoop requests and
sends snoop responses (vice versa for the slave). These two distinct
phases now use different access functions, as described below.
Starting with the functional access, a master sends a request to a
slave through sendFunctional, and the request packet is turned into a
response before the call returns. In a system without cache coherence,
this is all that is needed from the functional interface. For the
cache-coherent scenario, a slave also sends snoop requests to coherent
masters through sendFunctionalSnoop, with responses returned within
the same packet pointer. This is currently used by the bus and caches,
and the LSQ of the O3 CPU. The send/recvFunctional and
send/recvFunctionalSnoop are moved from the Port super class to the
appropriate subclass.
Atomic accesses follow the same flow as functional accesses, with
request being sent from master to slave through sendAtomic. In the
case of cache-coherent ports, a slave can send snoop requests to a
master through sendAtomicSnoop. Just as for the functional access
methods, the atomic send and receive member functions are moved to the
appropriate subclasses.
The timing access methods are different from the functional and atomic
in that requests and responses are separated in time and
send/recvTiming are used for both directions. Hence, a master uses
sendTiming to send a request to a slave, and a slave uses sendTiming
to send a response back to a master, at a later point in time. Snoop
requests and responses travel in the opposite direction, similar to
what happens in functional and atomic accesses. With the introduction
of this patch, it is possible to determine the direction of packets in
the bus, and no longer necessary to look for both a master and a slave
port with the requested port id.
In contrast to the normal recvFunctional, recvAtomic and recvTiming
that are pure virtual functions, the recvFunctionalSnoop,
recvAtomicSnoop and recvTimingSnoop have a default implementation that
calls panic. This is to allow non-coherent master and slave ports to
not implement these functions.
2012-04-14 11:45:07 +02:00
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/**
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* Snooping a coherence request, do nothing.
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*/
|
MEM: Separate requests and responses for timing accesses
This patch moves send/recvTiming and send/recvTimingSnoop from the
Port base class to the MasterPort and SlavePort, and also splits them
into separate member functions for requests and responses:
send/recvTimingReq, send/recvTimingResp, and send/recvTimingSnoopReq,
send/recvTimingSnoopResp. A master port sends requests and receives
responses, and also receives snoop requests and sends snoop
responses. A slave port has the reciprocal behaviour as it receives
requests and sends responses, and sends snoop requests and receives
snoop responses.
For all MemObjects that have only master ports or slave ports (but not
both), e.g. a CPU, or a PIO device, this patch merely adds more
clarity to what kind of access is taking place. For example, a CPU
port used to call sendTiming, and will now call
sendTimingReq. Similarly, a response previously came back through
recvTiming, which is now recvTimingResp. For the modules that have
both master and slave ports, e.g. the bus, the behaviour was
previously relying on branches based on pkt->isRequest(), and this is
now replaced with a direct call to the apprioriate member function
depending on the type of access. Please note that send/recvRetry is
still shared by all the timing accessors and remains in the Port base
class for now (to maintain the current bus functionality and avoid
changing the statistics of all regressions).
The packet queue is split into a MasterPort and SlavePort version to
facilitate the use of the new timing accessors. All uses of the
PacketQueue are updated accordingly.
With this patch, the type of packet (request or response) is now well
defined for each type of access, and asserts on pkt->isRequest() and
pkt->isResponse() are now moved to the appropriate send member
functions. It is also worth noting that sendTimingSnoopReq no longer
returns a boolean, as the semantics do not alow snoop requests to be
rejected or stalled. All these assumptions are now excplicitly part of
the port interface itself.
2012-05-01 19:40:42 +02:00
|
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|
void recvTimingSnoopReq(PacketPtr pkt) { }
|
MEM: Separate snoops and normal memory requests/responses
This patch introduces port access methods that separates snoop
request/responses from normal memory request/responses. The
differentiation is made for functional, atomic and timing accesses and
builds on the introduction of master and slave ports.
Before the introduction of this patch, the packets belonging to the
different phases of the protocol (request -> [forwarded snoop request
-> snoop response]* -> response) all use the same port access
functions, even though the snoop packets flow in the opposite
direction to the normal packet. That is, a coherent master sends
normal request and receives responses, but receives snoop requests and
sends snoop responses (vice versa for the slave). These two distinct
phases now use different access functions, as described below.
Starting with the functional access, a master sends a request to a
slave through sendFunctional, and the request packet is turned into a
response before the call returns. In a system without cache coherence,
this is all that is needed from the functional interface. For the
cache-coherent scenario, a slave also sends snoop requests to coherent
masters through sendFunctionalSnoop, with responses returned within
the same packet pointer. This is currently used by the bus and caches,
and the LSQ of the O3 CPU. The send/recvFunctional and
send/recvFunctionalSnoop are moved from the Port super class to the
appropriate subclass.
Atomic accesses follow the same flow as functional accesses, with
request being sent from master to slave through sendAtomic. In the
case of cache-coherent ports, a slave can send snoop requests to a
master through sendAtomicSnoop. Just as for the functional access
methods, the atomic send and receive member functions are moved to the
appropriate subclasses.
The timing access methods are different from the functional and atomic
in that requests and responses are separated in time and
send/recvTiming are used for both directions. Hence, a master uses
sendTiming to send a request to a slave, and a slave uses sendTiming
to send a response back to a master, at a later point in time. Snoop
requests and responses travel in the opposite direction, similar to
what happens in functional and atomic accesses. With the introduction
of this patch, it is possible to determine the direction of packets in
the bus, and no longer necessary to look for both a master and a slave
port with the requested port id.
In contrast to the normal recvFunctional, recvAtomic and recvTiming
that are pure virtual functions, the recvFunctionalSnoop,
recvAtomicSnoop and recvTimingSnoop have a default implementation that
calls panic. This is to allow non-coherent master and slave ports to
not implement these functions.
2012-04-14 11:45:07 +02:00
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Tick recvAtomicSnoop(PacketPtr pkt) { return 0; }
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void recvFunctionalSnoop(PacketPtr pkt) { }
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2007-11-13 03:06:57 +01:00
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void recvRetry();
|
MEM: Introduce the master/slave port sub-classes in C++
This patch introduces the notion of a master and slave port in the C++
code, thus bringing the previous classification from the Python
classes into the corresponding simulation objects and memory objects.
The patch enables us to classify behaviours into the two bins and add
assumptions and enfore compliance, also simplifying the two
interfaces. As a starting point, isSnooping is confined to a master
port, and getAddrRanges to slave ports. More of these specilisations
are to come in later patches.
The getPort function is not getMasterPort and getSlavePort, and
returns a port reference rather than a pointer as NULL would never be
a valid return value. The default implementation of these two
functions is placed in MemObject, and calls fatal.
The one drawback with this specific patch is that it requires some
code duplication, e.g. QueuedPort becomes QueuedMasterPort and
QueuedSlavePort, and BusPort becomes BusMasterPort and BusSlavePort
(avoiding multiple inheritance). With the later introduction of the
port interfaces, moving the functionality outside the port itself, a
lot of the duplicated code will disappear again.
2012-03-30 15:40:11 +02:00
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bool isSnooping() const { return true; }
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2007-11-13 03:06:57 +01:00
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};
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2011-02-07 07:14:18 +01:00
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friend class WalkerPort;
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WalkerPort port;
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2007-11-13 03:06:57 +01:00
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2011-02-07 07:14:18 +01:00
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// State to track each walk of the page table
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class WalkerState : public FastAlloc
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{
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private:
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enum State {
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Ready,
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Waiting,
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// Long mode
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LongPML4, LongPDP, LongPD, LongPTE,
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// PAE legacy mode
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PAEPDP, PAEPD, PAEPTE,
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// Non PAE legacy mode with and without PSE
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PSEPD, PD, PTE
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};
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2007-11-13 03:06:57 +01:00
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2011-02-07 07:14:18 +01:00
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protected:
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2012-02-12 23:07:38 +01:00
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Walker *walker;
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2011-02-07 07:14:18 +01:00
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ThreadContext *tc;
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RequestPtr req;
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State state;
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State nextState;
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int dataSize;
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bool enableNX;
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unsigned inflight;
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TlbEntry entry;
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PacketPtr read;
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std::vector<PacketPtr> writes;
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Fault timingFault;
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TLB::Translation * translation;
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BaseTLB::Mode mode;
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bool functional;
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bool timing;
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bool retrying;
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bool started;
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public:
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WalkerState(Walker * _walker, BaseTLB::Translation *_translation,
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RequestPtr _req, bool _isFunctional = false) :
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walker(_walker), req(_req), state(Ready),
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nextState(Ready), inflight(0),
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translation(_translation),
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functional(_isFunctional), timing(false),
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retrying(false), started(false)
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{
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}
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void initState(ThreadContext * _tc, BaseTLB::Mode _mode,
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bool _isTiming = false);
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Fault startWalk();
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2012-04-15 08:24:18 +02:00
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Fault startFunctional(Addr &addr, unsigned &logBytes);
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2011-02-07 07:14:18 +01:00
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bool recvPacket(PacketPtr pkt);
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bool isRetrying();
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bool wasStarted();
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bool isTiming();
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void retry();
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std::string name() const {return walker->name();}
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private:
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void setupWalk(Addr vaddr);
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Fault stepWalk(PacketPtr &write);
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void sendPackets();
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void endWalk();
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Fault pageFault(bool present);
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};
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friend class WalkerState;
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// State for timing and atomic accesses (need multiple per walker in
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// the case of multiple outstanding requests in timing mode)
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std::list<WalkerState *> currStates;
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// State for functional accesses (only need one of these per walker)
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WalkerState funcState;
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struct WalkerSenderState : public Packet::SenderState
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{
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WalkerState * senderWalk;
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Packet::SenderState * saved;
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WalkerSenderState(WalkerState * _senderWalk,
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Packet::SenderState * _saved) :
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senderWalk(_senderWalk), saved(_saved) {}
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};
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2007-11-13 03:06:57 +01:00
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2011-02-07 07:14:18 +01:00
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public:
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// Kick off the state machine.
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Fault start(ThreadContext * _tc, BaseTLB::Translation *translation,
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RequestPtr req, BaseTLB::Mode mode);
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Fault startFunctional(ThreadContext * _tc, Addr &addr,
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2012-04-15 08:24:18 +02:00
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unsigned &logBytes, BaseTLB::Mode mode);
|
MEM: Introduce the master/slave port sub-classes in C++
This patch introduces the notion of a master and slave port in the C++
code, thus bringing the previous classification from the Python
classes into the corresponding simulation objects and memory objects.
The patch enables us to classify behaviours into the two bins and add
assumptions and enfore compliance, also simplifying the two
interfaces. As a starting point, isSnooping is confined to a master
port, and getAddrRanges to slave ports. More of these specilisations
are to come in later patches.
The getPort function is not getMasterPort and getSlavePort, and
returns a port reference rather than a pointer as NULL would never be
a valid return value. The default implementation of these two
functions is placed in MemObject, and calls fatal.
The one drawback with this specific patch is that it requires some
code duplication, e.g. QueuedPort becomes QueuedMasterPort and
QueuedSlavePort, and BusPort becomes BusMasterPort and BusSlavePort
(avoiding multiple inheritance). With the later introduction of the
port interfaces, moving the functionality outside the port itself, a
lot of the duplicated code will disappear again.
2012-03-30 15:40:11 +02:00
|
|
|
MasterPort &getMasterPort(const std::string &if_name, int idx = -1);
|
2011-02-07 07:14:18 +01:00
|
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protected:
|
2007-11-13 03:06:57 +01:00
|
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// The TLB we're supposed to load.
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TLB * tlb;
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System * sys;
|
2012-02-12 23:07:38 +01:00
|
|
|
MasterID masterId;
|
2011-02-07 07:14:18 +01:00
|
|
|
|
|
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|
// Functions for dealing with packets.
|
MEM: Separate requests and responses for timing accesses
This patch moves send/recvTiming and send/recvTimingSnoop from the
Port base class to the MasterPort and SlavePort, and also splits them
into separate member functions for requests and responses:
send/recvTimingReq, send/recvTimingResp, and send/recvTimingSnoopReq,
send/recvTimingSnoopResp. A master port sends requests and receives
responses, and also receives snoop requests and sends snoop
responses. A slave port has the reciprocal behaviour as it receives
requests and sends responses, and sends snoop requests and receives
snoop responses.
For all MemObjects that have only master ports or slave ports (but not
both), e.g. a CPU, or a PIO device, this patch merely adds more
clarity to what kind of access is taking place. For example, a CPU
port used to call sendTiming, and will now call
sendTimingReq. Similarly, a response previously came back through
recvTiming, which is now recvTimingResp. For the modules that have
both master and slave ports, e.g. the bus, the behaviour was
previously relying on branches based on pkt->isRequest(), and this is
now replaced with a direct call to the apprioriate member function
depending on the type of access. Please note that send/recvRetry is
still shared by all the timing accessors and remains in the Port base
class for now (to maintain the current bus functionality and avoid
changing the statistics of all regressions).
The packet queue is split into a MasterPort and SlavePort version to
facilitate the use of the new timing accessors. All uses of the
PacketQueue are updated accordingly.
With this patch, the type of packet (request or response) is now well
defined for each type of access, and asserts on pkt->isRequest() and
pkt->isResponse() are now moved to the appropriate send member
functions. It is also worth noting that sendTimingSnoopReq no longer
returns a boolean, as the semantics do not alow snoop requests to be
rejected or stalled. All these assumptions are now excplicitly part of
the port interface itself.
2012-05-01 19:40:42 +02:00
|
|
|
bool recvTimingResp(PacketPtr pkt);
|
2011-02-07 07:14:18 +01:00
|
|
|
void recvRetry();
|
|
|
|
bool sendTiming(WalkerState * sendingState, PacketPtr pkt);
|
2007-11-13 03:06:57 +01:00
|
|
|
|
|
|
|
public:
|
|
|
|
|
|
|
|
void setTLB(TLB * _tlb)
|
|
|
|
{
|
|
|
|
tlb = _tlb;
|
|
|
|
}
|
|
|
|
|
|
|
|
typedef X86PagetableWalkerParams Params;
|
|
|
|
|
2012-02-12 23:07:38 +01:00
|
|
|
const Params *
|
|
|
|
params() const
|
|
|
|
{
|
|
|
|
return static_cast<const Params *>(_params);
|
|
|
|
}
|
|
|
|
|
2007-11-13 03:06:57 +01:00
|
|
|
Walker(const Params *params) :
|
2011-02-07 07:14:18 +01:00
|
|
|
MemObject(params), port(name() + ".port", this),
|
2012-02-12 23:07:38 +01:00
|
|
|
funcState(this, NULL, NULL, true), tlb(NULL), sys(params->system),
|
|
|
|
masterId(sys->getMasterId(name()))
|
2007-11-13 03:06:57 +01:00
|
|
|
{
|
|
|
|
}
|
|
|
|
};
|
|
|
|
}
|
|
|
|
#endif // __ARCH_X86_PAGE_TABLE_WALKER_HH__
|