2010-01-30 05:29:22 +01:00
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/*
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* Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "mem/ruby/profiler/MemCntrlProfiler.hh"
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2010-03-11 03:33:11 +01:00
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using namespace std;
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2010-01-30 05:29:22 +01:00
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MemCntrlProfiler::MemCntrlProfiler(const string& description,
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int banks_per_rank,
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int ranks_per_dimm,
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int dimms_per_channel)
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{
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m_description = description;
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m_banks_per_rank = banks_per_rank;
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m_ranks_per_dimm = ranks_per_dimm;
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m_dimms_per_channel = dimms_per_channel;
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int totalBanks = banks_per_rank *
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ranks_per_dimm *
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dimms_per_channel;
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m_memBankCount.setSize(totalBanks);
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clearStats();
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}
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MemCntrlProfiler::~MemCntrlProfiler()
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{
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}
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void MemCntrlProfiler::printStats(ostream& out) const
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{
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if (m_memReq || m_memRefresh) { // if there's a memory controller at all
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uint64 total_stalls = m_memInputQ + m_memBankQ + m_memWaitCycles;
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double stallsPerReq = total_stalls * 1.0 / m_memReq;
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out << "Memory controller: " << m_description << ":" << endl;
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out << " memory_total_requests: " << m_memReq << endl; // does not include refreshes
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out << " memory_reads: " << m_memRead << endl;
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out << " memory_writes: " << m_memWrite << endl;
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out << " memory_refreshes: " << m_memRefresh << endl;
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out << " memory_total_request_delays: " << total_stalls << endl;
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out << " memory_delays_per_request: " << stallsPerReq << endl;
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out << " memory_delays_in_input_queue: " << m_memInputQ << endl;
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out << " memory_delays_behind_head_of_bank_queue: " << m_memBankQ << endl;
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out << " memory_delays_stalled_at_head_of_bank_queue: " << m_memWaitCycles << endl;
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// Note: The following "memory stalls" entries are a breakdown of the
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// cycles which already showed up in m_memWaitCycles. The order is
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// significant; it is the priority of attributing the cycles.
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// For example, bank_busy is before arbitration because if the bank was
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// busy, we didn't even check arbitration.
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// Note: "not old enough" means that since we grouped waiting heads-of-queues
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// into batches to avoid starvation, a request in a newer batch
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// didn't try to arbitrate yet because there are older requests waiting.
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out << " memory_stalls_for_bank_busy: " << m_memBankBusy << endl;
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out << " memory_stalls_for_random_busy: " << m_memRandBusy << endl;
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out << " memory_stalls_for_anti_starvation: " << m_memNotOld << endl;
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out << " memory_stalls_for_arbitration: " << m_memArbWait << endl;
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out << " memory_stalls_for_bus: " << m_memBusBusy << endl;
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out << " memory_stalls_for_tfaw: " << m_memTfawBusy << endl;
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out << " memory_stalls_for_read_write_turnaround: " << m_memReadWriteBusy << endl;
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out << " memory_stalls_for_read_read_turnaround: " << m_memDataBusBusy << endl;
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out << " accesses_per_bank: ";
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for (int bank=0; bank < m_memBankCount.size(); bank++) {
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out << m_memBankCount[bank] << " ";
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}
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} else {
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out << "Memory Controller: " << m_description
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<< " no stats recorded." << endl;
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}
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out << endl;
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out << endl;
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}
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void MemCntrlProfiler::clearStats()
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{
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m_memReq = 0;
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m_memBankBusy = 0;
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m_memBusBusy = 0;
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m_memTfawBusy = 0;
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m_memReadWriteBusy = 0;
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m_memDataBusBusy = 0;
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m_memRefresh = 0;
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m_memRead = 0;
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m_memWrite = 0;
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m_memWaitCycles = 0;
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m_memInputQ = 0;
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m_memBankQ = 0;
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m_memArbWait = 0;
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m_memRandBusy = 0;
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m_memNotOld = 0;
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for (int bank=0;
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bank < m_memBankCount.size();
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bank++) {
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m_memBankCount[bank] = 0;
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}
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}
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void MemCntrlProfiler::profileMemReq(int bank) {
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m_memReq++;
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m_memBankCount[bank]++;
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}
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void MemCntrlProfiler::profileMemBankBusy() {
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m_memBankBusy++;
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}
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void MemCntrlProfiler::profileMemBusBusy() {
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m_memBusBusy++;
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}
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void MemCntrlProfiler::profileMemReadWriteBusy() {
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m_memReadWriteBusy++;
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}
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void MemCntrlProfiler::profileMemDataBusBusy() {
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m_memDataBusBusy++;
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}
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void MemCntrlProfiler::profileMemTfawBusy() {
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m_memTfawBusy++;
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}
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void MemCntrlProfiler::profileMemRefresh() {
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m_memRefresh++;
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}
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void MemCntrlProfiler::profileMemRead() {
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m_memRead++;
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}
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void MemCntrlProfiler::profileMemWrite() {
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m_memWrite++;
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}
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void MemCntrlProfiler::profileMemWaitCycles(int cycles) {
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m_memWaitCycles += cycles;
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}
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void MemCntrlProfiler::profileMemInputQ(int cycles) {
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m_memInputQ += cycles;
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}
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void MemCntrlProfiler::profileMemBankQ(int cycles) {
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m_memBankQ += cycles;
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}
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void MemCntrlProfiler::profileMemArbWait(int cycles) {
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m_memArbWait += cycles;
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}
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void MemCntrlProfiler::profileMemRandBusy() {
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m_memRandBusy++;
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}
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void MemCntrlProfiler::profileMemNotOld() {
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m_memNotOld++;
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}
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