2007-04-09 09:59:56 +02:00
|
|
|
|
|
|
|
|
---------- Begin Simulation Statistics ----------
|
|
|
|
|
global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
2007-04-13 16:00:42 +02:00
|
|
|
global.BPredUnit.BTBHits 3021 # Number of BTB hits
|
|
|
|
|
global.BPredUnit.BTBLookups 7086 # Number of BTB lookups
|
2007-04-09 09:59:56 +02:00
|
|
|
global.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
|
|
|
|
|
global.BPredUnit.condIncorrect 2077 # Number of conditional branches incorrect
|
2007-04-13 16:00:42 +02:00
|
|
|
global.BPredUnit.condPredicted 7877 # Number of conditional branches predicted
|
|
|
|
|
global.BPredUnit.lookups 7877 # Number of BP lookups
|
2007-04-09 09:59:56 +02:00
|
|
|
global.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
|
2007-04-13 16:00:42 +02:00
|
|
|
host_inst_rate 4388 # Simulator instruction rate (inst/s)
|
|
|
|
|
host_mem_usage 179936 # Number of bytes of host memory used
|
|
|
|
|
host_seconds 2.50 # Real time elapsed on the host
|
|
|
|
|
host_tick_rate 568121 # Simulator tick rate (ticks/s)
|
2007-04-09 09:59:56 +02:00
|
|
|
memdepunit.memDep.conflictingLoads 12 # Number of conflicting loads.
|
|
|
|
|
memdepunit.memDep.conflictingStores 0 # Number of conflicting stores.
|
|
|
|
|
memdepunit.memDep.insertedLoads 3250 # Number of loads inserted to the mem dependence unit.
|
|
|
|
|
memdepunit.memDep.insertedStores 2817 # Number of stores inserted to the mem dependence unit.
|
|
|
|
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
|
|
|
|
sim_insts 10976 # Number of instructions simulated
|
|
|
|
|
sim_seconds 0.000001 # Number of seconds simulated
|
2007-04-13 16:00:42 +02:00
|
|
|
sim_ticks 1421207 # Number of ticks simulated
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.commit.COM:branches 2152 # Number of branches committed
|
2007-04-13 16:00:42 +02:00
|
|
|
system.cpu.commit.COM:bw_lim_events 225 # number cycles where commit BW limit reached
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
|
|
|
|
|
system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
|
2007-04-13 16:00:42 +02:00
|
|
|
system.cpu.commit.COM:committed_per_cycle.samples 220766
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.commit.COM:committed_per_cycle.min_value 0
|
2007-04-13 16:00:42 +02:00
|
|
|
0 215368 9755.49%
|
|
|
|
|
1 2915 132.04%
|
|
|
|
|
2 1196 54.18%
|
|
|
|
|
3 673 30.48%
|
|
|
|
|
4 208 9.42%
|
|
|
|
|
5 79 3.58%
|
|
|
|
|
6 91 4.12%
|
2007-04-09 09:59:56 +02:00
|
|
|
7 11 0.50%
|
2007-04-13 16:00:42 +02:00
|
|
|
8 225 10.19%
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.commit.COM:committed_per_cycle.max_value 8
|
|
|
|
|
system.cpu.commit.COM:committed_per_cycle.end_dist
|
|
|
|
|
|
|
|
|
|
system.cpu.commit.COM:count 10976 # Number of instructions committed
|
|
|
|
|
system.cpu.commit.COM:loads 1462 # Number of loads committed
|
|
|
|
|
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
|
|
|
|
|
system.cpu.commit.COM:refs 2760 # Number of memory references committed
|
|
|
|
|
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
|
|
|
|
|
system.cpu.commit.branchMispredicts 2077 # The number of times a branch was mispredicted
|
|
|
|
|
system.cpu.commit.commitCommittedInsts 10976 # The number of committed instructions
|
|
|
|
|
system.cpu.commit.commitNonSpecStalls 327 # The number of times commit has been forced to stall to communicate backwards
|
|
|
|
|
system.cpu.commit.commitSquashedInsts 14263 # The number of squashed insts skipped by commit
|
|
|
|
|
system.cpu.committedInsts 10976 # Number of Instructions Simulated
|
|
|
|
|
system.cpu.committedInsts_total 10976 # Number of Instructions Simulated
|
2007-04-13 16:00:42 +02:00
|
|
|
system.cpu.cpi 129.483145 # CPI: Cycles Per Instruction
|
|
|
|
|
system.cpu.cpi_total 129.483145 # CPI: Total CPI of All Threads
|
|
|
|
|
system.cpu.dcache.ReadReq_accesses 2738 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_miss_latency 6586.074627 # average ReadReq miss latency
|
|
|
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 6513.166667 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.dcache.ReadReq_hits 2604 # number of ReadReq hits
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_latency 882534 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_miss_rate 0.048941 # miss rate for ReadReq accesses
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.dcache.ReadReq_misses 134 # number of ReadReq misses
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_hits 68 # number of ReadReq MSHR hits
|
2007-04-13 16:00:42 +02:00
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency 429869 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate 0.024105 # mshr miss rate for ReadReq accesses
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.dcache.ReadReq_mshr_misses 66 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.dcache.SwapReq_accesses 6 # number of SwapReq accesses(hits+misses)
|
|
|
|
|
system.cpu.dcache.SwapReq_hits 6 # number of SwapReq hits
|
|
|
|
|
system.cpu.dcache.WriteReq_accesses 1292 # number of WriteReq accesses(hits+misses)
|
2007-04-13 16:00:42 +02:00
|
|
|
system.cpu.dcache.WriteReq_avg_miss_latency 7962.583924 # average WriteReq miss latency
|
|
|
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 7138.593023 # average WriteReq mshr miss latency
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.dcache.WriteReq_hits 869 # number of WriteReq hits
|
2007-04-13 16:00:42 +02:00
|
|
|
system.cpu.dcache.WriteReq_miss_latency 3368173 # number of WriteReq miss cycles
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.dcache.WriteReq_miss_rate 0.327399 # miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_misses 423 # number of WriteReq misses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_hits 337 # number of WriteReq MSHR hits
|
2007-04-13 16:00:42 +02:00
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency 613919 # number of WriteReq MSHR miss cycles
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate 0.066563 # mshr miss rate for WriteReq accesses
|
|
|
|
|
system.cpu.dcache.WriteReq_mshr_misses 86 # number of WriteReq MSHR misses
|
|
|
|
|
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
2007-04-13 16:00:42 +02:00
|
|
|
system.cpu.dcache.avg_refs 22.888158 # Average number of references to valid blocks.
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
2007-04-13 16:00:42 +02:00
|
|
|
system.cpu.dcache.demand_accesses 4030 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.dcache.demand_avg_miss_latency 7631.430880 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency 6867.026316 # average overall mshr miss latency
|
|
|
|
|
system.cpu.dcache.demand_hits 3473 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.dcache.demand_miss_latency 4250707 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.dcache.demand_miss_rate 0.138213 # miss rate for demand accesses
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.dcache.demand_misses 557 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.dcache.demand_mshr_hits 405 # number of demand (read+write) MSHR hits
|
2007-04-13 16:00:42 +02:00
|
|
|
system.cpu.dcache.demand_mshr_miss_latency 1043788 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.demand_mshr_miss_rate 0.037717 # mshr miss rate for demand accesses
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.dcache.demand_mshr_misses 152 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2007-04-13 16:00:42 +02:00
|
|
|
system.cpu.dcache.overall_accesses 4030 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.dcache.overall_avg_miss_latency 7631.430880 # average overall miss latency
|
|
|
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency 6867.026316 # average overall mshr miss latency
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
2007-04-13 16:00:42 +02:00
|
|
|
system.cpu.dcache.overall_hits 3473 # number of overall hits
|
|
|
|
|
system.cpu.dcache.overall_miss_latency 4250707 # number of overall miss cycles
|
|
|
|
|
system.cpu.dcache.overall_miss_rate 0.138213 # miss rate for overall accesses
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.dcache.overall_misses 557 # number of overall misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_hits 405 # number of overall MSHR hits
|
2007-04-13 16:00:42 +02:00
|
|
|
system.cpu.dcache.overall_mshr_miss_latency 1043788 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_miss_rate 0.037717 # mshr miss rate for overall accesses
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.dcache.overall_mshr_misses 152 # number of overall MSHR misses
|
|
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
|
|
|
|
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
|
|
|
|
system.cpu.dcache.replacements 0 # number of replacements
|
|
|
|
|
system.cpu.dcache.sampled_refs 152 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2007-04-13 16:00:42 +02:00
|
|
|
system.cpu.dcache.tagsinuse 90.938565 # Cycle average of tags in use
|
|
|
|
|
system.cpu.dcache.total_refs 3479 # Total number of references to valid blocks.
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.dcache.writebacks 0 # number of writebacks
|
2007-04-13 16:00:42 +02:00
|
|
|
system.cpu.decode.DECODE:BlockedCycles 192302 # Number of cycles decode is blocked
|
|
|
|
|
system.cpu.decode.DECODE:DecodedInsts 39763 # Number of instructions handled by decode
|
|
|
|
|
system.cpu.decode.DECODE:IdleCycles 19973 # Number of cycles decode is idle
|
|
|
|
|
system.cpu.decode.DECODE:RunCycles 8441 # Number of cycles decode is running
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.decode.DECODE:SquashCycles 3162 # Number of cycles decode is squashing
|
2007-04-13 16:00:42 +02:00
|
|
|
system.cpu.decode.DECODE:UnblockCycles 50 # Number of cycles decode is unblocking
|
|
|
|
|
system.cpu.fetch.Branches 7877 # Number of branches that fetch encountered
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.fetch.CacheLines 5085 # Number of cache lines fetched
|
2007-04-13 16:00:42 +02:00
|
|
|
system.cpu.fetch.Cycles 14430 # Number of cycles fetch has run and was not squashing or blocked
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.fetch.IcacheSquashes 745 # Number of outstanding Icache misses that were squashed
|
2007-04-13 16:00:42 +02:00
|
|
|
system.cpu.fetch.Insts 43366 # Number of instructions fetch has processed
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.fetch.SquashCycles 2134 # Number of cycles fetch has spent squashing
|
2007-04-13 16:00:42 +02:00
|
|
|
system.cpu.fetch.branchRate 0.035176 # Number of branch fetches per cycle
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.fetch.icacheStallCycles 5085 # Number of cycles fetch is stalled on an Icache miss
|
2007-04-13 16:00:42 +02:00
|
|
|
system.cpu.fetch.predictedBranches 3021 # Number of branches that fetch has predicted taken
|
|
|
|
|
system.cpu.fetch.rate 0.193660 # Number of inst fetches per cycle
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
|
2007-04-13 16:00:42 +02:00
|
|
|
system.cpu.fetch.rateDist.samples 223928
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.fetch.rateDist.min_value 0
|
2007-04-13 16:00:42 +02:00
|
|
|
0 214584 9582.72%
|
|
|
|
|
1 2258 100.84%
|
|
|
|
|
2 658 29.38%
|
|
|
|
|
3 958 42.78%
|
|
|
|
|
4 553 24.70%
|
|
|
|
|
5 816 36.44%
|
|
|
|
|
6 951 42.47%
|
|
|
|
|
7 280 12.50%
|
|
|
|
|
8 2870 128.17%
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.fetch.rateDist.max_value 8
|
|
|
|
|
system.cpu.fetch.rateDist.end_dist
|
|
|
|
|
|
|
|
|
|
system.cpu.icache.ReadReq_accesses 5085 # number of ReadReq accesses(hits+misses)
|
2007-04-13 16:00:42 +02:00
|
|
|
system.cpu.icache.ReadReq_avg_miss_latency 5150.152209 # average ReadReq miss latency
|
|
|
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency 4503.673025 # average ReadReq mshr miss latency
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.icache.ReadReq_hits 4474 # number of ReadReq hits
|
2007-04-13 16:00:42 +02:00
|
|
|
system.cpu.icache.ReadReq_miss_latency 3146743 # number of ReadReq miss cycles
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.icache.ReadReq_miss_rate 0.120157 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.ReadReq_misses 611 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_hits 244 # number of ReadReq MSHR hits
|
2007-04-13 16:00:42 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency 1652848 # number of ReadReq MSHR miss cycles
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate 0.072173 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_misses 367 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.avg_refs 12.325069 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
|
|
|
system.cpu.icache.demand_accesses 5085 # number of demand (read+write) accesses
|
2007-04-13 16:00:42 +02:00
|
|
|
system.cpu.icache.demand_avg_miss_latency 5150.152209 # average overall miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency 4503.673025 # average overall mshr miss latency
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.icache.demand_hits 4474 # number of demand (read+write) hits
|
2007-04-13 16:00:42 +02:00
|
|
|
system.cpu.icache.demand_miss_latency 3146743 # number of demand (read+write) miss cycles
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.icache.demand_miss_rate 0.120157 # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.demand_misses 611 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.icache.demand_mshr_hits 244 # number of demand (read+write) MSHR hits
|
2007-04-13 16:00:42 +02:00
|
|
|
system.cpu.icache.demand_mshr_miss_latency 1652848 # number of demand (read+write) MSHR miss cycles
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.icache.demand_mshr_miss_rate 0.072173 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.demand_mshr_misses 367 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
|
system.cpu.icache.overall_accesses 5085 # number of overall (read+write) accesses
|
2007-04-13 16:00:42 +02:00
|
|
|
system.cpu.icache.overall_avg_miss_latency 5150.152209 # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency 4503.673025 # average overall mshr miss latency
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.icache.overall_hits 4474 # number of overall hits
|
2007-04-13 16:00:42 +02:00
|
|
|
system.cpu.icache.overall_miss_latency 3146743 # number of overall miss cycles
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.icache.overall_miss_rate 0.120157 # miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.overall_misses 611 # number of overall misses
|
|
|
|
|
system.cpu.icache.overall_mshr_hits 244 # number of overall MSHR hits
|
2007-04-13 16:00:42 +02:00
|
|
|
system.cpu.icache.overall_mshr_miss_latency 1652848 # number of overall MSHR miss cycles
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.icache.overall_mshr_miss_rate 0.072173 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.overall_mshr_misses 367 # number of overall MSHR misses
|
|
|
|
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
|
|
|
|
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
|
|
|
|
system.cpu.icache.replacements 1 # number of replacements
|
|
|
|
|
system.cpu.icache.sampled_refs 363 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2007-04-13 16:00:42 +02:00
|
|
|
system.cpu.icache.tagsinuse 172.868641 # Cycle average of tags in use
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.icache.total_refs 4474 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.icache.writebacks 0 # number of writebacks
|
2007-04-13 16:00:42 +02:00
|
|
|
system.cpu.idleCycles 1197280 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
|
|
|
system.cpu.iew.EXEC:branches 3577 # Number of branches executed
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.iew.EXEC:nop 0 # number of nop insts executed
|
2007-04-13 16:00:42 +02:00
|
|
|
system.cpu.iew.EXEC:rate 0.092802 # Inst execution rate
|
|
|
|
|
system.cpu.iew.EXEC:refs 5258 # number of memory reference insts executed
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.iew.EXEC:stores 2386 # Number of stores executed
|
|
|
|
|
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
|
|
|
|
|
system.cpu.iew.WB:consumers 9737 # num instructions consuming a value
|
2007-04-13 16:00:42 +02:00
|
|
|
system.cpu.iew.WB:count 19771 # cumulative count of insts written-back
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.iew.WB:fanout 0.790901 # average fanout of values written-back
|
|
|
|
|
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
|
|
|
|
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
|
|
|
system.cpu.iew.WB:producers 7701 # num instructions producing a value
|
2007-04-13 16:00:42 +02:00
|
|
|
system.cpu.iew.WB:rate 0.088292 # insts written-back per cycle
|
|
|
|
|
system.cpu.iew.WB:sent 20063 # cumulative count of insts sent to commit
|
|
|
|
|
system.cpu.iew.branchMispredicts 2594 # Number of branch mispredicts detected at execute
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.iew.iewBlockCycles 476 # Number of cycles IEW is blocking
|
|
|
|
|
system.cpu.iew.iewDispLoadInsts 3250 # Number of dispatched load instructions
|
|
|
|
|
system.cpu.iew.iewDispNonSpecInsts 617 # Number of dispatched non-speculative instructions
|
2007-04-13 16:00:42 +02:00
|
|
|
system.cpu.iew.iewDispSquashedInsts 2694 # Number of squashed instructions skipped by dispatch
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.iew.iewDispStoreInsts 2817 # Number of dispatched store instructions
|
|
|
|
|
system.cpu.iew.iewDispatchedInsts 25240 # Number of instructions dispatched to IQ
|
2007-04-13 16:00:42 +02:00
|
|
|
system.cpu.iew.iewExecLoadInsts 2872 # Number of load instructions executed
|
|
|
|
|
system.cpu.iew.iewExecSquashedInsts 1777 # Number of squashed instructions skipped in execute
|
|
|
|
|
system.cpu.iew.iewExecutedInsts 20781 # Number of executed instructions
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.iew.iewIQFullEvents 7 # Number of times the IQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
|
|
|
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
|
|
|
|
|
system.cpu.iew.iewSquashCycles 3162 # Number of cycles IEW is squashing
|
|
|
|
|
system.cpu.iew.iewUnblockCycles 35 # Number of cycles IEW is unblocking
|
|
|
|
|
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
|
|
|
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
|
|
|
|
system.cpu.iew.lsq.thread.0.forwLoads 39 # Number of loads that had data forwarded from stores
|
|
|
|
|
system.cpu.iew.lsq.thread.0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed
|
|
|
|
|
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
|
|
|
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
|
|
|
system.cpu.iew.lsq.thread.0.memOrderViolation 54 # Number of memory ordering violations
|
|
|
|
|
system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled
|
|
|
|
|
system.cpu.iew.lsq.thread.0.squashedLoads 1788 # Number of loads squashed
|
|
|
|
|
system.cpu.iew.lsq.thread.0.squashedStores 1519 # Number of stores squashed
|
|
|
|
|
system.cpu.iew.memOrderViolationEvents 54 # Number of memory order violations
|
2007-04-13 16:00:42 +02:00
|
|
|
system.cpu.iew.predictedNotTakenIncorrect 963 # Number of branches that were predicted not taken incorrectly
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.iew.predictedTakenIncorrect 1631 # Number of branches that were predicted taken incorrectly
|
|
|
|
|
system.cpu.ipc 0.007723 # IPC: Instructions Per Cycle
|
|
|
|
|
system.cpu.ipc_total 0.007723 # IPC: Total IPC of All Threads
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0 22558 # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0.start_dist
|
|
|
|
|
(null) 1831 8.12% # Type of FU issued
|
|
|
|
|
IntAlu 15054 66.73% # Type of FU issued
|
|
|
|
|
IntMult 0 0.00% # Type of FU issued
|
|
|
|
|
IntDiv 0 0.00% # Type of FU issued
|
|
|
|
|
FloatAdd 0 0.00% # Type of FU issued
|
|
|
|
|
FloatCmp 0 0.00% # Type of FU issued
|
|
|
|
|
FloatCvt 0 0.00% # Type of FU issued
|
|
|
|
|
FloatMult 0 0.00% # Type of FU issued
|
|
|
|
|
FloatDiv 0 0.00% # Type of FU issued
|
|
|
|
|
FloatSqrt 0 0.00% # Type of FU issued
|
|
|
|
|
MemRead 3091 13.70% # Type of FU issued
|
|
|
|
|
MemWrite 2582 11.45% # Type of FU issued
|
|
|
|
|
IprAccess 0 0.00% # Type of FU issued
|
|
|
|
|
InstPrefetch 0 0.00% # Type of FU issued
|
|
|
|
|
system.cpu.iq.ISSUE:FU_type_0.end_dist
|
|
|
|
|
system.cpu.iq.ISSUE:fu_busy_cnt 162 # FU busy when requested
|
|
|
|
|
system.cpu.iq.ISSUE:fu_busy_rate 0.007181 # FU busy rate (busy events/executed inst)
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full.start_dist
|
|
|
|
|
(null) 0 0.00% # attempts to use FU when none available
|
|
|
|
|
IntAlu 42 25.93% # attempts to use FU when none available
|
|
|
|
|
IntMult 0 0.00% # attempts to use FU when none available
|
|
|
|
|
IntDiv 0 0.00% # attempts to use FU when none available
|
|
|
|
|
FloatAdd 0 0.00% # attempts to use FU when none available
|
|
|
|
|
FloatCmp 0 0.00% # attempts to use FU when none available
|
|
|
|
|
FloatCvt 0 0.00% # attempts to use FU when none available
|
|
|
|
|
FloatMult 0 0.00% # attempts to use FU when none available
|
|
|
|
|
FloatDiv 0 0.00% # attempts to use FU when none available
|
|
|
|
|
FloatSqrt 0 0.00% # attempts to use FU when none available
|
|
|
|
|
MemRead 14 8.64% # attempts to use FU when none available
|
|
|
|
|
MemWrite 106 65.43% # attempts to use FU when none available
|
|
|
|
|
IprAccess 0 0.00% # attempts to use FU when none available
|
|
|
|
|
InstPrefetch 0 0.00% # attempts to use FU when none available
|
|
|
|
|
system.cpu.iq.ISSUE:fu_full.end_dist
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
|
2007-04-13 16:00:42 +02:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle.samples 223928
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
|
2007-04-13 16:00:42 +02:00
|
|
|
0 214838 9594.07%
|
|
|
|
|
1 3976 177.56%
|
|
|
|
|
2 1244 55.55%
|
|
|
|
|
3 1359 60.69%
|
|
|
|
|
4 1316 58.77%
|
|
|
|
|
5 612 27.33%
|
|
|
|
|
6 444 19.83%
|
|
|
|
|
7 83 3.71%
|
|
|
|
|
8 56 2.50%
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
|
|
|
|
|
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
|
|
|
|
|
|
2007-04-13 16:00:42 +02:00
|
|
|
system.cpu.iq.ISSUE:rate 0.100738 # Inst issue rate
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.iq.iqInstsAdded 24623 # Number of instructions added to the IQ (excludes non-spec)
|
|
|
|
|
system.cpu.iq.iqInstsIssued 22558 # Number of instructions issued
|
|
|
|
|
system.cpu.iq.iqNonSpecInstsAdded 617 # Number of non-speculative instructions added to the IQ
|
|
|
|
|
system.cpu.iq.iqSquashedInstsExamined 11469 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
|
|
|
system.cpu.iq.iqSquashedInstsIssued 174 # Number of squashed instructions issued
|
|
|
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 290 # Number of squashed non-spec instructions that were removed
|
|
|
|
|
system.cpu.iq.iqSquashedOperandsExamined 5834 # Number of squashed operands that are examined and possibly removed from graph
|
|
|
|
|
system.cpu.l2cache.ReadReq_accesses 513 # number of ReadReq accesses(hits+misses)
|
2007-04-13 16:00:42 +02:00
|
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency 4755.715400 # average ReadReq miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2343.752437 # average ReadReq mshr miss latency
|
|
|
|
|
system.cpu.l2cache.ReadReq_miss_latency 2439682 # number of ReadReq miss cycles
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_misses 513 # number of ReadReq misses
|
2007-04-13 16:00:42 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 1202345 # number of ReadReq MSHR miss cycles
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.l2cache.ReadReq_mshr_misses 513 # number of ReadReq MSHR misses
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
|
|
|
system.cpu.l2cache.demand_accesses 513 # number of demand (read+write) accesses
|
2007-04-13 16:00:42 +02:00
|
|
|
system.cpu.l2cache.demand_avg_miss_latency 4755.715400 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 2343.752437 # average overall mshr miss latency
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits
|
2007-04-13 16:00:42 +02:00
|
|
|
system.cpu.l2cache.demand_miss_latency 2439682 # number of demand (read+write) miss cycles
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_misses 513 # number of demand (read+write) misses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
2007-04-13 16:00:42 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency 1202345 # number of demand (read+write) MSHR miss cycles
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses 513 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
|
system.cpu.l2cache.overall_accesses 513 # number of overall (read+write) accesses
|
2007-04-13 16:00:42 +02:00
|
|
|
system.cpu.l2cache.overall_avg_miss_latency 4755.715400 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 2343.752437 # average overall mshr miss latency
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
|
|
|
|
system.cpu.l2cache.overall_hits 0 # number of overall hits
|
2007-04-13 16:00:42 +02:00
|
|
|
system.cpu.l2cache.overall_miss_latency 2439682 # number of overall miss cycles
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_misses 513 # number of overall misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
2007-04-13 16:00:42 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency 1202345 # number of overall MSHR miss cycles
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses 513 # number of overall MSHR misses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
|
|
|
|
system.cpu.l2cache.replacements 0 # number of replacements
|
|
|
|
|
system.cpu.l2cache.sampled_refs 512 # Sample count of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2007-04-13 16:00:42 +02:00
|
|
|
system.cpu.l2cache.tagsinuse 262.945674 # Cycle average of tags in use
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.l2cache.writebacks 0 # number of writebacks
|
2007-04-13 16:00:42 +02:00
|
|
|
system.cpu.numCycles 223928 # number of cpu cycles simulated
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.rename.RENAME:BlockCycles 960 # Number of cycles rename is blocking
|
|
|
|
|
system.cpu.rename.RENAME:CommittedMaps 9868 # Number of HB maps that are committed
|
|
|
|
|
system.cpu.rename.RENAME:IQFullEvents 2 # Number of times rename has blocked due to IQ full
|
2007-04-13 16:00:42 +02:00
|
|
|
system.cpu.rename.RENAME:IdleCycles 21302 # Number of cycles rename is idle
|
|
|
|
|
system.cpu.rename.RENAME:LSQFullEvents 411 # Number of times rename has blocked due to LSQ full
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.rename.RENAME:ROBFullEvents 4 # Number of times rename has blocked due to ROB full
|
|
|
|
|
system.cpu.rename.RENAME:RenameLookups 46931 # Number of register rename lookups that rename has made
|
2007-04-13 16:00:42 +02:00
|
|
|
system.cpu.rename.RENAME:RenamedInsts 31249 # Number of instructions processed by rename
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.rename.RENAME:RenamedOperands 25831 # Number of destination operands rename has renamed
|
2007-04-13 16:00:42 +02:00
|
|
|
system.cpu.rename.RENAME:RunCycles 7136 # Number of cycles rename is running
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.rename.RENAME:SquashCycles 3162 # Number of cycles rename is squashing
|
2007-04-13 16:00:42 +02:00
|
|
|
system.cpu.rename.RENAME:UnblockCycles 614 # Number of cycles rename is unblocking
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.rename.RENAME:UndoneMaps 15963 # Number of HB maps that are undone due to squashing
|
2007-04-13 16:00:42 +02:00
|
|
|
system.cpu.rename.RENAME:serializeStallCycles 190754 # count of cycles rename stalled for serializing inst
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.rename.RENAME:serializingInsts 638 # count of serializing insts renamed
|
2007-04-13 16:00:42 +02:00
|
|
|
system.cpu.rename.RENAME:skidInsts 5529 # count of insts added to the skid buffer
|
2007-04-09 09:59:56 +02:00
|
|
|
system.cpu.rename.RENAME:tempSerializingInsts 629 # count of temporary serializing insts renamed
|
|
|
|
|
system.cpu.timesIdled 289 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
|
|
|
system.cpu.workload.PROG:num_syscalls 8 # Number of system calls
|
|
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
