363 lines
10 KiB
C++
363 lines
10 KiB
C++
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/*
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* Copyright (c) 2016, Dresden University of Technology (TU Dresden)
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
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* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Christian Menard
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*/
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#include <sstream>
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#include "params/ExternalMaster.hh"
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#include "sc_master_port.hh"
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#include "sim/system.hh"
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namespace Gem5SystemC
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{
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PacketPtr
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SCMasterPort::generatePacket(tlm::tlm_generic_payload& trans)
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{
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Request::Flags flags;
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auto req = new Request(trans.get_address(), trans.get_data_length(), flags,
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owner.masterId);
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MemCmd cmd;
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switch (trans.get_command()) {
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case tlm::TLM_READ_COMMAND:
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cmd = MemCmd::ReadReq;
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break;
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case tlm::TLM_WRITE_COMMAND:
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cmd = MemCmd::WriteReq;
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break;
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default:
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SC_REPORT_FATAL("SCMasterPort",
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"received transaction with unsupported command");
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}
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/*
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* Allocate a new Packet. The packet will be deleted when it returns from
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* the gem5 world as a response.
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*/
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auto pkt = new Packet(req, cmd);
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pkt->dataStatic(trans.get_data_ptr());
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return pkt;
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}
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void
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SCMasterPort::destroyPacket(PacketPtr pkt)
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{
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delete pkt;
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}
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SCMasterPort::SCMasterPort(const std::string& name_,
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const std::string& systemc_name,
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ExternalMaster& owner_,
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Module& module)
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: ExternalMaster::Port(name_, owner_),
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tSocket(systemc_name.c_str()),
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peq(this, &SCMasterPort::peq_cb),
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waitForRetry(false),
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pendingRequest(nullptr),
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needToSendRetry(false),
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responseInProgress(false),
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module(module)
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{
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auto system =
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dynamic_cast<const ExternalMasterParams*>(owner_.params())->system;
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/*
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* Register the TLM non-blocking interface when using gem5 Timing mode and
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* the TLM blocking interface when using the gem5 Atomic mode.
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* Then the magic (TM) in simple_target_socket automatically transforms
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* non-blocking in blocking transactions and vice versa.
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*
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* NOTE: The mode may change during execution.
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*/
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if (system->isTimingMode()) {
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SC_REPORT_INFO("SCMasterPort", "register non-blocking interface");
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tSocket.register_nb_transport_fw(this,
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&SCMasterPort::nb_transport_fw);
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} else if (system->isAtomicMode()) {
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SC_REPORT_INFO("SCMasterPort", "register blocking interface");
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tSocket.register_b_transport(this, &SCMasterPort::b_transport);
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} else {
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panic("gem5 operates neither in Timing nor in Atomic mode");
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}
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tSocket.register_transport_dbg(this, &SCMasterPort::transport_dbg);
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}
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void
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SCMasterPort::checkTransaction(tlm::tlm_generic_payload& trans)
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{
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if (trans.is_response_error()) {
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std::stringstream ss;
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ss << "Transaction returned with error, response status = "
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<< trans.get_response_string();
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SC_REPORT_ERROR("TLM-2", ss.str().c_str());
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}
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}
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tlm::tlm_sync_enum
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SCMasterPort::nb_transport_fw(tlm::tlm_generic_payload& trans,
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tlm::tlm_phase& phase, sc_core::sc_time& delay)
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{
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uint64_t adr = trans.get_address();
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unsigned len = trans.get_data_length();
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unsigned char* byteEnable = trans.get_byte_enable_ptr();
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unsigned width = trans.get_streaming_width();
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// check the transaction attributes for unsupported features ...
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if (byteEnable != 0) {
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trans.set_response_status(tlm::TLM_BYTE_ENABLE_ERROR_RESPONSE);
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return tlm::TLM_COMPLETED;
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}
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if (width < len) { // is this a burst request?
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trans.set_response_status(tlm::TLM_BURST_ERROR_RESPONSE);
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return tlm::TLM_COMPLETED;
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}
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// ... and queue the valid transaction
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peq.notify(trans, phase, delay);
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return tlm::TLM_ACCEPTED;
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}
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void
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SCMasterPort::peq_cb(tlm::tlm_generic_payload& trans,
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const tlm::tlm_phase& phase)
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{
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// catch up with SystemC time
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module.catchup();
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assert(curTick() == sc_core::sc_time_stamp().value());
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switch (phase) {
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case tlm::BEGIN_REQ:
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handleBeginReq(trans);
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break;
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case tlm::END_RESP:
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handleEndResp(trans);
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break;
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default:
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panic("unimplemented phase in callback");
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}
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// the functions called above may have scheduled gem5 events
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// -> notify the event loop handler
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module.notify();
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}
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void
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SCMasterPort::handleBeginReq(tlm::tlm_generic_payload& trans)
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{
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sc_assert(!waitForRetry);
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sc_assert(pendingRequest == nullptr);
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trans.acquire();
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auto pkt = generatePacket(trans);
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auto tlmSenderState = new TlmSenderState(trans);
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pkt->pushSenderState(tlmSenderState);
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if (sendTimingReq(pkt)) { // port is free -> send END_REQ immediately
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sendEndReq(trans);
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} else { // port is blocked -> wait for retry before sending END_REQ
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waitForRetry = true;
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pendingRequest = &trans;
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}
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}
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void
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SCMasterPort::handleEndResp(tlm::tlm_generic_payload& trans)
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{
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sc_assert(responseInProgress);
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responseInProgress = false;
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checkTransaction(trans);
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if (needToSendRetry) {
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sendRetryResp();
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needToSendRetry = false;
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}
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}
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void
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SCMasterPort::sendEndReq(tlm::tlm_generic_payload& trans)
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{
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tlm::tlm_phase phase = tlm::END_REQ;
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auto delay = sc_core::SC_ZERO_TIME;
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auto status = tSocket->nb_transport_bw(trans, phase, delay);
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panic_if(status != tlm::TLM_ACCEPTED,
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"Unexpected status after sending END_REQ");
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}
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void
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SCMasterPort::b_transport(tlm::tlm_generic_payload& trans,
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sc_core::sc_time& t)
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{
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auto pkt = generatePacket(trans);
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// send an atomic request to gem5
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Tick ticks = sendAtomic(pkt);
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panic_if(!pkt->isResponse(), "Packet sending failed!\n");
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// one tick is a pico second
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auto delay =
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sc_core::sc_time((double)(ticks / SimClock::Int::ps), sc_core::SC_PS);
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// update time
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t += delay;
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destroyPacket(pkt);
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trans.set_response_status(tlm::TLM_OK_RESPONSE);
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}
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unsigned int
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SCMasterPort::transport_dbg(tlm::tlm_generic_payload& trans)
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{
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auto pkt = generatePacket(trans);
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sendFunctional(pkt);
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destroyPacket(pkt);
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return trans.get_data_length();
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}
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bool
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SCMasterPort::get_direct_mem_ptr(tlm::tlm_generic_payload& trans,
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tlm::tlm_dmi& dmi_data)
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{
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return false;
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}
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bool
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SCMasterPort::recvTimingResp(PacketPtr pkt)
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{
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// exclusion rule
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// We need to Wait for END_RESP before sending next BEGIN_RESP
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if (responseInProgress) {
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sc_assert(!needToSendRetry);
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needToSendRetry = true;
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return false;
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}
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sc_assert(pkt->isResponse());
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// pay for annotaded transport delays
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auto delay =
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sc_core::sc_time::from_value(pkt->payloadDelay + pkt->headerDelay);
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auto tlmSenderState = dynamic_cast<TlmSenderState*>(pkt->popSenderState());
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auto& trans = tlmSenderState->trans;
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// clean up
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delete tlmSenderState;
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destroyPacket(pkt);
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sendBeginResp(trans, delay);
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trans.release();
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return true;
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}
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void
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SCMasterPort::sendBeginResp(tlm::tlm_generic_payload& trans,
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sc_core::sc_time& delay)
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{
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tlm::tlm_phase phase = tlm::BEGIN_RESP;
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trans.set_response_status(tlm::TLM_OK_RESPONSE);
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auto status = tSocket->nb_transport_bw(trans, phase, delay);
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if (status == tlm::TLM_COMPLETED ||
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status == tlm::TLM_UPDATED && phase == tlm::END_RESP) {
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// transaction completed -> no need to wait for tlm::END_RESP
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responseInProgress = false;
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} else if (status == tlm::TLM_ACCEPTED) {
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// we need to wait for tlm::END_RESP
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responseInProgress = true;
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} else {
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panic("Unexpected status after sending BEGIN_RESP");
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}
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}
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void
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SCMasterPort::recvReqRetry()
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{
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sc_assert(waitForRetry);
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sc_assert(pendingRequest != nullptr);
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auto& trans = *pendingRequest;
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waitForRetry = false;
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pendingRequest = nullptr;
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// retry
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handleBeginReq(trans);
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}
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void
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SCMasterPort::recvRangeChange()
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{
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SC_REPORT_WARNING("SCMasterPort",
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"received address range change but ignored it");
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}
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class SCMasterPortHandler : public ExternalMaster::Handler
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{
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Module& module;
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public:
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SCMasterPortHandler(Module& module) : module(module) {}
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ExternalMaster::Port* getExternalPort(const std::string& name,
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ExternalMaster& owner,
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const std::string& port_data)
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{
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// This will make a new initiatiator port
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return new SCMasterPort(name, port_data, owner, module);
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}
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};
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void
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SCMasterPort::registerPortHandler(Module& module)
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{
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ExternalMaster::registerHandler("tlm_master",
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new SCMasterPortHandler(module));
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}
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} // namespace Gem5SystemC
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