2011-02-08 04:23:11 +01:00
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---------- Begin Simulation Statistics ----------
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2011-02-23 22:10:50 +01:00
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host_inst_rate 844061 # Simulator instruction rate (inst/s)
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host_mem_usage 378168 # Number of bytes of host memory used
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host_seconds 59.91 # Real time elapsed on the host
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host_tick_rate 1914863662 # Simulator tick rate (ticks/s)
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2011-02-08 04:23:11 +01:00
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sim_freq 1000000000000 # Frequency of simulated ticks
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2011-02-23 22:10:50 +01:00
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sim_insts 50570667 # Number of instructions simulated
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2011-02-12 01:29:36 +01:00
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sim_seconds 0.114727 # Number of seconds simulated
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sim_ticks 114726567000 # Number of ticks simulated
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system.cpu.dcache.LoadLockedReq_accesses::0 100290 # number of LoadLockedReq accesses(hits+misses)
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system.cpu.dcache.LoadLockedReq_accesses::total 100290 # number of LoadLockedReq accesses(hits+misses)
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system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14562.978560 # average LoadLockedReq miss latency
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2011-02-08 04:23:11 +01:00
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system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency
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system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency
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2011-02-12 01:29:36 +01:00
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system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11562.978560 # average LoadLockedReq mshr miss latency
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2011-02-08 04:23:11 +01:00
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system.cpu.dcache.LoadLockedReq_avg_mshr_uncacheable_latency inf # average LoadLockedReq mshr uncacheable latency
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2011-02-12 01:29:36 +01:00
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system.cpu.dcache.LoadLockedReq_hits::0 95066 # number of LoadLockedReq hits
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system.cpu.dcache.LoadLockedReq_hits::total 95066 # number of LoadLockedReq hits
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system.cpu.dcache.LoadLockedReq_miss_latency 76077000 # number of LoadLockedReq miss cycles
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system.cpu.dcache.LoadLockedReq_miss_rate::0 0.052089 # miss rate for LoadLockedReq accesses
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system.cpu.dcache.LoadLockedReq_misses::0 5224 # number of LoadLockedReq misses
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system.cpu.dcache.LoadLockedReq_misses::total 5224 # number of LoadLockedReq misses
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system.cpu.dcache.LoadLockedReq_mshr_miss_latency 60405000 # number of LoadLockedReq MSHR miss cycles
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system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.052089 # mshr miss rate for LoadLockedReq accesses
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2011-02-08 04:23:11 +01:00
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system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses
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system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses
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2011-02-12 01:29:36 +01:00
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system.cpu.dcache.LoadLockedReq_mshr_misses 5224 # number of LoadLockedReq MSHR misses
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system.cpu.dcache.LoadLockedReq_mshr_uncacheable_latency 310532000 # number of LoadLockedReq MSHR uncacheable cycles
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system.cpu.dcache.ReadReq_accesses::0 7828656 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_accesses::total 7828656 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_avg_miss_latency::0 15679.539912 # average ReadReq miss latency
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2011-02-08 04:23:11 +01:00
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system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
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2011-02-12 01:29:36 +01:00
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12679.195749 # average ReadReq mshr miss latency
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2011-02-08 04:23:11 +01:00
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system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
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2011-02-12 01:29:36 +01:00
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system.cpu.dcache.ReadReq_hits::0 7590397 # number of ReadReq hits
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system.cpu.dcache.ReadReq_hits::total 7590397 # number of ReadReq hits
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system.cpu.dcache.ReadReq_miss_latency 3735791500 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_rate::0 0.030434 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_misses::0 238259 # number of ReadReq misses
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system.cpu.dcache.ReadReq_misses::total 238259 # number of ReadReq misses
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system.cpu.dcache.ReadReq_mshr_miss_latency 3020932500 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.030434 # mshr miss rate for ReadReq accesses
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2011-02-08 04:23:11 +01:00
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system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
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2011-02-12 01:29:36 +01:00
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system.cpu.dcache.ReadReq_mshr_misses 238259 # number of ReadReq MSHR misses
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system.cpu.dcache.ReadReq_mshr_uncacheable_latency 38191771500 # number of ReadReq MSHR uncacheable cycles
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system.cpu.dcache.StoreCondReq_accesses::0 100289 # number of StoreCondReq accesses(hits+misses)
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system.cpu.dcache.StoreCondReq_accesses::total 100289 # number of StoreCondReq accesses(hits+misses)
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system.cpu.dcache.StoreCondReq_hits::0 100289 # number of StoreCondReq hits
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system.cpu.dcache.StoreCondReq_hits::total 100289 # number of StoreCondReq hits
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system.cpu.dcache.WriteReq_accesses::0 6674369 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_accesses::total 6674369 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_avg_miss_latency::0 40728.962545 # average WriteReq miss latency
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2011-02-08 04:23:11 +01:00
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system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency
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2011-02-12 01:29:36 +01:00
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency 37728.712808 # average WriteReq mshr miss latency
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2011-02-08 04:23:11 +01:00
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system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
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2011-02-12 01:29:36 +01:00
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system.cpu.dcache.WriteReq_hits::0 6502188 # number of WriteReq hits
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system.cpu.dcache.WriteReq_hits::total 6502188 # number of WriteReq hits
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system.cpu.dcache.WriteReq_miss_latency 7012753500 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_rate::0 0.025797 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_misses::0 172181 # number of WriteReq misses
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system.cpu.dcache.WriteReq_misses::total 172181 # number of WriteReq misses
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system.cpu.dcache.WriteReq_mshr_miss_latency 6496167500 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.025797 # mshr miss rate for WriteReq accesses
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2011-02-08 04:23:11 +01:00
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system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses
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2011-02-12 01:29:36 +01:00
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system.cpu.dcache.WriteReq_mshr_misses 172181 # number of WriteReq MSHR misses
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system.cpu.dcache.WriteReq_mshr_uncacheable_latency 927436000 # number of WriteReq MSHR uncacheable cycles
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2011-02-08 04:23:11 +01:00
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system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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2011-02-12 01:29:36 +01:00
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system.cpu.dcache.avg_refs 34.529769 # Average number of references to valid blocks.
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2011-02-08 04:23:11 +01:00
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system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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2011-02-12 01:29:36 +01:00
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system.cpu.dcache.demand_accesses::0 14503025 # number of demand (read+write) accesses
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2011-02-08 04:23:11 +01:00
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system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses
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2011-02-12 01:29:36 +01:00
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system.cpu.dcache.demand_accesses::total 14503025 # number of demand (read+write) accesses
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system.cpu.dcache.demand_avg_miss_latency::0 26187.859370 # average overall miss latency
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2011-02-08 04:23:11 +01:00
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system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency
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system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency
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2011-02-12 01:29:36 +01:00
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system.cpu.dcache.demand_avg_mshr_miss_latency 23187.554819 # average overall mshr miss latency
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system.cpu.dcache.demand_hits::0 14092585 # number of demand (read+write) hits
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2011-02-08 04:23:11 +01:00
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system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits
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2011-02-12 01:29:36 +01:00
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system.cpu.dcache.demand_hits::total 14092585 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_latency 10748545000 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_rate::0 0.028300 # miss rate for demand accesses
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2011-02-08 04:23:11 +01:00
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system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses
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system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses
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2011-02-12 01:29:36 +01:00
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system.cpu.dcache.demand_misses::0 410440 # number of demand (read+write) misses
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2011-02-08 04:23:11 +01:00
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system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses
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2011-02-12 01:29:36 +01:00
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system.cpu.dcache.demand_misses::total 410440 # number of demand (read+write) misses
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2011-02-08 04:23:11 +01:00
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system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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2011-02-12 01:29:36 +01:00
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system.cpu.dcache.demand_mshr_miss_latency 9517100000 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_rate::0 0.028300 # mshr miss rate for demand accesses
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2011-02-08 04:23:11 +01:00
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system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
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2011-02-12 01:29:36 +01:00
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system.cpu.dcache.demand_mshr_misses 410440 # number of demand (read+write) MSHR misses
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2011-02-08 04:23:11 +01:00
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.occ_%::0 0.994530 # Average percentage of cache occupancy
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2011-02-12 01:29:36 +01:00
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system.cpu.dcache.occ_blocks::0 509.199247 # Average occupied blocks per context
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system.cpu.dcache.overall_accesses::0 14503025 # number of overall (read+write) accesses
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2011-02-08 04:23:11 +01:00
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system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses
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2011-02-12 01:29:36 +01:00
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system.cpu.dcache.overall_accesses::total 14503025 # number of overall (read+write) accesses
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system.cpu.dcache.overall_avg_miss_latency::0 26187.859370 # average overall miss latency
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2011-02-08 04:23:11 +01:00
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system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency
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system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency
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2011-02-12 01:29:36 +01:00
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system.cpu.dcache.overall_avg_mshr_miss_latency 23187.554819 # average overall mshr miss latency
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2011-02-08 04:23:11 +01:00
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
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2011-02-12 01:29:36 +01:00
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system.cpu.dcache.overall_hits::0 14092585 # number of overall hits
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2011-02-08 04:23:11 +01:00
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system.cpu.dcache.overall_hits::1 0 # number of overall hits
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2011-02-12 01:29:36 +01:00
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system.cpu.dcache.overall_hits::total 14092585 # number of overall hits
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system.cpu.dcache.overall_miss_latency 10748545000 # number of overall miss cycles
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system.cpu.dcache.overall_miss_rate::0 0.028300 # miss rate for overall accesses
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2011-02-08 04:23:11 +01:00
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system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses
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system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses
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2011-02-12 01:29:36 +01:00
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system.cpu.dcache.overall_misses::0 410440 # number of overall misses
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2011-02-08 04:23:11 +01:00
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system.cpu.dcache.overall_misses::1 0 # number of overall misses
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2011-02-12 01:29:36 +01:00
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system.cpu.dcache.overall_misses::total 410440 # number of overall misses
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2011-02-08 04:23:11 +01:00
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system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
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2011-02-12 01:29:36 +01:00
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system.cpu.dcache.overall_mshr_miss_latency 9517100000 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_rate::0 0.028300 # mshr miss rate for overall accesses
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2011-02-08 04:23:11 +01:00
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system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
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2011-02-12 01:29:36 +01:00
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system.cpu.dcache.overall_mshr_misses 410440 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_uncacheable_latency 39119207500 # number of overall MSHR uncacheable cycles
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2011-02-08 04:23:11 +01:00
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system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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2011-02-12 01:29:36 +01:00
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system.cpu.dcache.replacements 413327 # number of replacements
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system.cpu.dcache.sampled_refs 413839 # Sample count of references to valid blocks.
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2011-02-08 04:23:11 +01:00
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system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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2011-02-12 01:29:36 +01:00
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system.cpu.dcache.tagsinuse 509.199247 # Cycle average of tags in use
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system.cpu.dcache.total_refs 14289765 # Total number of references to valid blocks.
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2011-02-08 04:23:11 +01:00
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system.cpu.dcache.warmup_cycle 658097000 # Cycle when the warmup percentage was hit.
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2011-02-12 01:29:36 +01:00
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system.cpu.dcache.writebacks 381698 # number of writebacks
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system.cpu.dtb.accesses 15531532 # DTB accesses
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2011-02-08 04:23:11 +01:00
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system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
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2011-02-12 01:29:36 +01:00
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system.cpu.dtb.flush_entries 2220 # Number of entries that have been flushed from TLB
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2011-02-08 04:23:11 +01:00
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system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed
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system.cpu.dtb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID
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system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.dtb.flush_tlb_mva_asid 33670 # Number of times TLB was flushed by MVA & ASID
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2011-02-12 01:29:36 +01:00
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system.cpu.dtb.hits 15525999 # DTB hits
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2011-02-08 04:23:11 +01:00
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system.cpu.dtb.inst_accesses 0 # ITB inst accesses
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system.cpu.dtb.inst_hits 0 # ITB inst hits
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system.cpu.dtb.inst_misses 0 # ITB inst misses
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2011-02-12 01:29:36 +01:00
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system.cpu.dtb.misses 5533 # DTB misses
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2011-02-08 04:23:11 +01:00
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system.cpu.dtb.perms_faults 255 # Number of TLB faults due to permissions restrictions
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2011-02-12 01:29:36 +01:00
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system.cpu.dtb.prefetch_faults 757 # Number of TLB faults due to prefetch
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system.cpu.dtb.read_accesses 8744287 # DTB read accesses
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system.cpu.dtb.read_hits 8739733 # DTB read hits
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system.cpu.dtb.read_misses 4554 # DTB read misses
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system.cpu.dtb.write_accesses 6787245 # DTB write accesses
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system.cpu.dtb.write_hits 6786266 # DTB write hits
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system.cpu.dtb.write_misses 979 # DTB write misses
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system.cpu.icache.ReadReq_accesses::0 41555414 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_accesses::total 41555414 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_avg_miss_latency::0 14790.398445 # average ReadReq miss latency
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2011-02-08 04:23:11 +01:00
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system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
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system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
|
2011-02-12 01:29:36 +01:00
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system.cpu.icache.ReadReq_avg_mshr_miss_latency 11789.103925 # average ReadReq mshr miss latency
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2011-02-08 04:23:11 +01:00
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system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
|
2011-02-12 01:29:36 +01:00
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|
|
system.cpu.icache.ReadReq_hits::0 41121276 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.ReadReq_hits::total 41121276 # number of ReadReq hits
|
|
|
|
|
system.cpu.icache.ReadReq_miss_latency 6421074000 # number of ReadReq miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_miss_rate::0 0.010447 # miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.ReadReq_misses::0 434138 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.ReadReq_misses::total 434138 # number of ReadReq misses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_latency 5118098000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::0 0.010447 # mshr miss rate for ReadReq accesses
|
2011-02-08 04:23:11 +01:00
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
|
2011-02-12 01:29:36 +01:00
|
|
|
system.cpu.icache.ReadReq_mshr_misses 434138 # number of ReadReq MSHR misses
|
2011-02-08 04:23:11 +01:00
|
|
|
system.cpu.icache.ReadReq_mshr_uncacheable_latency 349111000 # number of ReadReq MSHR uncacheable cycles
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
2011-02-12 01:29:36 +01:00
|
|
|
system.cpu.icache.avg_refs 94.719366 # Average number of references to valid blocks.
|
2011-02-08 04:23:11 +01:00
|
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
2011-02-12 01:29:36 +01:00
|
|
|
system.cpu.icache.demand_accesses::0 41555414 # number of demand (read+write) accesses
|
2011-02-08 04:23:11 +01:00
|
|
|
system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses
|
2011-02-12 01:29:36 +01:00
|
|
|
system.cpu.icache.demand_accesses::total 41555414 # number of demand (read+write) accesses
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency::0 14790.398445 # average overall miss latency
|
2011-02-08 04:23:11 +01:00
|
|
|
system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency
|
|
|
|
|
system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency
|
2011-02-12 01:29:36 +01:00
|
|
|
system.cpu.icache.demand_avg_mshr_miss_latency 11789.103925 # average overall mshr miss latency
|
|
|
|
|
system.cpu.icache.demand_hits::0 41121276 # number of demand (read+write) hits
|
2011-02-08 04:23:11 +01:00
|
|
|
system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits
|
2011-02-12 01:29:36 +01:00
|
|
|
system.cpu.icache.demand_hits::total 41121276 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.icache.demand_miss_latency 6421074000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.icache.demand_miss_rate::0 0.010447 # miss rate for demand accesses
|
2011-02-08 04:23:11 +01:00
|
|
|
system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses
|
2011-02-12 01:29:36 +01:00
|
|
|
system.cpu.icache.demand_misses::0 434138 # number of demand (read+write) misses
|
2011-02-08 04:23:11 +01:00
|
|
|
system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses
|
2011-02-12 01:29:36 +01:00
|
|
|
system.cpu.icache.demand_misses::total 434138 # number of demand (read+write) misses
|
2011-02-08 04:23:11 +01:00
|
|
|
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
2011-02-12 01:29:36 +01:00
|
|
|
system.cpu.icache.demand_mshr_miss_latency 5118098000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_rate::0 0.010447 # mshr miss rate for demand accesses
|
2011-02-08 04:23:11 +01:00
|
|
|
system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
|
2011-02-12 01:29:36 +01:00
|
|
|
system.cpu.icache.demand_mshr_misses 434138 # number of demand (read+write) MSHR misses
|
2011-02-08 04:23:11 +01:00
|
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-02-12 01:29:36 +01:00
|
|
|
system.cpu.icache.occ_%::0 0.946115 # Average percentage of cache occupancy
|
|
|
|
|
system.cpu.icache.occ_blocks::0 484.411008 # Average occupied blocks per context
|
|
|
|
|
system.cpu.icache.overall_accesses::0 41555414 # number of overall (read+write) accesses
|
2011-02-08 04:23:11 +01:00
|
|
|
system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses
|
2011-02-12 01:29:36 +01:00
|
|
|
system.cpu.icache.overall_accesses::total 41555414 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency::0 14790.398445 # average overall miss latency
|
2011-02-08 04:23:11 +01:00
|
|
|
system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency
|
|
|
|
|
system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency
|
2011-02-12 01:29:36 +01:00
|
|
|
system.cpu.icache.overall_avg_mshr_miss_latency 11789.103925 # average overall mshr miss latency
|
2011-02-08 04:23:11 +01:00
|
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
|
2011-02-12 01:29:36 +01:00
|
|
|
system.cpu.icache.overall_hits::0 41121276 # number of overall hits
|
2011-02-08 04:23:11 +01:00
|
|
|
system.cpu.icache.overall_hits::1 0 # number of overall hits
|
2011-02-12 01:29:36 +01:00
|
|
|
system.cpu.icache.overall_hits::total 41121276 # number of overall hits
|
|
|
|
|
system.cpu.icache.overall_miss_latency 6421074000 # number of overall miss cycles
|
|
|
|
|
system.cpu.icache.overall_miss_rate::0 0.010447 # miss rate for overall accesses
|
2011-02-08 04:23:11 +01:00
|
|
|
system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses
|
2011-02-12 01:29:36 +01:00
|
|
|
system.cpu.icache.overall_misses::0 434138 # number of overall misses
|
2011-02-08 04:23:11 +01:00
|
|
|
system.cpu.icache.overall_misses::1 0 # number of overall misses
|
2011-02-12 01:29:36 +01:00
|
|
|
system.cpu.icache.overall_misses::total 434138 # number of overall misses
|
2011-02-08 04:23:11 +01:00
|
|
|
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
2011-02-12 01:29:36 +01:00
|
|
|
system.cpu.icache.overall_mshr_miss_latency 5118098000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_rate::0 0.010447 # mshr miss rate for overall accesses
|
2011-02-08 04:23:11 +01:00
|
|
|
system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
|
2011-02-12 01:29:36 +01:00
|
|
|
system.cpu.icache.overall_mshr_misses 434138 # number of overall MSHR misses
|
2011-02-08 04:23:11 +01:00
|
|
|
system.cpu.icache.overall_mshr_uncacheable_latency 349111000 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-02-12 01:29:36 +01:00
|
|
|
system.cpu.icache.replacements 433626 # number of replacements
|
|
|
|
|
system.cpu.icache.sampled_refs 434138 # Sample count of references to valid blocks.
|
2011-02-08 04:23:11 +01:00
|
|
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2011-02-12 01:29:36 +01:00
|
|
|
system.cpu.icache.tagsinuse 484.411008 # Cycle average of tags in use
|
|
|
|
|
system.cpu.icache.total_refs 41121276 # Total number of references to valid blocks.
|
2011-02-08 04:23:11 +01:00
|
|
|
system.cpu.icache.warmup_cycle 14253306000 # Cycle when the warmup percentage was hit.
|
2011-02-12 01:29:36 +01:00
|
|
|
system.cpu.icache.writebacks 34007 # number of writebacks
|
2011-02-08 04:23:11 +01:00
|
|
|
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
2011-02-12 01:29:36 +01:00
|
|
|
system.cpu.itb.accesses 41558233 # DTB accesses
|
2011-02-08 04:23:11 +01:00
|
|
|
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
|
|
|
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
|
|
|
system.cpu.itb.flush_entries 1478 # Number of entries that have been flushed from TLB
|
|
|
|
|
system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed
|
|
|
|
|
system.cpu.itb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID
|
|
|
|
|
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
|
|
|
system.cpu.itb.flush_tlb_mva_asid 33670 # Number of times TLB was flushed by MVA & ASID
|
2011-02-12 01:29:36 +01:00
|
|
|
system.cpu.itb.hits 41555414 # DTB hits
|
|
|
|
|
system.cpu.itb.inst_accesses 41558233 # ITB inst accesses
|
|
|
|
|
system.cpu.itb.inst_hits 41555414 # ITB inst hits
|
2011-02-08 04:23:11 +01:00
|
|
|
system.cpu.itb.inst_misses 2819 # ITB inst misses
|
|
|
|
|
system.cpu.itb.misses 2819 # DTB misses
|
|
|
|
|
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
|
|
|
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
|
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
|
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
|
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
|
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
|
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
|
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
|
|
|
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
|
|
|
|
system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
|
|
|
|
|
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
2011-02-12 01:29:36 +01:00
|
|
|
system.cpu.numCycles 229453134 # number of cpu cycles simulated
|
2011-02-08 04:23:13 +01:00
|
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
|
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
2011-02-12 01:29:36 +01:00
|
|
|
system.cpu.num_busy_cycles 229453134 # Number of busy cycles
|
2011-02-08 04:23:13 +01:00
|
|
|
system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls
|
|
|
|
|
system.cpu.num_fp_alu_accesses 6058 # Number of float alu accesses
|
|
|
|
|
system.cpu.num_fp_insts 6058 # number of float instructions
|
|
|
|
|
system.cpu.num_fp_register_reads 4226 # number of times the floating registers were read
|
|
|
|
|
system.cpu.num_fp_register_writes 1834 # number of times the floating registers were written
|
|
|
|
|
system.cpu.num_func_calls 0 # number of times a function call or return occured
|
|
|
|
|
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
2011-02-23 22:10:50 +01:00
|
|
|
system.cpu.num_insts 50570667 # Number of instructions executed
|
2011-02-12 01:29:36 +01:00
|
|
|
system.cpu.num_int_alu_accesses 41841366 # Number of integer alu accesses
|
|
|
|
|
system.cpu.num_int_insts 41841366 # number of integer instructions
|
|
|
|
|
system.cpu.num_int_register_reads 138034734 # number of times the integer registers were read
|
|
|
|
|
system.cpu.num_int_register_writes 34325875 # number of times the integer registers were written
|
|
|
|
|
system.cpu.num_load_insts 9211791 # Number of load instructions
|
|
|
|
|
system.cpu.num_mem_refs 16296219 # number of memory refs
|
|
|
|
|
system.cpu.num_store_insts 7084428 # Number of store instructions
|
2011-02-08 04:23:11 +01:00
|
|
|
system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
|
|
|
system.iocache.avg_refs no_value # Average number of references to valid blocks.
|
|
|
|
|
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.iocache.cache_copies 0 # number of cache copies performed
|
|
|
|
|
system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses
|
|
|
|
|
system.iocache.demand_accesses::1 0 # number of demand (read+write) accesses
|
|
|
|
|
system.iocache.demand_accesses::total 0 # number of demand (read+write) accesses
|
|
|
|
|
system.iocache.demand_avg_miss_latency::0 no_value # average overall miss latency
|
|
|
|
|
system.iocache.demand_avg_miss_latency::1 no_value # average overall miss latency
|
|
|
|
|
system.iocache.demand_avg_miss_latency::total no_value # average overall miss latency
|
|
|
|
|
system.iocache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
|
|
|
|
|
system.iocache.demand_hits::0 0 # number of demand (read+write) hits
|
|
|
|
|
system.iocache.demand_hits::1 0 # number of demand (read+write) hits
|
|
|
|
|
system.iocache.demand_hits::total 0 # number of demand (read+write) hits
|
|
|
|
|
system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles
|
|
|
|
|
system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses
|
|
|
|
|
system.iocache.demand_miss_rate::1 no_value # miss rate for demand accesses
|
|
|
|
|
system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses
|
|
|
|
|
system.iocache.demand_misses::0 0 # number of demand (read+write) misses
|
|
|
|
|
system.iocache.demand_misses::1 0 # number of demand (read+write) misses
|
|
|
|
|
system.iocache.demand_misses::total 0 # number of demand (read+write) misses
|
|
|
|
|
system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
|
|
|
|
system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.iocache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses
|
|
|
|
|
system.iocache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses
|
|
|
|
|
system.iocache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses
|
|
|
|
|
system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
|
|
|
|
|
system.iocache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
|
system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses
|
|
|
|
|
system.iocache.overall_accesses::1 0 # number of overall (read+write) accesses
|
|
|
|
|
system.iocache.overall_accesses::total 0 # number of overall (read+write) accesses
|
|
|
|
|
system.iocache.overall_avg_miss_latency::0 no_value # average overall miss latency
|
|
|
|
|
system.iocache.overall_avg_miss_latency::1 no_value # average overall miss latency
|
|
|
|
|
system.iocache.overall_avg_miss_latency::total no_value # average overall miss latency
|
|
|
|
|
system.iocache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
|
|
|
|
|
system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
|
|
|
system.iocache.overall_hits::0 0 # number of overall hits
|
|
|
|
|
system.iocache.overall_hits::1 0 # number of overall hits
|
|
|
|
|
system.iocache.overall_hits::total 0 # number of overall hits
|
|
|
|
|
system.iocache.overall_miss_latency 0 # number of overall miss cycles
|
|
|
|
|
system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses
|
|
|
|
|
system.iocache.overall_miss_rate::1 no_value # miss rate for overall accesses
|
|
|
|
|
system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses
|
|
|
|
|
system.iocache.overall_misses::0 0 # number of overall misses
|
|
|
|
|
system.iocache.overall_misses::1 0 # number of overall misses
|
|
|
|
|
system.iocache.overall_misses::total 0 # number of overall misses
|
|
|
|
|
system.iocache.overall_mshr_hits 0 # number of overall MSHR hits
|
|
|
|
|
system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
|
|
|
|
|
system.iocache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses
|
|
|
|
|
system.iocache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses
|
|
|
|
|
system.iocache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses
|
|
|
|
|
system.iocache.overall_mshr_misses 0 # number of overall MSHR misses
|
|
|
|
|
system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.iocache.replacements 0 # number of replacements
|
|
|
|
|
system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
|
|
|
|
|
system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
|
|
|
system.iocache.tagsinuse 0 # Cycle average of tags in use
|
|
|
|
|
system.iocache.total_refs 0 # Total number of references to valid blocks.
|
|
|
|
|
system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.iocache.writebacks 0 # number of writebacks
|
|
|
|
|
system.l2c.LoadLockedReq_avg_mshr_uncacheable_latency inf # average LoadLockedReq mshr uncacheable latency
|
2011-02-12 01:29:36 +01:00
|
|
|
system.l2c.LoadLockedReq_mshr_uncacheable_latency 234360000 # number of LoadLockedReq MSHR uncacheable cycles
|
|
|
|
|
system.l2c.ReadExReq_accesses::0 170356 # number of ReadExReq accesses(hits+misses)
|
|
|
|
|
system.l2c.ReadExReq_accesses::total 170356 # number of ReadExReq accesses(hits+misses)
|
2011-02-08 04:23:11 +01:00
|
|
|
system.l2c.ReadExReq_avg_miss_latency::0 52000 # average ReadExReq miss latency
|
|
|
|
|
system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency
|
|
|
|
|
system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency
|
|
|
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
|
2011-02-12 01:29:36 +01:00
|
|
|
system.l2c.ReadExReq_hits::0 62546 # number of ReadExReq hits
|
|
|
|
|
system.l2c.ReadExReq_hits::total 62546 # number of ReadExReq hits
|
|
|
|
|
system.l2c.ReadExReq_miss_latency 5606120000 # number of ReadExReq miss cycles
|
|
|
|
|
system.l2c.ReadExReq_miss_rate::0 0.632851 # miss rate for ReadExReq accesses
|
|
|
|
|
system.l2c.ReadExReq_misses::0 107810 # number of ReadExReq misses
|
|
|
|
|
system.l2c.ReadExReq_misses::total 107810 # number of ReadExReq misses
|
|
|
|
|
system.l2c.ReadExReq_mshr_miss_latency 4312400000 # number of ReadExReq MSHR miss cycles
|
|
|
|
|
system.l2c.ReadExReq_mshr_miss_rate::0 0.632851 # mshr miss rate for ReadExReq accesses
|
2011-02-08 04:23:11 +01:00
|
|
|
system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses
|
|
|
|
|
system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses
|
2011-02-12 01:29:36 +01:00
|
|
|
system.l2c.ReadExReq_mshr_misses 107810 # number of ReadExReq MSHR misses
|
|
|
|
|
system.l2c.ReadReq_accesses::0 675489 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.l2c.ReadReq_accesses::1 5600 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.l2c.ReadReq_accesses::total 681089 # number of ReadReq accesses(hits+misses)
|
|
|
|
|
system.l2c.ReadReq_avg_miss_latency::0 52080.437900 # average ReadReq miss latency
|
|
|
|
|
system.l2c.ReadReq_avg_miss_latency::1 33725803.571429 # average ReadReq miss latency
|
|
|
|
|
system.l2c.ReadReq_avg_miss_latency::total 33777884.009328 # average ReadReq miss latency
|
2011-02-08 04:23:11 +01:00
|
|
|
system.l2c.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
|
|
|
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
|
2011-02-12 01:29:36 +01:00
|
|
|
system.l2c.ReadReq_hits::0 657357 # number of ReadReq hits
|
|
|
|
|
system.l2c.ReadReq_hits::1 5572 # number of ReadReq hits
|
|
|
|
|
system.l2c.ReadReq_hits::total 662929 # number of ReadReq hits
|
|
|
|
|
system.l2c.ReadReq_miss_latency 944322500 # number of ReadReq miss cycles
|
|
|
|
|
system.l2c.ReadReq_miss_rate::0 0.026843 # miss rate for ReadReq accesses
|
|
|
|
|
system.l2c.ReadReq_miss_rate::1 0.005000 # miss rate for ReadReq accesses
|
|
|
|
|
system.l2c.ReadReq_miss_rate::total 0.031843 # miss rate for ReadReq accesses
|
|
|
|
|
system.l2c.ReadReq_misses::0 18132 # number of ReadReq misses
|
|
|
|
|
system.l2c.ReadReq_misses::1 28 # number of ReadReq misses
|
|
|
|
|
system.l2c.ReadReq_misses::total 18160 # number of ReadReq misses
|
|
|
|
|
system.l2c.ReadReq_mshr_miss_latency 726400000 # number of ReadReq MSHR miss cycles
|
|
|
|
|
system.l2c.ReadReq_mshr_miss_rate::0 0.026884 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.l2c.ReadReq_mshr_miss_rate::1 3.242857 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.l2c.ReadReq_mshr_miss_rate::total 3.269741 # mshr miss rate for ReadReq accesses
|
|
|
|
|
system.l2c.ReadReq_mshr_misses 18160 # number of ReadReq MSHR misses
|
|
|
|
|
system.l2c.ReadReq_mshr_uncacheable_latency 29200446000 # number of ReadReq MSHR uncacheable cycles
|
|
|
|
|
system.l2c.UpgradeReq_accesses::0 1825 # number of UpgradeReq accesses(hits+misses)
|
|
|
|
|
system.l2c.UpgradeReq_accesses::total 1825 # number of UpgradeReq accesses(hits+misses)
|
|
|
|
|
system.l2c.UpgradeReq_avg_miss_latency::0 489.208633 # average UpgradeReq miss latency
|
2011-02-08 04:23:11 +01:00
|
|
|
system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency
|
|
|
|
|
system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency
|
|
|
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
|
2011-02-12 01:29:36 +01:00
|
|
|
system.l2c.UpgradeReq_hits::0 18 # number of UpgradeReq hits
|
|
|
|
|
system.l2c.UpgradeReq_hits::total 18 # number of UpgradeReq hits
|
|
|
|
|
system.l2c.UpgradeReq_miss_latency 884000 # number of UpgradeReq miss cycles
|
|
|
|
|
system.l2c.UpgradeReq_miss_rate::0 0.990137 # miss rate for UpgradeReq accesses
|
|
|
|
|
system.l2c.UpgradeReq_misses::0 1807 # number of UpgradeReq misses
|
|
|
|
|
system.l2c.UpgradeReq_misses::total 1807 # number of UpgradeReq misses
|
|
|
|
|
system.l2c.UpgradeReq_mshr_miss_latency 72280000 # number of UpgradeReq MSHR miss cycles
|
|
|
|
|
system.l2c.UpgradeReq_mshr_miss_rate::0 0.990137 # mshr miss rate for UpgradeReq accesses
|
2011-02-08 04:23:11 +01:00
|
|
|
system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses
|
|
|
|
|
system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses
|
2011-02-12 01:29:36 +01:00
|
|
|
system.l2c.UpgradeReq_mshr_misses 1807 # number of UpgradeReq MSHR misses
|
2011-02-08 04:23:11 +01:00
|
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
|
2011-02-12 01:29:36 +01:00
|
|
|
system.l2c.WriteReq_mshr_uncacheable_latency 740884000 # number of WriteReq MSHR uncacheable cycles
|
|
|
|
|
system.l2c.Writeback_accesses::0 415705 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.l2c.Writeback_accesses::total 415705 # number of Writeback accesses(hits+misses)
|
|
|
|
|
system.l2c.Writeback_hits::0 415705 # number of Writeback hits
|
|
|
|
|
system.l2c.Writeback_hits::total 415705 # number of Writeback hits
|
2011-02-08 04:23:11 +01:00
|
|
|
system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
|
|
|
system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
2011-02-12 01:29:36 +01:00
|
|
|
system.l2c.avg_refs 7.060757 # Average number of references to valid blocks.
|
2011-02-08 04:23:11 +01:00
|
|
|
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.l2c.cache_copies 0 # number of cache copies performed
|
2011-02-12 01:29:36 +01:00
|
|
|
system.l2c.demand_accesses::0 845845 # number of demand (read+write) accesses
|
|
|
|
|
system.l2c.demand_accesses::1 5600 # number of demand (read+write) accesses
|
|
|
|
|
system.l2c.demand_accesses::total 851445 # number of demand (read+write) accesses
|
|
|
|
|
system.l2c.demand_avg_miss_latency::0 52011.580728 # average overall miss latency
|
|
|
|
|
system.l2c.demand_avg_miss_latency::1 233944375 # average overall miss latency
|
|
|
|
|
system.l2c.demand_avg_miss_latency::total 233996386.580728 # average overall miss latency
|
2011-02-08 04:23:11 +01:00
|
|
|
system.l2c.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
2011-02-12 01:29:36 +01:00
|
|
|
system.l2c.demand_hits::0 719903 # number of demand (read+write) hits
|
|
|
|
|
system.l2c.demand_hits::1 5572 # number of demand (read+write) hits
|
|
|
|
|
system.l2c.demand_hits::total 725475 # number of demand (read+write) hits
|
|
|
|
|
system.l2c.demand_miss_latency 6550442500 # number of demand (read+write) miss cycles
|
|
|
|
|
system.l2c.demand_miss_rate::0 0.148895 # miss rate for demand accesses
|
|
|
|
|
system.l2c.demand_miss_rate::1 0.005000 # miss rate for demand accesses
|
|
|
|
|
system.l2c.demand_miss_rate::total 0.153895 # miss rate for demand accesses
|
|
|
|
|
system.l2c.demand_misses::0 125942 # number of demand (read+write) misses
|
|
|
|
|
system.l2c.demand_misses::1 28 # number of demand (read+write) misses
|
|
|
|
|
system.l2c.demand_misses::total 125970 # number of demand (read+write) misses
|
2011-02-08 04:23:11 +01:00
|
|
|
system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
2011-02-12 01:29:36 +01:00
|
|
|
system.l2c.demand_mshr_miss_latency 5038800000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.l2c.demand_mshr_miss_rate::0 0.148928 # mshr miss rate for demand accesses
|
|
|
|
|
system.l2c.demand_mshr_miss_rate::1 22.494643 # mshr miss rate for demand accesses
|
|
|
|
|
system.l2c.demand_mshr_miss_rate::total 22.643571 # mshr miss rate for demand accesses
|
|
|
|
|
system.l2c.demand_mshr_misses 125970 # number of demand (read+write) MSHR misses
|
2011-02-08 04:23:11 +01:00
|
|
|
system.l2c.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
2011-02-12 01:29:36 +01:00
|
|
|
system.l2c.occ_%::0 0.081481 # Average percentage of cache occupancy
|
|
|
|
|
system.l2c.occ_%::1 0.477898 # Average percentage of cache occupancy
|
|
|
|
|
system.l2c.occ_blocks::0 5339.953820 # Average occupied blocks per context
|
|
|
|
|
system.l2c.occ_blocks::1 31319.548737 # Average occupied blocks per context
|
|
|
|
|
system.l2c.overall_accesses::0 845845 # number of overall (read+write) accesses
|
|
|
|
|
system.l2c.overall_accesses::1 5600 # number of overall (read+write) accesses
|
|
|
|
|
system.l2c.overall_accesses::total 851445 # number of overall (read+write) accesses
|
|
|
|
|
system.l2c.overall_avg_miss_latency::0 52011.580728 # average overall miss latency
|
|
|
|
|
system.l2c.overall_avg_miss_latency::1 233944375 # average overall miss latency
|
|
|
|
|
system.l2c.overall_avg_miss_latency::total 233996386.580728 # average overall miss latency
|
2011-02-08 04:23:11 +01:00
|
|
|
system.l2c.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
|
|
|
|
system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
|
2011-02-12 01:29:36 +01:00
|
|
|
system.l2c.overall_hits::0 719903 # number of overall hits
|
|
|
|
|
system.l2c.overall_hits::1 5572 # number of overall hits
|
|
|
|
|
system.l2c.overall_hits::total 725475 # number of overall hits
|
|
|
|
|
system.l2c.overall_miss_latency 6550442500 # number of overall miss cycles
|
|
|
|
|
system.l2c.overall_miss_rate::0 0.148895 # miss rate for overall accesses
|
|
|
|
|
system.l2c.overall_miss_rate::1 0.005000 # miss rate for overall accesses
|
|
|
|
|
system.l2c.overall_miss_rate::total 0.153895 # miss rate for overall accesses
|
|
|
|
|
system.l2c.overall_misses::0 125942 # number of overall misses
|
|
|
|
|
system.l2c.overall_misses::1 28 # number of overall misses
|
|
|
|
|
system.l2c.overall_misses::total 125970 # number of overall misses
|
2011-02-08 04:23:11 +01:00
|
|
|
system.l2c.overall_mshr_hits 0 # number of overall MSHR hits
|
2011-02-12 01:29:36 +01:00
|
|
|
system.l2c.overall_mshr_miss_latency 5038800000 # number of overall MSHR miss cycles
|
|
|
|
|
system.l2c.overall_mshr_miss_rate::0 0.148928 # mshr miss rate for overall accesses
|
|
|
|
|
system.l2c.overall_mshr_miss_rate::1 22.494643 # mshr miss rate for overall accesses
|
|
|
|
|
system.l2c.overall_mshr_miss_rate::total 22.643571 # mshr miss rate for overall accesses
|
|
|
|
|
system.l2c.overall_mshr_misses 125970 # number of overall MSHR misses
|
|
|
|
|
system.l2c.overall_mshr_uncacheable_latency 29941330000 # number of overall MSHR uncacheable cycles
|
2011-02-08 04:23:11 +01:00
|
|
|
system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
2011-02-12 01:29:36 +01:00
|
|
|
system.l2c.replacements 93233 # number of replacements
|
|
|
|
|
system.l2c.sampled_refs 124676 # Sample count of references to valid blocks.
|
2011-02-08 04:23:11 +01:00
|
|
|
system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2011-02-12 01:29:36 +01:00
|
|
|
system.l2c.tagsinuse 36659.502556 # Cycle average of tags in use
|
|
|
|
|
system.l2c.total_refs 880307 # Total number of references to valid blocks.
|
2011-02-08 04:23:11 +01:00
|
|
|
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
2011-02-12 01:29:36 +01:00
|
|
|
system.l2c.writebacks 87349 # number of writebacks
|
2011-02-08 04:23:11 +01:00
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
