gem5/src/arch/x86/isa_traits.hh

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 * Authors: Gabe Black
 */

#ifndef __ARCH_X86_ISATRAITS_HH__
#define __ARCH_X86_ISATRAITS_HH__

#include "arch/x86/intregs.hh"
#include "arch/x86/max_inst_regs.hh"
#include "arch/x86/types.hh"
#include "arch/x86/x86_traits.hh"
#include "sim/host.hh"

class StaticInstPtr;

namespace LittleEndianGuest {}

namespace X86ISA
{
    //This makes sure the little endian version of certain functions
    //are used.
    using namespace LittleEndianGuest;
    using X86ISAInst::MaxInstSrcRegs;
    using X86ISAInst::MaxInstDestRegs;

    // X86 does not have a delay slot
#define ISA_HAS_DELAY_SLOT 0

    // X86 NOP (XCHG rAX, rAX)
    //XXX This needs to be set to an intermediate instruction struct
    //which encodes this instruction

    // These enumerate all the registers for dependence tracking.
    enum DependenceTags {
        //There are 16 microcode registers at the moment. This is an
        //unusually large constant to make sure there isn't overflow.
        FP_Base_DepTag = 128,
        Ctrl_Base_DepTag =
            FP_Base_DepTag +
            //mmx/x87 registers
            8 +
            //xmm registers
            16 * 2 +
            //The microcode fp registers
            8 +
            //The indices that are mapped over the fp stack
            8
    };

    // semantically meaningful register indices
    //There is no such register in X86
    const int ZeroReg = NUM_INTREGS;
    const int StackPointerReg = INTREG_RSP;
    //X86 doesn't seem to have a link register
    const int ReturnAddressReg = 0;
    const int ReturnValueReg = INTREG_RAX;
    const int FramePointerReg = INTREG_RBP;

    // Some OS syscalls use a second register (rdx) to return a second
    // value
    const int SyscallPseudoReturnReg = INTREG_RDX;

    //4k. This value is not constant on x86.
    const int LogVMPageSize = 12;
    const int VMPageSize = (1 << LogVMPageSize);

    const int PageShift = 12;
    const int PageBytes = 1ULL << PageShift;

    const int BranchPredAddrShiftAmt = 0;

    StaticInstPtr decodeInst(ExtMachInst);

    const Addr LoadAddrMask = ULL(-1);
};

#endif // __ARCH_X86_ISATRAITS_HH__