2009-04-06 03:53:15 +02:00
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// -*- mode:c++ -*-
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// Copyright (c) 2007-2008 The Florida State University
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met: redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer;
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// redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution;
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// neither the name of the copyright holders nor the names of its
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// Authors: Stephen Hines
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////////////////////////////////////////////////////////////////////
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//
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// Memory-format instructions
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//
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def template LoadStoreDeclare {{
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/**
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* Static instruction class for "%(mnemonic)s".
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*/
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class %(class_name)s : public %(base_class)s
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{
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protected:
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/**
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* "Fake" effective address computation class for "%(mnemonic)s".
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*/
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class EAComp : public %(base_class)s
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{
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public:
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/// Constructor
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2009-06-22 01:41:07 +02:00
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EAComp(ExtMachInst machInst);
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2009-04-06 03:53:15 +02:00
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%(BasicExecDeclare)s
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};
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/**
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* "Fake" memory access instruction class for "%(mnemonic)s".
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*/
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class MemAcc : public %(base_class)s
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{
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public:
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/// Constructor
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2009-06-22 01:41:07 +02:00
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MemAcc(ExtMachInst machInst);
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2009-04-06 03:53:15 +02:00
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%(BasicExecDeclare)s
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};
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public:
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/// Constructor.
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2009-06-22 01:41:07 +02:00
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%(class_name)s(ExtMachInst machInst);
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2009-04-06 03:53:15 +02:00
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%(BasicExecDeclare)s
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%(InitiateAccDeclare)s
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%(CompleteAccDeclare)s
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};
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}};
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def template InitiateAccDeclare {{
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Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const;
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}};
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def template CompleteAccDeclare {{
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Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const;
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}};
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def template EACompConstructor {{
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2009-06-22 01:41:07 +02:00
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inline %(class_name)s::EAComp::EAComp(ExtMachInst machInst)
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2009-04-06 03:53:15 +02:00
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: %(base_class)s("%(mnemonic)s (EAComp)", machInst, IntAluOp)
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{
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%(constructor)s;
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}
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}};
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def template MemAccConstructor {{
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2009-06-22 01:41:07 +02:00
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inline %(class_name)s::MemAcc::MemAcc(ExtMachInst machInst)
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2009-04-06 03:53:15 +02:00
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: %(base_class)s("%(mnemonic)s (MemAcc)", machInst, %(op_class)s)
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{
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%(constructor)s;
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}
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}};
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def template LoadStoreConstructor {{
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2009-06-22 01:41:07 +02:00
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inline %(class_name)s::%(class_name)s(ExtMachInst machInst)
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2009-04-06 03:53:15 +02:00
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: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
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new EAComp(machInst), new MemAcc(machInst))
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{
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%(constructor)s;
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}
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}};
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def template EACompExecute {{
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Fault
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%(class_name)s::EAComp::execute(%(CPU_exec_context)s *xc,
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Trace::InstRecord *traceData) const
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{
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Addr EA;
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Fault fault = NoFault;
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%(op_decl)s;
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%(op_rd)s;
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%(ea_code)s;
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2009-06-21 18:37:41 +02:00
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if (%(predicate_test)s)
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2009-04-06 03:53:15 +02:00
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{
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if (fault == NoFault) {
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%(op_wb)s;
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xc->setEA(EA);
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}
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}
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return fault;
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}
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}};
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def template LoadMemAccExecute {{
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Fault
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%(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
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Trace::InstRecord *traceData) const
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{
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Addr EA;
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Fault fault = NoFault;
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%(op_decl)s;
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%(op_rd)s;
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EA = xc->getEA();
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2009-06-21 18:37:41 +02:00
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if (%(predicate_test)s)
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2009-04-06 03:53:15 +02:00
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{
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if (fault == NoFault) {
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fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags);
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%(memacc_code)s;
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}
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if (fault == NoFault) {
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%(op_wb)s;
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}
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}
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return fault;
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}
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}};
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def template LoadExecute {{
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Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
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Trace::InstRecord *traceData) const
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{
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Addr EA;
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Fault fault = NoFault;
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%(op_decl)s;
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%(op_rd)s;
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%(ea_code)s;
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2009-06-21 18:37:41 +02:00
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if (%(predicate_test)s)
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2009-04-06 03:53:15 +02:00
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{
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if (fault == NoFault) {
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fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags);
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%(memacc_code)s;
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}
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if (fault == NoFault) {
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%(op_wb)s;
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}
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}
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return fault;
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}
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}};
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def template LoadInitiateAcc {{
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Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
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Trace::InstRecord *traceData) const
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{
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Addr EA;
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Fault fault = NoFault;
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%(op_src_decl)s;
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%(op_rd)s;
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%(ea_code)s;
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2009-06-21 18:37:41 +02:00
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if (%(predicate_test)s)
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2009-04-06 03:53:15 +02:00
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{
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if (fault == NoFault) {
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fault = xc->read(EA, (uint%(mem_acc_size)d_t &)Mem, memAccessFlags);
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}
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}
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return fault;
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}
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}};
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def template LoadCompleteAcc {{
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Fault %(class_name)s::completeAcc(PacketPtr pkt,
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%(CPU_exec_context)s *xc,
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Trace::InstRecord *traceData) const
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{
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Fault fault = NoFault;
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%(op_decl)s;
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%(op_rd)s;
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2009-06-21 18:37:41 +02:00
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if (%(predicate_test)s)
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2009-04-06 03:53:15 +02:00
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{
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// ARM instructions will not have a pkt if the predicate is false
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Mem = pkt->get<typeof(Mem)>();
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if (fault == NoFault) {
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%(memacc_code)s;
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}
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if (fault == NoFault) {
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%(op_wb)s;
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}
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}
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return fault;
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}
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}};
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def template StoreMemAccExecute {{
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Fault
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%(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
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Trace::InstRecord *traceData) const
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{
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Addr EA;
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Fault fault = NoFault;
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%(op_decl)s;
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%(op_rd)s;
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2009-06-21 18:37:41 +02:00
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if (%(predicate_test)s)
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2009-04-06 03:53:15 +02:00
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{
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EA = xc->getEA();
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if (fault == NoFault) {
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fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
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memAccessFlags, NULL);
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if (traceData) { traceData->setData(Mem); }
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}
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if (fault == NoFault) {
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%(op_wb)s;
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}
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}
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return fault;
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}
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}};
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def template StoreExecute {{
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Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
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Trace::InstRecord *traceData) const
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{
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Addr EA;
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Fault fault = NoFault;
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%(op_decl)s;
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%(op_rd)s;
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%(ea_code)s;
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2009-06-21 18:37:41 +02:00
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if (%(predicate_test)s)
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2009-04-06 03:53:15 +02:00
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{
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if (fault == NoFault) {
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%(memacc_code)s;
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}
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if (fault == NoFault) {
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fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
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memAccessFlags, NULL);
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if (traceData) { traceData->setData(Mem); }
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}
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if (fault == NoFault) {
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%(op_wb)s;
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}
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}
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return fault;
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}
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}};
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def template StoreInitiateAcc {{
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Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
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Trace::InstRecord *traceData) const
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{
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Addr EA;
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Fault fault = NoFault;
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%(op_decl)s;
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%(op_rd)s;
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%(ea_code)s;
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2009-06-21 18:37:41 +02:00
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if (%(predicate_test)s)
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2009-04-06 03:53:15 +02:00
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{
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if (fault == NoFault) {
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%(memacc_code)s;
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}
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if (fault == NoFault) {
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fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
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memAccessFlags, NULL);
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if (traceData) { traceData->setData(Mem); }
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}
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// Need to write back any potential address register update
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if (fault == NoFault) {
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%(op_wb)s;
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}
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}
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return fault;
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}
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}};
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def template StoreCompleteAcc {{
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Fault %(class_name)s::completeAcc(PacketPtr pkt,
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%(CPU_exec_context)s *xc,
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Trace::InstRecord *traceData) const
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{
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Fault fault = NoFault;
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2009-07-09 08:02:19 +02:00
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%(op_decl)s;
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%(op_rd)s;
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2009-04-06 03:53:15 +02:00
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2009-06-21 18:37:41 +02:00
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if (%(predicate_test)s)
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2009-04-06 03:53:15 +02:00
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{
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if (fault == NoFault) {
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%(op_wb)s;
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}
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}
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return fault;
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}
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}};
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def template StoreCondCompleteAcc {{
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Fault %(class_name)s::completeAcc(PacketPtr pkt,
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%(CPU_exec_context)s *xc,
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Trace::InstRecord *traceData) const
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{
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Fault fault = NoFault;
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%(op_dest_decl)s;
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2009-06-21 18:37:41 +02:00
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if (%(predicate_test)s)
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2009-04-06 03:53:15 +02:00
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{
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if (fault == NoFault) {
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%(op_wb)s;
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}
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}
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return fault;
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}
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}};
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def template MiscMemAccExecute {{
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Fault %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
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|
Trace::InstRecord *traceData) const
|
|
|
|
{
|
|
|
|
Addr EA;
|
|
|
|
Fault fault = NoFault;
|
|
|
|
|
|
|
|
%(op_decl)s;
|
|
|
|
%(op_rd)s;
|
|
|
|
|
2009-06-21 18:37:41 +02:00
|
|
|
if (%(predicate_test)s)
|
2009-04-06 03:53:15 +02:00
|
|
|
{
|
|
|
|
EA = xc->getEA();
|
|
|
|
|
|
|
|
if (fault == NoFault) {
|
|
|
|
%(memacc_code)s;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return NoFault;
|
|
|
|
}
|
|
|
|
}};
|
|
|
|
|
|
|
|
def template MiscExecute {{
|
|
|
|
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
|
|
|
|
Trace::InstRecord *traceData) const
|
|
|
|
{
|
|
|
|
Addr EA;
|
|
|
|
Fault fault = NoFault;
|
|
|
|
|
|
|
|
%(op_decl)s;
|
|
|
|
%(op_rd)s;
|
|
|
|
%(ea_code)s;
|
|
|
|
|
2009-06-21 18:37:41 +02:00
|
|
|
if (%(predicate_test)s)
|
2009-04-06 03:53:15 +02:00
|
|
|
{
|
|
|
|
if (fault == NoFault) {
|
|
|
|
%(memacc_code)s;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return NoFault;
|
|
|
|
}
|
|
|
|
}};
|
|
|
|
|
|
|
|
def template MiscInitiateAcc {{
|
|
|
|
Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
|
|
|
|
Trace::InstRecord *traceData) const
|
|
|
|
{
|
|
|
|
panic("Misc instruction does not support split access method!");
|
|
|
|
return NoFault;
|
|
|
|
}
|
|
|
|
}};
|
|
|
|
|
|
|
|
|
|
|
|
def template MiscCompleteAcc {{
|
|
|
|
Fault %(class_name)s::completeAcc(PacketPtr pkt,
|
|
|
|
%(CPU_exec_context)s *xc,
|
|
|
|
Trace::InstRecord *traceData) const
|
|
|
|
{
|
|
|
|
panic("Misc instruction does not support split access method!");
|
|
|
|
|
|
|
|
return NoFault;
|
|
|
|
}
|
|
|
|
}};
|
|
|
|
|
2009-07-09 08:02:19 +02:00
|
|
|
let {{
|
|
|
|
def buildPUBWLCase(p, u, b, w, l):
|
|
|
|
return (p << 4) + (u << 3) + (b << 2) + (w << 1) + (l << 0)
|
|
|
|
|
2009-07-09 08:02:19 +02:00
|
|
|
def buildMode2Inst(p, u, b, w, l, suffix, offset):
|
|
|
|
mnem = ("str", "ldr")[l]
|
|
|
|
op = ("-", "+")[u]
|
|
|
|
offset = op + ArmGenericCodeSubs(offset);
|
|
|
|
mem = ("Mem", "Mem.ub")[b]
|
|
|
|
code = ("%s = Rd;", "Rd = %s;")[l] % mem
|
|
|
|
ea_code = "EA = Rn %s;" % ("", offset)[p]
|
|
|
|
if p == 0 or w == 1:
|
|
|
|
code += "Rn = Rn %s;" % offset
|
|
|
|
if p == 0 and w == 0:
|
|
|
|
# Here's where we'll tack on a flag to make this a usermode access.
|
|
|
|
mnem += "t"
|
|
|
|
type = ("Store", "Load")[l]
|
|
|
|
suffix = "_%s_P%dU%dB%dW%d" % (suffix, p, u, b, w)
|
|
|
|
if b == 1:
|
|
|
|
mnem += "b"
|
|
|
|
return LoadStoreBase(mnem, mnem.capitalize() + suffix,
|
|
|
|
ea_code, code, mem_flags = [], inst_flags = [],
|
|
|
|
exec_template_base = type.capitalize())
|
|
|
|
|
2009-07-09 08:02:19 +02:00
|
|
|
def buildMode3Inst(p, u, i, w, type, code, mnem):
|
|
|
|
op = ("-", "+")[u]
|
|
|
|
offset = ("%s Rm", "%s hilo")[i] % op
|
|
|
|
ea_code = "EA = Rn %s;" % ("", offset)[p]
|
|
|
|
if p == 0 or w == 1:
|
|
|
|
code += "Rn = Rn %s;" % offset
|
|
|
|
suffix = "_P%dU%dI%dW%d" % (p, u, i, w)
|
|
|
|
return LoadStoreBase(mnem, mnem.capitalize() + suffix,
|
|
|
|
ea_code, code, mem_flags = [], inst_flags = [],
|
|
|
|
exec_template_base = type.capitalize())
|
|
|
|
}};
|
|
|
|
|
2009-07-09 08:02:19 +02:00
|
|
|
def format AddrMode2(suffix, offset) {{
|
|
|
|
header_output = decoder_output = exec_output = ""
|
|
|
|
decode_block = "switch(PUBWL) {\n"
|
|
|
|
|
|
|
|
# Loop over all the values of p, u, b, w and l and build instructions and
|
|
|
|
# a decode block for them.
|
|
|
|
for p in (0, 1):
|
|
|
|
for u in (0, 1):
|
|
|
|
for b in (0, 1):
|
|
|
|
for w in (0, 1):
|
|
|
|
for l in (0, 1):
|
|
|
|
(new_header_output,
|
|
|
|
new_decoder_output,
|
|
|
|
new_decode_block,
|
|
|
|
new_exec_output) = buildMode2Inst(p, u, b, w, l,
|
|
|
|
suffix, offset)
|
|
|
|
header_output += new_header_output
|
|
|
|
decoder_output += new_decoder_output
|
|
|
|
exec_output += new_exec_output
|
|
|
|
decode_block += '''
|
|
|
|
case %#x:
|
|
|
|
{%s}
|
|
|
|
break;
|
|
|
|
''' % (buildPUBWLCase(p,u,b,w,l), new_decode_block)
|
|
|
|
decode_block += '''
|
|
|
|
default:
|
|
|
|
return new Unknown(machInst);
|
|
|
|
break;
|
|
|
|
}'''
|
|
|
|
}};
|
|
|
|
|
2009-07-09 08:02:19 +02:00
|
|
|
def format AddrMode3(l0Type, l0Code, l1Type, l1Code) {{
|
|
|
|
l0Code = ArmGenericCodeSubs(l0Code);
|
|
|
|
l1Code = ArmGenericCodeSubs(l1Code);
|
|
|
|
|
|
|
|
header_output = decoder_output = exec_output = ""
|
|
|
|
decode_block = "switch(PUBWL) {\n"
|
|
|
|
(l0Mnem, l1Mnem) = name.split("_");
|
|
|
|
|
|
|
|
# Loop over all the values of p, u, i, w and l and build instructions and
|
|
|
|
# a decode block for them.
|
|
|
|
for (l, type, code, mnem) in ((0, l0Type, l0Code, l0Mnem),
|
|
|
|
(1, l1Type, l1Code, l1Mnem)):
|
|
|
|
for p in (0, 1):
|
|
|
|
wset = (0, 1)
|
|
|
|
if (p == 0):
|
|
|
|
wset = (0,)
|
|
|
|
for u in (0, 1):
|
|
|
|
for i in (0, 1):
|
|
|
|
for w in wset:
|
|
|
|
(new_header_output,
|
|
|
|
new_decoder_output,
|
|
|
|
new_decode_block,
|
|
|
|
new_exec_output) = buildMode3Inst(p, u, i, w,
|
|
|
|
type, code, mnem)
|
|
|
|
header_output += new_header_output
|
|
|
|
decoder_output += new_decoder_output
|
|
|
|
exec_output += new_exec_output
|
|
|
|
decode_block += '''
|
|
|
|
case %#x:
|
|
|
|
{%s}
|
|
|
|
break;
|
|
|
|
''' % (buildPUBWLCase(p,u,i,w,l), new_decode_block)
|
|
|
|
|
|
|
|
decode_block += '''
|
|
|
|
default:
|
|
|
|
return new Unknown(machInst);
|
|
|
|
break;
|
|
|
|
}'''
|
|
|
|
}};
|
|
|
|
|
2009-04-06 03:53:15 +02:00
|
|
|
def format ArmLoadMemory(memacc_code, ea_code = {{ EA = Rn + disp; }},
|
|
|
|
mem_flags = [], inst_flags = []) {{
|
|
|
|
ea_code = ArmGenericCodeSubs(ea_code)
|
|
|
|
memacc_code = ArmGenericCodeSubs(memacc_code)
|
|
|
|
(header_output, decoder_output, decode_block, exec_output) = \
|
|
|
|
LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
|
|
|
|
decode_template = BasicDecode,
|
|
|
|
exec_template_base = 'Load')
|
|
|
|
}};
|
|
|
|
|
|
|
|
def format ArmStoreMemory(memacc_code, ea_code = {{ EA = Rn + disp; }},
|
|
|
|
mem_flags = [], inst_flags = []) {{
|
|
|
|
ea_code = ArmGenericCodeSubs(ea_code)
|
|
|
|
memacc_code = ArmGenericCodeSubs(memacc_code)
|
|
|
|
(header_output, decoder_output, decode_block, exec_output) = \
|
|
|
|
LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
|
|
|
|
exec_template_base = 'Store')
|
|
|
|
}};
|
|
|
|
|