2014-12-23 15:31:17 +01:00
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/*
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* Copyright (c) 2012-2014 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Thomas Grass
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* Andreas Hansson
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* Marco Elver
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*/
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#ifndef __MEM_MEM_CHECKER_MONITOR_HH__
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#define __MEM_MEM_CHECKER_MONITOR_HH__
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#include "base/statistics.hh"
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#include "mem/mem_checker.hh"
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#include "mem/mem_object.hh"
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#include "params/MemCheckerMonitor.hh"
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#include "sim/system.hh"
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/**
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* Implements a MemChecker monitor, to be inserted between two ports.
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*/
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class MemCheckerMonitor : public MemObject
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{
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public:
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/** Parameters of memchecker monitor */
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typedef MemCheckerMonitorParams Params;
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const Params* params() const
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{ return reinterpret_cast<const Params*>(_params); }
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/**
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* Constructor based on the Python params
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*
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* @param params Python parameters
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*/
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MemCheckerMonitor(Params* params);
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/** Destructor */
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~MemCheckerMonitor();
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virtual BaseMasterPort& getMasterPort(const std::string& if_name,
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PortID idx = InvalidPortID);
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virtual BaseSlavePort& getSlavePort(const std::string& if_name,
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PortID idx = InvalidPortID);
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virtual void init();
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private:
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struct MemCheckerMonitorSenderState : public Packet::SenderState
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{
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MemCheckerMonitorSenderState(MemChecker::Serial _serial)
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: serial(_serial)
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{}
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MemChecker::Serial serial;
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};
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/**
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* This is the master port of the communication monitor. All recv
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* functions call a function in MemCheckerMonitor, where the
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* send function of the slave port is called. Besides this, these
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* functions can also perform actions for capturing statistics.
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*/
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class MonitorMasterPort : public MasterPort
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{
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public:
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MonitorMasterPort(const std::string& _name, MemCheckerMonitor& _mon)
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: MasterPort(_name, &_mon), mon(_mon)
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{ }
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protected:
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void recvFunctionalSnoop(PacketPtr pkt)
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{
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mon.recvFunctionalSnoop(pkt);
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}
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Tick recvAtomicSnoop(PacketPtr pkt)
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{
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return mon.recvAtomicSnoop(pkt);
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}
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bool recvTimingResp(PacketPtr pkt)
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{
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return mon.recvTimingResp(pkt);
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}
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void recvTimingSnoopReq(PacketPtr pkt)
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{
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mon.recvTimingSnoopReq(pkt);
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}
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void recvRangeChange()
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{
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mon.recvRangeChange();
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}
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bool isSnooping() const
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{
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return mon.isSnooping();
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}
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2015-03-02 10:00:35 +01:00
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void recvReqRetry()
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2014-12-23 15:31:17 +01:00
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{
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2015-03-02 10:00:35 +01:00
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mon.recvReqRetry();
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2014-12-23 15:31:17 +01:00
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}
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private:
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MemCheckerMonitor& mon;
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};
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/** Instance of master port, facing the memory side */
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MonitorMasterPort masterPort;
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/**
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* This is the slave port of the communication monitor. All recv
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* functions call a function in MemCheckerMonitor, where the
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* send function of the master port is called. Besides this, these
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* functions can also perform actions for capturing statistics.
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*/
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class MonitorSlavePort : public SlavePort
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{
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public:
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MonitorSlavePort(const std::string& _name, MemCheckerMonitor& _mon)
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: SlavePort(_name, &_mon), mon(_mon)
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{ }
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protected:
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void recvFunctional(PacketPtr pkt)
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{
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mon.recvFunctional(pkt);
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}
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Tick recvAtomic(PacketPtr pkt)
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{
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return mon.recvAtomic(pkt);
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}
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bool recvTimingReq(PacketPtr pkt)
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{
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return mon.recvTimingReq(pkt);
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}
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bool recvTimingSnoopResp(PacketPtr pkt)
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{
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return mon.recvTimingSnoopResp(pkt);
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}
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AddrRangeList getAddrRanges() const
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{
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return mon.getAddrRanges();
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}
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2015-03-02 10:00:35 +01:00
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void recvRespRetry()
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2014-12-23 15:31:17 +01:00
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{
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2015-03-02 10:00:35 +01:00
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mon.recvRespRetry();
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2014-12-23 15:31:17 +01:00
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}
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private:
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MemCheckerMonitor& mon;
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};
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/** Instance of slave port, i.e. on the CPU side */
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MonitorSlavePort slavePort;
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void recvFunctional(PacketPtr pkt);
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void recvFunctionalSnoop(PacketPtr pkt);
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Tick recvAtomic(PacketPtr pkt);
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Tick recvAtomicSnoop(PacketPtr pkt);
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bool recvTimingReq(PacketPtr pkt);
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bool recvTimingResp(PacketPtr pkt);
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void recvTimingSnoopReq(PacketPtr pkt);
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bool recvTimingSnoopResp(PacketPtr pkt);
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AddrRangeList getAddrRanges() const;
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bool isSnooping() const;
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2015-03-02 10:00:35 +01:00
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void recvReqRetry();
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2014-12-23 15:31:17 +01:00
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2015-03-02 10:00:35 +01:00
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void recvRespRetry();
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2014-12-23 15:31:17 +01:00
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void recvRangeChange();
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bool warnOnly;
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MemChecker *memchecker;
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};
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#endif //__MEM_MEM_CHECKER_MONITOR_HH__
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