2006-05-16 23:36:50 +02:00
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/*
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2014-12-05 10:47:35 +01:00
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* Copyright 2014 Google, Inc.
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2015-09-30 18:14:19 +02:00
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* Copyright (c) 2010-2013,2015 ARM Limited
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2010-11-08 20:58:22 +01:00
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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2006-05-16 23:36:50 +02:00
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* Copyright (c) 2002-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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2006-06-01 01:26:56 +02:00
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*
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* Authors: Steve Reinhardt
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2006-05-16 23:36:50 +02:00
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*/
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2006-10-08 19:53:24 +02:00
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#include "arch/locked_mem.hh"
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2011-03-02 08:18:47 +01:00
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#include "arch/mmapped_ipr.hh"
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2006-05-16 23:36:50 +02:00
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#include "arch/utility.hh"
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2007-02-12 19:06:30 +01:00
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#include "base/bigint.hh"
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2009-09-23 17:34:21 +02:00
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#include "config/the_isa.hh"
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2006-05-16 23:36:50 +02:00
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#include "cpu/simple/timing.hh"
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2011-04-15 19:44:06 +02:00
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#include "cpu/exetrace.hh"
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2011-04-15 19:44:32 +02:00
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#include "debug/Config.hh"
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2012-08-15 16:38:08 +02:00
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#include "debug/Drain.hh"
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2011-04-15 19:44:32 +02:00
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#include "debug/ExecFaulting.hh"
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#include "debug/SimpleCPU.hh"
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2006-10-20 08:38:45 +02:00
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#include "mem/packet.hh"
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#include "mem/packet_access.hh"
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2007-07-24 06:51:38 +02:00
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#include "params/TimingSimpleCPU.hh"
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2010-09-14 04:26:03 +02:00
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#include "sim/faults.hh"
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2011-11-01 12:01:13 +01:00
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#include "sim/full_system.hh"
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2006-07-13 02:22:07 +02:00
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#include "sim/system.hh"
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2006-05-16 23:36:50 +02:00
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2014-11-06 12:42:22 +01:00
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#include "debug/Mwait.hh"
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2006-05-16 23:36:50 +02:00
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using namespace std;
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using namespace TheISA;
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void
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TimingSimpleCPU::init()
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{
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2015-09-30 18:14:19 +02:00
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BaseSimpleCPU::init();
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2006-05-16 23:36:50 +02:00
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}
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void
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2012-01-17 19:55:08 +01:00
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TimingSimpleCPU::TimingCPUPort::TickEvent::schedule(PacketPtr _pkt, Tick t)
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2006-07-21 01:00:40 +02:00
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{
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pkt = _pkt;
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2008-10-09 13:58:24 +02:00
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cpu->schedule(this, t);
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2006-07-21 01:00:40 +02:00
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}
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2008-08-11 21:22:16 +02:00
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TimingSimpleCPU::TimingSimpleCPU(TimingSimpleCPUParams *p)
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2012-01-17 19:55:08 +01:00
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: BaseSimpleCPU(p), fetchTranslation(this), icachePort(this),
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2012-08-28 20:30:31 +02:00
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dcachePort(this), ifetch_pkt(NULL), dcache_pkt(NULL), previousCycle(0),
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2015-07-07 10:51:05 +02:00
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fetchEvent(this)
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2006-05-16 23:36:50 +02:00
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{
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_status = Idle;
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}
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2014-01-24 22:29:30 +01:00
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2006-05-16 23:36:50 +02:00
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TimingSimpleCPU::~TimingSimpleCPU()
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{
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}
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2015-07-07 10:51:05 +02:00
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DrainState
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TimingSimpleCPU::drain()
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2006-06-30 01:45:24 +02:00
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{
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2013-01-07 19:05:52 +01:00
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if (switchedOut())
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2015-07-07 10:51:05 +02:00
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return DrainState::Drained;
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2013-01-07 19:05:52 +01:00
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2012-11-02 17:32:01 +01:00
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if (_status == Idle ||
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2013-01-07 19:05:52 +01:00
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(_status == BaseSimpleCPU::Running && isDrained())) {
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2013-01-07 19:05:46 +01:00
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DPRINTF(Drain, "No need to drain.\n");
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2015-09-30 18:14:19 +02:00
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activeThreads.clear();
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2015-07-07 10:51:05 +02:00
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return DrainState::Drained;
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2006-06-30 01:45:24 +02:00
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} else {
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2015-09-30 18:14:19 +02:00
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DPRINTF(Drain, "Requesting drain.\n");
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2013-01-07 19:05:46 +01:00
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// The fetch event can become descheduled if a drain didn't
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// succeed on the first attempt. We need to reschedule it if
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// the CPU is waiting for a microcode routine to complete.
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2013-01-07 19:05:52 +01:00
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if (_status == BaseSimpleCPU::Running && !fetchEvent.scheduled())
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2013-04-22 19:20:31 +02:00
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schedule(fetchEvent, clockEdge());
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2013-01-07 19:05:46 +01:00
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2015-07-07 10:51:05 +02:00
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return DrainState::Draining;
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2006-06-30 01:45:24 +02:00
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}
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2006-05-16 23:36:50 +02:00
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}
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void
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2012-11-02 17:32:01 +01:00
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TimingSimpleCPU::drainResume()
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2006-05-16 23:36:50 +02:00
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{
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2013-01-07 19:05:46 +01:00
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assert(!fetchEvent.scheduled());
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2013-01-07 19:05:52 +01:00
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if (switchedOut())
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return;
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2013-01-07 19:05:46 +01:00
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2007-11-08 16:46:41 +01:00
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DPRINTF(SimpleCPU, "Resume\n");
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2013-02-15 23:40:08 +01:00
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verifyMemoryMode();
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2013-01-07 19:05:52 +01:00
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assert(!threadContexts.empty());
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2006-10-12 00:44:48 +02:00
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2015-09-30 18:14:19 +02:00
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_status = BaseSimpleCPU::Idle;
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for (ThreadID tid = 0; tid < numThreads; tid++) {
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if (threadInfo[tid]->thread->status() == ThreadContext::Active) {
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threadInfo[tid]->notIdleFraction = 1;
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activeThreads.push_back(tid);
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_status = BaseSimpleCPU::Running;
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// Fetch if any threads active
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if (!fetchEvent.scheduled()) {
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schedule(fetchEvent, nextCycle());
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}
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} else {
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threadInfo[tid]->notIdleFraction = 0;
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}
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2006-05-16 23:36:50 +02:00
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}
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2015-09-30 18:14:19 +02:00
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system->totalNumInsts = 0;
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2013-01-07 19:05:46 +01:00
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}
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bool
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TimingSimpleCPU::tryCompleteDrain()
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{
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2015-07-07 10:51:05 +02:00
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if (drainState() != DrainState::Draining)
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2013-01-07 19:05:46 +01:00
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return false;
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2015-09-30 18:14:19 +02:00
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DPRINTF(Drain, "tryCompleteDrain.\n");
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2013-01-07 19:05:46 +01:00
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if (!isDrained())
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return false;
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DPRINTF(Drain, "CPU done draining, processing drain event\n");
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2015-07-07 10:51:05 +02:00
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signalDrainDone();
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2006-06-30 01:45:24 +02:00
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2013-01-07 19:05:46 +01:00
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return true;
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2006-06-30 01:45:24 +02:00
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}
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void
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TimingSimpleCPU::switchOut()
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{
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2015-09-30 18:14:19 +02:00
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SimpleExecContext& t_info = *threadInfo[curThread];
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M5_VAR_USED SimpleThread* thread = t_info.thread;
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2013-01-07 19:05:44 +01:00
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BaseSimpleCPU::switchOut();
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2013-01-07 19:05:46 +01:00
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assert(!fetchEvent.scheduled());
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2012-11-02 17:32:01 +01:00
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assert(_status == BaseSimpleCPU::Running || _status == Idle);
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2015-09-30 18:14:19 +02:00
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assert(!t_info.stayAtPC);
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assert(thread->microPC() == 0);
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2013-01-07 19:05:46 +01:00
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2014-10-16 11:49:41 +02:00
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updateCycleCounts();
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2006-05-16 23:36:50 +02:00
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}
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void
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TimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
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{
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2013-01-07 19:05:44 +01:00
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BaseSimpleCPU::takeOverFrom(oldCPU);
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2006-05-16 23:36:50 +02:00
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2012-08-28 20:30:31 +02:00
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previousCycle = curCycle();
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2006-05-16 23:36:50 +02:00
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}
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2013-02-15 23:40:08 +01:00
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void
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TimingSimpleCPU::verifyMemoryMode() const
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{
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2013-02-15 23:40:09 +01:00
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if (!system->isTimingMode()) {
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2013-02-15 23:40:08 +01:00
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fatal("The timing CPU requires the memory system to be in "
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"'timing' mode.\n");
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}
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}
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2006-05-16 23:36:50 +02:00
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void
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alpha,arm,mips,power,x86,cpu,sim: Cleanup activate/deactivate
activate(), suspend(), and halt() used on thread contexts had an optional
delay parameter. However this parameter was often ignored. Also, when used,
the delay was seemily arbitrarily set to 0 or 1 cycle (no other delays were
ever specified). This patch removes the delay parameter and 'Events'
associated with them across all ISAs and cores. Unused activate logic
is also removed.
2014-09-20 23:18:35 +02:00
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TimingSimpleCPU::activateContext(ThreadID thread_num)
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2006-05-16 23:36:50 +02:00
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{
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alpha,arm,mips,power,x86,cpu,sim: Cleanup activate/deactivate
activate(), suspend(), and halt() used on thread contexts had an optional
delay parameter. However this parameter was often ignored. Also, when used,
the delay was seemily arbitrarily set to 0 or 1 cycle (no other delays were
ever specified). This patch removes the delay parameter and 'Events'
associated with them across all ISAs and cores. Unused activate logic
is also removed.
2014-09-20 23:18:35 +02:00
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DPRINTF(SimpleCPU, "ActivateContext %d\n", thread_num);
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2007-11-08 16:46:41 +01:00
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2015-09-30 18:14:19 +02:00
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assert(thread_num < numThreads);
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2006-05-16 23:36:50 +02:00
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2015-09-30 18:14:19 +02:00
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threadInfo[thread_num]->notIdleFraction = 1;
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if (_status == BaseSimpleCPU::Idle)
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_status = BaseSimpleCPU::Running;
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2006-11-29 22:07:55 +01:00
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2006-05-16 23:36:50 +02:00
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// kick things off by initiating the fetch of the next instruction
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2015-09-30 18:14:19 +02:00
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if (!fetchEvent.scheduled())
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schedule(fetchEvent, clockEdge(Cycles(0)));
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if (std::find(activeThreads.begin(), activeThreads.end(), thread_num)
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== activeThreads.end()) {
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activeThreads.push_back(thread_num);
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}
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2006-05-16 23:36:50 +02:00
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}
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void
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2012-01-31 18:05:52 +01:00
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TimingSimpleCPU::suspendContext(ThreadID thread_num)
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2006-05-16 23:36:50 +02:00
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{
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2007-11-08 16:46:41 +01:00
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DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num);
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2015-09-30 18:14:19 +02:00
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assert(thread_num < numThreads);
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activeThreads.remove(thread_num);
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2006-05-16 23:36:50 +02:00
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2009-04-19 11:23:29 +02:00
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if (_status == Idle)
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return;
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2012-11-02 17:32:01 +01:00
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assert(_status == BaseSimpleCPU::Running);
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2006-05-16 23:36:50 +02:00
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2015-09-30 18:14:19 +02:00
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threadInfo[thread_num]->notIdleFraction = 0;
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2006-05-26 20:33:43 +02:00
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2015-09-30 18:14:19 +02:00
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if (activeThreads.empty()) {
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_status = Idle;
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if (fetchEvent.scheduled()) {
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deschedule(fetchEvent);
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}
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}
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2006-05-16 23:36:50 +02:00
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}
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2008-11-10 06:56:28 +01:00
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bool
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TimingSimpleCPU::handleReadPacket(PacketPtr pkt)
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{
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2015-09-30 18:14:19 +02:00
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SimpleExecContext &t_info = *threadInfo[curThread];
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SimpleThread* thread = t_info.thread;
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2008-11-10 06:56:28 +01:00
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RequestPtr req = pkt->req;
|
2014-11-12 15:05:22 +01:00
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// We're about the issues a locked load, so tell the monitor
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// to start caring about this address
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if (pkt->isRead() && pkt->req->isLLSC()) {
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TheISA::handleLockedRead(thread, pkt->req);
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}
|
2011-03-02 08:18:47 +01:00
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if (req->isMmappedIpr()) {
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2012-08-28 20:30:33 +02:00
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Cycles delay = TheISA::handleIprRead(thread->getTC(), pkt);
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2012-08-28 20:30:31 +02:00
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new IprEvent(pkt, this, clockEdge(delay));
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2008-11-10 06:56:28 +01:00
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_status = DcacheWaitResponse;
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dcache_pkt = NULL;
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MEM: Separate requests and responses for timing accesses
This patch moves send/recvTiming and send/recvTimingSnoop from the
Port base class to the MasterPort and SlavePort, and also splits them
into separate member functions for requests and responses:
send/recvTimingReq, send/recvTimingResp, and send/recvTimingSnoopReq,
send/recvTimingSnoopResp. A master port sends requests and receives
responses, and also receives snoop requests and sends snoop
responses. A slave port has the reciprocal behaviour as it receives
requests and sends responses, and sends snoop requests and receives
snoop responses.
For all MemObjects that have only master ports or slave ports (but not
both), e.g. a CPU, or a PIO device, this patch merely adds more
clarity to what kind of access is taking place. For example, a CPU
port used to call sendTiming, and will now call
sendTimingReq. Similarly, a response previously came back through
recvTiming, which is now recvTimingResp. For the modules that have
both master and slave ports, e.g. the bus, the behaviour was
previously relying on branches based on pkt->isRequest(), and this is
now replaced with a direct call to the apprioriate member function
depending on the type of access. Please note that send/recvRetry is
still shared by all the timing accessors and remains in the Port base
class for now (to maintain the current bus functionality and avoid
changing the statistics of all regressions).
The packet queue is split into a MasterPort and SlavePort version to
facilitate the use of the new timing accessors. All uses of the
PacketQueue are updated accordingly.
With this patch, the type of packet (request or response) is now well
defined for each type of access, and asserts on pkt->isRequest() and
pkt->isResponse() are now moved to the appropriate send member
functions. It is also worth noting that sendTimingSnoopReq no longer
returns a boolean, as the semantics do not alow snoop requests to be
rejected or stalled. All these assumptions are now excplicitly part of
the port interface itself.
2012-05-01 19:40:42 +02:00
|
|
|
} else if (!dcachePort.sendTimingReq(pkt)) {
|
2008-11-10 06:56:28 +01:00
|
|
|
_status = DcacheRetry;
|
|
|
|
dcache_pkt = pkt;
|
|
|
|
} else {
|
|
|
|
_status = DcacheWaitResponse;
|
|
|
|
// memory system takes ownership of packet
|
|
|
|
dcache_pkt = NULL;
|
|
|
|
}
|
|
|
|
return dcache_pkt == NULL;
|
|
|
|
}
|
2006-05-16 23:36:50 +02:00
|
|
|
|
2009-02-25 19:16:15 +01:00
|
|
|
void
|
2010-02-12 20:53:19 +01:00
|
|
|
TimingSimpleCPU::sendData(RequestPtr req, uint8_t *data, uint64_t *res,
|
|
|
|
bool read)
|
2008-11-14 08:30:37 +01:00
|
|
|
{
|
2015-09-30 18:14:19 +02:00
|
|
|
SimpleExecContext &t_info = *threadInfo[curThread];
|
|
|
|
SimpleThread* thread = t_info.thread;
|
|
|
|
|
2015-01-22 11:00:53 +01:00
|
|
|
PacketPtr pkt = buildPacket(req, read);
|
2014-12-02 12:07:43 +01:00
|
|
|
pkt->dataDynamic<uint8_t>(data);
|
2009-02-25 19:16:15 +01:00
|
|
|
if (req->getFlags().isSet(Request::NO_ACCESS)) {
|
|
|
|
assert(!dcache_pkt);
|
|
|
|
pkt->makeResponse();
|
|
|
|
completeDataAccess(pkt);
|
|
|
|
} else if (read) {
|
|
|
|
handleReadPacket(pkt);
|
|
|
|
} else {
|
|
|
|
bool do_access = true; // flag to suppress cache access
|
2008-11-14 08:30:37 +01:00
|
|
|
|
2009-04-20 06:44:15 +02:00
|
|
|
if (req->isLLSC()) {
|
2014-01-24 22:29:30 +01:00
|
|
|
do_access = TheISA::handleLockedWrite(thread, req, dcachePort.cacheBlockMask);
|
2009-02-25 19:16:15 +01:00
|
|
|
} else if (req->isCondSwap()) {
|
|
|
|
assert(res);
|
|
|
|
req->setExtraData(*res);
|
|
|
|
}
|
2008-11-14 08:30:37 +01:00
|
|
|
|
2009-02-25 19:16:15 +01:00
|
|
|
if (do_access) {
|
|
|
|
dcache_pkt = pkt;
|
|
|
|
handleWritePacket();
|
2015-09-30 18:14:19 +02:00
|
|
|
threadSnoop(pkt, curThread);
|
2009-02-25 19:16:15 +01:00
|
|
|
} else {
|
|
|
|
_status = DcacheWaitResponse;
|
|
|
|
completeDataAccess(pkt);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
2010-02-12 20:53:19 +01:00
|
|
|
TimingSimpleCPU::sendSplitData(RequestPtr req1, RequestPtr req2,
|
|
|
|
RequestPtr req, uint8_t *data, bool read)
|
2009-02-25 19:16:15 +01:00
|
|
|
{
|
|
|
|
PacketPtr pkt1, pkt2;
|
|
|
|
buildSplitPacket(pkt1, pkt2, req1, req2, req, data, read);
|
|
|
|
if (req->getFlags().isSet(Request::NO_ACCESS)) {
|
|
|
|
assert(!dcache_pkt);
|
|
|
|
pkt1->makeResponse();
|
|
|
|
completeDataAccess(pkt1);
|
|
|
|
} else if (read) {
|
2011-02-07 07:14:18 +01:00
|
|
|
SplitFragmentSenderState * send_state =
|
|
|
|
dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState);
|
2009-02-25 19:16:15 +01:00
|
|
|
if (handleReadPacket(pkt1)) {
|
|
|
|
send_state->clearFromParent();
|
2011-02-07 07:14:18 +01:00
|
|
|
send_state = dynamic_cast<SplitFragmentSenderState *>(
|
|
|
|
pkt2->senderState);
|
2009-02-25 19:16:15 +01:00
|
|
|
if (handleReadPacket(pkt2)) {
|
|
|
|
send_state->clearFromParent();
|
|
|
|
}
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
dcache_pkt = pkt1;
|
2011-02-07 07:14:18 +01:00
|
|
|
SplitFragmentSenderState * send_state =
|
|
|
|
dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState);
|
2009-02-25 19:16:15 +01:00
|
|
|
if (handleWritePacket()) {
|
|
|
|
send_state->clearFromParent();
|
|
|
|
dcache_pkt = pkt2;
|
2011-02-07 07:14:18 +01:00
|
|
|
send_state = dynamic_cast<SplitFragmentSenderState *>(
|
|
|
|
pkt2->senderState);
|
2009-02-25 19:16:15 +01:00
|
|
|
if (handleWritePacket()) {
|
|
|
|
send_state->clearFromParent();
|
|
|
|
}
|
|
|
|
}
|
2009-02-25 19:15:34 +01:00
|
|
|
}
|
2009-02-25 19:16:15 +01:00
|
|
|
}
|
2008-11-14 08:30:37 +01:00
|
|
|
|
2009-02-25 19:16:15 +01:00
|
|
|
void
|
2014-09-19 16:35:18 +02:00
|
|
|
TimingSimpleCPU::translationFault(const Fault &fault)
|
2009-02-25 19:16:15 +01:00
|
|
|
{
|
2009-11-11 06:10:18 +01:00
|
|
|
// fault may be NoFault in cases where a fault is suppressed,
|
|
|
|
// for instance prefetches.
|
2014-10-16 11:49:41 +02:00
|
|
|
updateCycleCounts();
|
2008-11-14 08:30:37 +01:00
|
|
|
|
2009-02-25 19:16:15 +01:00
|
|
|
if (traceData) {
|
|
|
|
// Since there was a fault, we shouldn't trace this instruction.
|
|
|
|
delete traceData;
|
|
|
|
traceData = NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
postExecute();
|
|
|
|
|
2013-01-07 19:05:46 +01:00
|
|
|
advanceInst(fault);
|
2008-11-14 08:30:37 +01:00
|
|
|
}
|
|
|
|
|
2015-01-22 11:00:53 +01:00
|
|
|
PacketPtr
|
|
|
|
TimingSimpleCPU::buildPacket(RequestPtr req, bool read)
|
2008-11-14 08:30:37 +01:00
|
|
|
{
|
2015-01-22 11:00:53 +01:00
|
|
|
return read ? Packet::createRead(req) : Packet::createWrite(req);
|
2009-02-25 19:16:15 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
TimingSimpleCPU::buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2,
|
|
|
|
RequestPtr req1, RequestPtr req2, RequestPtr req,
|
|
|
|
uint8_t *data, bool read)
|
|
|
|
{
|
|
|
|
pkt1 = pkt2 = NULL;
|
|
|
|
|
2011-03-02 08:18:47 +01:00
|
|
|
assert(!req1->isMmappedIpr() && !req2->isMmappedIpr());
|
2009-02-25 19:16:15 +01:00
|
|
|
|
|
|
|
if (req->getFlags().isSet(Request::NO_ACCESS)) {
|
2015-01-22 11:00:53 +01:00
|
|
|
pkt1 = buildPacket(req, read);
|
2009-02-25 19:16:15 +01:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2015-01-22 11:00:53 +01:00
|
|
|
pkt1 = buildPacket(req1, read);
|
|
|
|
pkt2 = buildPacket(req2, read);
|
2009-02-25 19:16:15 +01:00
|
|
|
|
MEM: Remove the Broadcast destination from the packet
This patch simplifies the packet by removing the broadcast flag and
instead more firmly relying on (and enforcing) the semantics of
transactions in the classic memory system, i.e. request packets are
routed from a master to a slave based on the address, and when they
are created they have neither a valid source, nor destination. On
their way to the slave, the request packet is updated with a source
field for all modules that multiplex packets from multiple master
(e.g. a bus). When a request packet is turned into a response packet
(at the final slave), it moves the potentially populated source field
to the destination field, and the response packet is routed through
any multiplexing components back to the master based on the
destination field.
Modules that connect multiplexing components, such as caches and
bridges store any existing source and destination field in the sender
state as a stack (just as before).
The packet constructor is simplified in that there is no longer a need
to pass the Packet::Broadcast as the destination (this was always the
case for the classic memory system). In the case of Ruby, rather than
using the parameter to the constructor we now rely on setDest, as
there is already another three-argument constructor in the packet
class.
In many places where the packet information was printed as part of
DPRINTFs, request packets would be printed with a numeric "dest" that
would always be -1 (Broadcast) and that field is now removed from the
printing.
2012-04-14 11:45:55 +02:00
|
|
|
PacketPtr pkt = new Packet(req, pkt1->cmd.responseCommand());
|
2009-02-25 19:16:15 +01:00
|
|
|
|
2014-12-02 12:07:43 +01:00
|
|
|
pkt->dataDynamic<uint8_t>(data);
|
2009-02-25 19:16:15 +01:00
|
|
|
pkt1->dataStatic<uint8_t>(data);
|
|
|
|
pkt2->dataStatic<uint8_t>(data + req1->getSize());
|
|
|
|
|
|
|
|
SplitMainSenderState * main_send_state = new SplitMainSenderState;
|
|
|
|
pkt->senderState = main_send_state;
|
|
|
|
main_send_state->fragments[0] = pkt1;
|
|
|
|
main_send_state->fragments[1] = pkt2;
|
|
|
|
main_send_state->outstanding = 2;
|
|
|
|
pkt1->senderState = new SplitFragmentSenderState(pkt, 0);
|
|
|
|
pkt2->senderState = new SplitFragmentSenderState(pkt, 1);
|
2008-11-14 08:30:37 +01:00
|
|
|
}
|
|
|
|
|
2006-05-16 23:36:50 +02:00
|
|
|
Fault
|
2011-07-03 07:35:04 +02:00
|
|
|
TimingSimpleCPU::readMem(Addr addr, uint8_t *data,
|
|
|
|
unsigned size, unsigned flags)
|
cpu. arch: add initiateMemRead() to ExecContext interface
For historical reasons, the ExecContext interface had a single
function, readMem(), that did two different things depending on
whether the ExecContext supported atomic memory mode (i.e.,
AtomicSimpleCPU) or timing memory mode (all the other models).
In the former case, it actually performed a memory read; in the
latter case, it merely initiated a read access, and the read
completion did not happen until later when a response packet
arrived from the memory system.
This led to some confusing things, including timing accesses
being required to provide a pointer for the return data even
though that pointer was only used in atomic mode.
This patch splits this interface, adding a new initiateMemRead()
function to the ExecContext interface to replace the timing-mode
use of readMem().
For consistency and clarity, the readMemTiming() helper function
in the ISA definitions is renamed to initiateMemRead() as well.
For x86, where the access size is passed in explicitly, we can
also get rid of the data parameter at this level. For other ISAs,
where the access size is determined from the type of the data
parameter, we have to keep the parameter for that purpose.
2016-01-18 03:27:46 +01:00
|
|
|
{
|
|
|
|
panic("readMem() is for atomic accesses, and should "
|
|
|
|
"never be called on TimingSimpleCPU.\n");
|
|
|
|
}
|
|
|
|
|
|
|
|
Fault
|
|
|
|
TimingSimpleCPU::initiateMemRead(Addr addr, unsigned size, unsigned flags)
|
2006-05-16 23:36:50 +02:00
|
|
|
{
|
2015-09-30 18:14:19 +02:00
|
|
|
SimpleExecContext &t_info = *threadInfo[curThread];
|
|
|
|
SimpleThread* thread = t_info.thread;
|
|
|
|
|
2008-11-10 06:56:28 +01:00
|
|
|
Fault fault;
|
|
|
|
const int asid = 0;
|
2015-09-30 18:14:19 +02:00
|
|
|
const ThreadID tid = curThread;
|
ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.
This change is a low level and pervasive reorganization of how PCs are managed
in M5. Back when Alpha was the only ISA, there were only 2 PCs to worry about,
the PC and the NPC, and the lsb of the PC signaled whether or not you were in
PAL mode. As other ISAs were added, we had to add an NNPC, micro PC and next
micropc, x86 and ARM introduced variable length instruction sets, and ARM
started to keep track of mode bits in the PC. Each CPU model handled PCs in
its own custom way that needed to be updated individually to handle the new
dimensions of variability, or, in the case of ARMs mode-bit-in-the-pc hack,
the complexity could be hidden in the ISA at the ISA implementation's expense.
Areas like the branch predictor hadn't been updated to handle branch delay
slots or micropcs, and it turns out that had introduced a significant (10s of
percent) performance bug in SPARC and to a lesser extend MIPS. Rather than
perpetuate the problem by reworking O3 again to handle the PC features needed
by x86, this change was introduced to rework PC handling in a more modular,
transparent, and hopefully efficient way.
PC type:
Rather than having the superset of all possible elements of PC state declared
in each of the CPU models, each ISA defines its own PCState type which has
exactly the elements it needs. A cross product of canned PCState classes are
defined in the new "generic" ISA directory for ISAs with/without delay slots
and microcode. These are either typedef-ed or subclassed by each ISA. To read
or write this structure through a *Context, you use the new pcState() accessor
which reads or writes depending on whether it has an argument. If you just
want the address of the current or next instruction or the current micro PC,
you can get those through read-only accessors on either the PCState type or
the *Contexts. These are instAddr(), nextInstAddr(), and microPC(). Note the
move away from readPC. That name is ambiguous since it's not clear whether or
not it should be the actual address to fetch from, or if it should have extra
bits in it like the PAL mode bit. Each class is free to define its own
functions to get at whatever values it needs however it needs to to be used in
ISA specific code. Eventually Alpha's PAL mode bit could be moved out of the
PC and into a separate field like ARM.
These types can be reset to a particular pc (where npc = pc +
sizeof(MachInst), nnpc = npc + sizeof(MachInst), upc = 0, nupc = 1 as
appropriate), printed, serialized, and compared. There is a branching()
function which encapsulates code in the CPU models that checked if an
instruction branched or not. Exactly what that means in the context of branch
delay slots which can skip an instruction when not taken is ambiguous, and
ideally this function and its uses can be eliminated. PCStates also generally
know how to advance themselves in various ways depending on if they point at
an instruction, a microop, or the last microop of a macroop. More on that
later.
Ideally, accessing all the PCs at once when setting them will improve
performance of M5 even though more data needs to be moved around. This is
because often all the PCs need to be manipulated together, and by getting them
all at once you avoid multiple function calls. Also, the PCs of a particular
thread will have spatial locality in the cache. Previously they were grouped
by element in arrays which spread out accesses.
Advancing the PC:
The PCs were previously managed entirely by the CPU which had to know about PC
semantics, try to figure out which dimension to increment the PC in, what to
set NPC/NNPC, etc. These decisions are best left to the ISA in conjunction
with the PC type itself. Because most of the information about how to
increment the PC (mainly what type of instruction it refers to) is contained
in the instruction object, a new advancePC virtual function was added to the
StaticInst class. Subclasses provide an implementation that moves around the
right element of the PC with a minimal amount of decision making. In ISAs like
Alpha, the instructions always simply assign NPC to PC without having to worry
about micropcs, nnpcs, etc. The added cost of a virtual function call should
be outweighed by not having to figure out as much about what to do with the
PCs and mucking around with the extra elements.
One drawback of making the StaticInsts advance the PC is that you have to
actually have one to advance the PC. This would, superficially, seem to
require decoding an instruction before fetch could advance. This is, as far as
I can tell, realistic. fetch would advance through memory addresses, not PCs,
perhaps predicting new memory addresses using existing ones. More
sophisticated decisions about control flow would be made later on, after the
instruction was decoded, and handed back to fetch. If branching needs to
happen, some amount of decoding needs to happen to see that it's a branch,
what the target is, etc. This could get a little more complicated if that gets
done by the predecoder, but I'm choosing to ignore that for now.
Variable length instructions:
To handle variable length instructions in x86 and ARM, the predecoder now
takes in the current PC by reference to the getExtMachInst function. It can
modify the PC however it needs to (by setting NPC to be the PC + instruction
length, for instance). This could be improved since the CPU doesn't know if
the PC was modified and always has to write it back.
ISA parser:
To support the new API, all PC related operand types were removed from the
parser and replaced with a PCState type. There are two warts on this
implementation. First, as with all the other operand types, the PCState still
has to have a valid operand type even though it doesn't use it. Second, using
syntax like PCS.npc(target) doesn't work for two reasons, this looks like the
syntax for operand type overriding, and the parser can't figure out if you're
reading or writing. Instructions that use the PCS operand (which I've
consistently called it) need to first read it into a local variable,
manipulate it, and then write it back out.
Return address stack:
The return address stack needed a little extra help because, in the presence
of branch delay slots, it has to merge together elements of the return PC and
the call PC. To handle that, a buildRetPC utility function was added. There
are basically only two versions in all the ISAs, but it didn't seem short
enough to put into the generic ISA directory. Also, the branch predictor code
in O3 and InOrder were adjusted so that they always store the PC of the actual
call instruction in the RAS, not the next PC. If the call instruction is a
microop, the next PC refers to the next microop in the same macroop which is
probably not desirable. The buildRetPC function advances the PC intelligently
to the next macroop (in an ISA specific way) so that that case works.
Change in stats:
There were no change in stats except in MIPS and SPARC in the O3 model. MIPS
runs in about 9% fewer ticks. SPARC runs with 30%-50% fewer ticks, which could
likely be improved further by setting call/return instruction flags and taking
advantage of the RAS.
TODO:
Add != operators to the PCState classes, defined trivially to be !(a==b).
Smooth out places where PCs are split apart, passed around, and put back
together later. I think this might happen in SPARC's fault code. Add ISA
specific constructors that allow setting PC elements without calling a bunch
of accessors. Try to eliminate the need for the branching() function. Factor
out Alpha's PAL mode pc bit into a separate flag field, and eliminate places
where it's blindly masked out or tested in the PC.
2010-10-31 08:07:20 +01:00
|
|
|
const Addr pc = thread->instAddr();
|
2013-07-18 14:31:16 +02:00
|
|
|
unsigned block_size = cacheLineSize();
|
2010-02-12 20:53:19 +01:00
|
|
|
BaseTLB::Mode mode = BaseTLB::Read;
|
2008-11-10 06:56:28 +01:00
|
|
|
|
2015-01-25 13:22:44 +01:00
|
|
|
if (traceData)
|
|
|
|
traceData->setMem(addr, size, flags);
|
2010-03-23 16:50:57 +01:00
|
|
|
|
2010-08-13 15:16:02 +02:00
|
|
|
RequestPtr req = new Request(asid, addr, size,
|
2015-09-30 18:14:19 +02:00
|
|
|
flags, dataMasterId(), pc,
|
|
|
|
thread->contextId(), tid);
|
2008-11-14 08:30:37 +01:00
|
|
|
|
2014-01-24 22:29:30 +01:00
|
|
|
req->taskId(taskId());
|
|
|
|
|
2010-08-13 15:16:02 +02:00
|
|
|
Addr split_addr = roundDown(addr + size - 1, block_size);
|
2008-11-14 08:30:37 +01:00
|
|
|
assert(split_addr <= addr || split_addr - addr < block_size);
|
|
|
|
|
2009-02-25 19:16:15 +01:00
|
|
|
_status = DTBWaitResponse;
|
2008-11-14 08:30:37 +01:00
|
|
|
if (split_addr > addr) {
|
2009-02-25 19:16:15 +01:00
|
|
|
RequestPtr req1, req2;
|
2009-04-20 06:44:15 +02:00
|
|
|
assert(!req->isLLSC() && !req->isSwap());
|
2009-02-25 19:16:15 +01:00
|
|
|
req->splitOnVaddr(split_addr, req1, req2);
|
|
|
|
|
2010-02-12 20:53:19 +01:00
|
|
|
WholeTranslationState *state =
|
2010-08-13 15:16:02 +02:00
|
|
|
new WholeTranslationState(req, req1, req2, new uint8_t[size],
|
2010-02-12 20:53:19 +01:00
|
|
|
NULL, mode);
|
2011-08-07 18:21:48 +02:00
|
|
|
DataTranslation<TimingSimpleCPU *> *trans1 =
|
|
|
|
new DataTranslation<TimingSimpleCPU *>(this, state, 0);
|
|
|
|
DataTranslation<TimingSimpleCPU *> *trans2 =
|
|
|
|
new DataTranslation<TimingSimpleCPU *>(this, state, 1);
|
2010-02-12 20:53:19 +01:00
|
|
|
|
2015-09-30 18:14:19 +02:00
|
|
|
thread->dtb->translateTiming(req1, thread->getTC(), trans1, mode);
|
|
|
|
thread->dtb->translateTiming(req2, thread->getTC(), trans2, mode);
|
2008-11-10 06:56:28 +01:00
|
|
|
} else {
|
2010-02-12 20:53:19 +01:00
|
|
|
WholeTranslationState *state =
|
2010-08-13 15:16:02 +02:00
|
|
|
new WholeTranslationState(req, new uint8_t[size], NULL, mode);
|
2011-08-07 18:21:48 +02:00
|
|
|
DataTranslation<TimingSimpleCPU *> *translation
|
|
|
|
= new DataTranslation<TimingSimpleCPU *>(this, state);
|
2015-09-30 18:14:19 +02:00
|
|
|
thread->dtb->translateTiming(req, thread->getTC(), translation, mode);
|
2006-05-16 23:36:50 +02:00
|
|
|
}
|
|
|
|
|
2008-11-10 06:56:28 +01:00
|
|
|
return NoFault;
|
2006-05-16 23:36:50 +02:00
|
|
|
}
|
|
|
|
|
2008-11-10 06:56:28 +01:00
|
|
|
bool
|
|
|
|
TimingSimpleCPU::handleWritePacket()
|
|
|
|
{
|
2015-09-30 18:14:19 +02:00
|
|
|
SimpleExecContext &t_info = *threadInfo[curThread];
|
|
|
|
SimpleThread* thread = t_info.thread;
|
|
|
|
|
2008-11-10 06:56:28 +01:00
|
|
|
RequestPtr req = dcache_pkt->req;
|
2011-03-02 08:18:47 +01:00
|
|
|
if (req->isMmappedIpr()) {
|
2012-08-28 20:30:33 +02:00
|
|
|
Cycles delay = TheISA::handleIprWrite(thread->getTC(), dcache_pkt);
|
2012-08-28 20:30:31 +02:00
|
|
|
new IprEvent(dcache_pkt, this, clockEdge(delay));
|
2008-11-10 06:56:28 +01:00
|
|
|
_status = DcacheWaitResponse;
|
|
|
|
dcache_pkt = NULL;
|
MEM: Separate requests and responses for timing accesses
This patch moves send/recvTiming and send/recvTimingSnoop from the
Port base class to the MasterPort and SlavePort, and also splits them
into separate member functions for requests and responses:
send/recvTimingReq, send/recvTimingResp, and send/recvTimingSnoopReq,
send/recvTimingSnoopResp. A master port sends requests and receives
responses, and also receives snoop requests and sends snoop
responses. A slave port has the reciprocal behaviour as it receives
requests and sends responses, and sends snoop requests and receives
snoop responses.
For all MemObjects that have only master ports or slave ports (but not
both), e.g. a CPU, or a PIO device, this patch merely adds more
clarity to what kind of access is taking place. For example, a CPU
port used to call sendTiming, and will now call
sendTimingReq. Similarly, a response previously came back through
recvTiming, which is now recvTimingResp. For the modules that have
both master and slave ports, e.g. the bus, the behaviour was
previously relying on branches based on pkt->isRequest(), and this is
now replaced with a direct call to the apprioriate member function
depending on the type of access. Please note that send/recvRetry is
still shared by all the timing accessors and remains in the Port base
class for now (to maintain the current bus functionality and avoid
changing the statistics of all regressions).
The packet queue is split into a MasterPort and SlavePort version to
facilitate the use of the new timing accessors. All uses of the
PacketQueue are updated accordingly.
With this patch, the type of packet (request or response) is now well
defined for each type of access, and asserts on pkt->isRequest() and
pkt->isResponse() are now moved to the appropriate send member
functions. It is also worth noting that sendTimingSnoopReq no longer
returns a boolean, as the semantics do not alow snoop requests to be
rejected or stalled. All these assumptions are now excplicitly part of
the port interface itself.
2012-05-01 19:40:42 +02:00
|
|
|
} else if (!dcachePort.sendTimingReq(dcache_pkt)) {
|
2008-11-10 06:56:28 +01:00
|
|
|
_status = DcacheRetry;
|
|
|
|
} else {
|
|
|
|
_status = DcacheWaitResponse;
|
|
|
|
// memory system takes ownership of packet
|
|
|
|
dcache_pkt = NULL;
|
|
|
|
}
|
|
|
|
return dcache_pkt == NULL;
|
|
|
|
}
|
2006-05-16 23:36:50 +02:00
|
|
|
|
|
|
|
Fault
|
2011-07-03 07:35:04 +02:00
|
|
|
TimingSimpleCPU::writeMem(uint8_t *data, unsigned size,
|
|
|
|
Addr addr, unsigned flags, uint64_t *res)
|
2006-05-16 23:36:50 +02:00
|
|
|
{
|
2015-09-30 18:14:19 +02:00
|
|
|
SimpleExecContext &t_info = *threadInfo[curThread];
|
|
|
|
SimpleThread* thread = t_info.thread;
|
|
|
|
|
2011-07-03 07:34:58 +02:00
|
|
|
uint8_t *newData = new uint8_t[size];
|
2008-11-10 06:56:28 +01:00
|
|
|
const int asid = 0;
|
2015-09-30 18:14:19 +02:00
|
|
|
const ThreadID tid = curThread;
|
ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.
This change is a low level and pervasive reorganization of how PCs are managed
in M5. Back when Alpha was the only ISA, there were only 2 PCs to worry about,
the PC and the NPC, and the lsb of the PC signaled whether or not you were in
PAL mode. As other ISAs were added, we had to add an NNPC, micro PC and next
micropc, x86 and ARM introduced variable length instruction sets, and ARM
started to keep track of mode bits in the PC. Each CPU model handled PCs in
its own custom way that needed to be updated individually to handle the new
dimensions of variability, or, in the case of ARMs mode-bit-in-the-pc hack,
the complexity could be hidden in the ISA at the ISA implementation's expense.
Areas like the branch predictor hadn't been updated to handle branch delay
slots or micropcs, and it turns out that had introduced a significant (10s of
percent) performance bug in SPARC and to a lesser extend MIPS. Rather than
perpetuate the problem by reworking O3 again to handle the PC features needed
by x86, this change was introduced to rework PC handling in a more modular,
transparent, and hopefully efficient way.
PC type:
Rather than having the superset of all possible elements of PC state declared
in each of the CPU models, each ISA defines its own PCState type which has
exactly the elements it needs. A cross product of canned PCState classes are
defined in the new "generic" ISA directory for ISAs with/without delay slots
and microcode. These are either typedef-ed or subclassed by each ISA. To read
or write this structure through a *Context, you use the new pcState() accessor
which reads or writes depending on whether it has an argument. If you just
want the address of the current or next instruction or the current micro PC,
you can get those through read-only accessors on either the PCState type or
the *Contexts. These are instAddr(), nextInstAddr(), and microPC(). Note the
move away from readPC. That name is ambiguous since it's not clear whether or
not it should be the actual address to fetch from, or if it should have extra
bits in it like the PAL mode bit. Each class is free to define its own
functions to get at whatever values it needs however it needs to to be used in
ISA specific code. Eventually Alpha's PAL mode bit could be moved out of the
PC and into a separate field like ARM.
These types can be reset to a particular pc (where npc = pc +
sizeof(MachInst), nnpc = npc + sizeof(MachInst), upc = 0, nupc = 1 as
appropriate), printed, serialized, and compared. There is a branching()
function which encapsulates code in the CPU models that checked if an
instruction branched or not. Exactly what that means in the context of branch
delay slots which can skip an instruction when not taken is ambiguous, and
ideally this function and its uses can be eliminated. PCStates also generally
know how to advance themselves in various ways depending on if they point at
an instruction, a microop, or the last microop of a macroop. More on that
later.
Ideally, accessing all the PCs at once when setting them will improve
performance of M5 even though more data needs to be moved around. This is
because often all the PCs need to be manipulated together, and by getting them
all at once you avoid multiple function calls. Also, the PCs of a particular
thread will have spatial locality in the cache. Previously they were grouped
by element in arrays which spread out accesses.
Advancing the PC:
The PCs were previously managed entirely by the CPU which had to know about PC
semantics, try to figure out which dimension to increment the PC in, what to
set NPC/NNPC, etc. These decisions are best left to the ISA in conjunction
with the PC type itself. Because most of the information about how to
increment the PC (mainly what type of instruction it refers to) is contained
in the instruction object, a new advancePC virtual function was added to the
StaticInst class. Subclasses provide an implementation that moves around the
right element of the PC with a minimal amount of decision making. In ISAs like
Alpha, the instructions always simply assign NPC to PC without having to worry
about micropcs, nnpcs, etc. The added cost of a virtual function call should
be outweighed by not having to figure out as much about what to do with the
PCs and mucking around with the extra elements.
One drawback of making the StaticInsts advance the PC is that you have to
actually have one to advance the PC. This would, superficially, seem to
require decoding an instruction before fetch could advance. This is, as far as
I can tell, realistic. fetch would advance through memory addresses, not PCs,
perhaps predicting new memory addresses using existing ones. More
sophisticated decisions about control flow would be made later on, after the
instruction was decoded, and handed back to fetch. If branching needs to
happen, some amount of decoding needs to happen to see that it's a branch,
what the target is, etc. This could get a little more complicated if that gets
done by the predecoder, but I'm choosing to ignore that for now.
Variable length instructions:
To handle variable length instructions in x86 and ARM, the predecoder now
takes in the current PC by reference to the getExtMachInst function. It can
modify the PC however it needs to (by setting NPC to be the PC + instruction
length, for instance). This could be improved since the CPU doesn't know if
the PC was modified and always has to write it back.
ISA parser:
To support the new API, all PC related operand types were removed from the
parser and replaced with a PCState type. There are two warts on this
implementation. First, as with all the other operand types, the PCState still
has to have a valid operand type even though it doesn't use it. Second, using
syntax like PCS.npc(target) doesn't work for two reasons, this looks like the
syntax for operand type overriding, and the parser can't figure out if you're
reading or writing. Instructions that use the PCS operand (which I've
consistently called it) need to first read it into a local variable,
manipulate it, and then write it back out.
Return address stack:
The return address stack needed a little extra help because, in the presence
of branch delay slots, it has to merge together elements of the return PC and
the call PC. To handle that, a buildRetPC utility function was added. There
are basically only two versions in all the ISAs, but it didn't seem short
enough to put into the generic ISA directory. Also, the branch predictor code
in O3 and InOrder were adjusted so that they always store the PC of the actual
call instruction in the RAS, not the next PC. If the call instruction is a
microop, the next PC refers to the next microop in the same macroop which is
probably not desirable. The buildRetPC function advances the PC intelligently
to the next macroop (in an ISA specific way) so that that case works.
Change in stats:
There were no change in stats except in MIPS and SPARC in the O3 model. MIPS
runs in about 9% fewer ticks. SPARC runs with 30%-50% fewer ticks, which could
likely be improved further by setting call/return instruction flags and taking
advantage of the RAS.
TODO:
Add != operators to the PCState classes, defined trivially to be !(a==b).
Smooth out places where PCs are split apart, passed around, and put back
together later. I think this might happen in SPARC's fault code. Add ISA
specific constructors that allow setting PC elements without calling a bunch
of accessors. Try to eliminate the need for the branching() function. Factor
out Alpha's PAL mode pc bit into a separate flag field, and eliminate places
where it's blindly masked out or tested in the PC.
2010-10-31 08:07:20 +01:00
|
|
|
const Addr pc = thread->instAddr();
|
2013-07-18 14:31:16 +02:00
|
|
|
unsigned block_size = cacheLineSize();
|
2010-02-12 20:53:19 +01:00
|
|
|
BaseTLB::Mode mode = BaseTLB::Write;
|
2008-11-10 06:56:28 +01:00
|
|
|
|
2014-01-24 22:29:30 +01:00
|
|
|
if (data == NULL) {
|
|
|
|
assert(flags & Request::CACHE_BLOCK_ZERO);
|
|
|
|
// This must be a cache block cleaning request
|
|
|
|
memset(newData, 0, size);
|
|
|
|
} else {
|
|
|
|
memcpy(newData, data, size);
|
|
|
|
}
|
|
|
|
|
2015-01-25 13:22:44 +01:00
|
|
|
if (traceData)
|
|
|
|
traceData->setMem(addr, size, flags);
|
2010-03-23 16:50:57 +01:00
|
|
|
|
2010-08-13 15:16:02 +02:00
|
|
|
RequestPtr req = new Request(asid, addr, size,
|
2015-09-30 18:14:19 +02:00
|
|
|
flags, dataMasterId(), pc,
|
|
|
|
thread->contextId(), tid);
|
2008-11-10 06:56:28 +01:00
|
|
|
|
2014-01-24 22:29:30 +01:00
|
|
|
req->taskId(taskId());
|
|
|
|
|
2010-08-13 15:16:02 +02:00
|
|
|
Addr split_addr = roundDown(addr + size - 1, block_size);
|
2008-11-14 08:30:37 +01:00
|
|
|
assert(split_addr <= addr || split_addr - addr < block_size);
|
2008-11-10 06:56:28 +01:00
|
|
|
|
2009-02-25 19:16:15 +01:00
|
|
|
_status = DTBWaitResponse;
|
2008-11-14 08:30:37 +01:00
|
|
|
if (split_addr > addr) {
|
2009-02-25 19:16:15 +01:00
|
|
|
RequestPtr req1, req2;
|
2009-04-20 06:44:15 +02:00
|
|
|
assert(!req->isLLSC() && !req->isSwap());
|
2009-02-25 19:16:15 +01:00
|
|
|
req->splitOnVaddr(split_addr, req1, req2);
|
|
|
|
|
2010-02-12 20:53:19 +01:00
|
|
|
WholeTranslationState *state =
|
2011-07-03 07:34:58 +02:00
|
|
|
new WholeTranslationState(req, req1, req2, newData, res, mode);
|
2011-08-07 18:21:48 +02:00
|
|
|
DataTranslation<TimingSimpleCPU *> *trans1 =
|
|
|
|
new DataTranslation<TimingSimpleCPU *>(this, state, 0);
|
|
|
|
DataTranslation<TimingSimpleCPU *> *trans2 =
|
|
|
|
new DataTranslation<TimingSimpleCPU *>(this, state, 1);
|
2010-02-12 20:53:19 +01:00
|
|
|
|
2015-09-30 18:14:19 +02:00
|
|
|
thread->dtb->translateTiming(req1, thread->getTC(), trans1, mode);
|
|
|
|
thread->dtb->translateTiming(req2, thread->getTC(), trans2, mode);
|
2008-11-10 06:56:28 +01:00
|
|
|
} else {
|
2010-02-12 20:53:19 +01:00
|
|
|
WholeTranslationState *state =
|
2011-07-03 07:34:58 +02:00
|
|
|
new WholeTranslationState(req, newData, res, mode);
|
2011-08-07 18:21:48 +02:00
|
|
|
DataTranslation<TimingSimpleCPU *> *translation =
|
|
|
|
new DataTranslation<TimingSimpleCPU *>(this, state);
|
2015-09-30 18:14:19 +02:00
|
|
|
thread->dtb->translateTiming(req, thread->getTC(), translation, mode);
|
2006-05-16 23:36:50 +02:00
|
|
|
}
|
|
|
|
|
2010-03-23 16:50:57 +01:00
|
|
|
// Translation faults will be returned via finishTranslation()
|
2008-11-10 06:56:28 +01:00
|
|
|
return NoFault;
|
2006-05-16 23:36:50 +02:00
|
|
|
}
|
|
|
|
|
2015-09-30 18:14:19 +02:00
|
|
|
void
|
|
|
|
TimingSimpleCPU::threadSnoop(PacketPtr pkt, ThreadID sender)
|
|
|
|
{
|
|
|
|
for (ThreadID tid = 0; tid < numThreads; tid++) {
|
|
|
|
if (tid != sender) {
|
2016-02-07 02:21:19 +01:00
|
|
|
if (getCpuAddrMonitor(tid)->doMonitor(pkt)) {
|
2015-09-30 18:14:19 +02:00
|
|
|
wakeup(tid);
|
2015-09-30 18:14:19 +02:00
|
|
|
}
|
|
|
|
TheISA::handleLockedSnoop(threadInfo[tid]->thread, pkt,
|
|
|
|
dcachePort.cacheBlockMask);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
2006-05-16 23:36:50 +02:00
|
|
|
|
2010-02-12 20:53:19 +01:00
|
|
|
void
|
|
|
|
TimingSimpleCPU::finishTranslation(WholeTranslationState *state)
|
|
|
|
{
|
2012-11-02 17:32:01 +01:00
|
|
|
_status = BaseSimpleCPU::Running;
|
2010-02-12 20:53:19 +01:00
|
|
|
|
|
|
|
if (state->getFault() != NoFault) {
|
|
|
|
if (state->isPrefetch()) {
|
|
|
|
state->setNoFault();
|
|
|
|
}
|
2010-09-30 16:35:19 +02:00
|
|
|
delete [] state->data;
|
2010-02-12 20:53:19 +01:00
|
|
|
state->deleteReqs();
|
|
|
|
translationFault(state->getFault());
|
|
|
|
} else {
|
|
|
|
if (!state->isSplit) {
|
|
|
|
sendData(state->mainReq, state->data, state->res,
|
|
|
|
state->mode == BaseTLB::Read);
|
|
|
|
} else {
|
|
|
|
sendSplitData(state->sreqLow, state->sreqHigh, state->mainReq,
|
|
|
|
state->data, state->mode == BaseTLB::Read);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
delete state;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2006-05-16 23:36:50 +02:00
|
|
|
void
|
|
|
|
TimingSimpleCPU::fetch()
|
|
|
|
{
|
2015-09-30 18:14:19 +02:00
|
|
|
// Change thread if multi-threaded
|
|
|
|
swapActiveThread();
|
|
|
|
|
|
|
|
SimpleExecContext &t_info = *threadInfo[curThread];
|
|
|
|
SimpleThread* thread = t_info.thread;
|
|
|
|
|
2007-11-08 16:46:41 +01:00
|
|
|
DPRINTF(SimpleCPU, "Fetch\n");
|
|
|
|
|
2014-12-05 10:47:35 +01:00
|
|
|
if (!curStaticInst || !curStaticInst->isDelayedCommit()) {
|
2006-10-23 08:39:02 +02:00
|
|
|
checkForInterrupts();
|
2014-12-05 10:47:35 +01:00
|
|
|
checkPcEventQueue();
|
|
|
|
}
|
2008-02-14 22:14:35 +01:00
|
|
|
|
2011-03-18 01:20:20 +01:00
|
|
|
// We must have just got suspended by a PC event
|
|
|
|
if (_status == Idle)
|
|
|
|
return;
|
|
|
|
|
ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.
This change is a low level and pervasive reorganization of how PCs are managed
in M5. Back when Alpha was the only ISA, there were only 2 PCs to worry about,
the PC and the NPC, and the lsb of the PC signaled whether or not you were in
PAL mode. As other ISAs were added, we had to add an NNPC, micro PC and next
micropc, x86 and ARM introduced variable length instruction sets, and ARM
started to keep track of mode bits in the PC. Each CPU model handled PCs in
its own custom way that needed to be updated individually to handle the new
dimensions of variability, or, in the case of ARMs mode-bit-in-the-pc hack,
the complexity could be hidden in the ISA at the ISA implementation's expense.
Areas like the branch predictor hadn't been updated to handle branch delay
slots or micropcs, and it turns out that had introduced a significant (10s of
percent) performance bug in SPARC and to a lesser extend MIPS. Rather than
perpetuate the problem by reworking O3 again to handle the PC features needed
by x86, this change was introduced to rework PC handling in a more modular,
transparent, and hopefully efficient way.
PC type:
Rather than having the superset of all possible elements of PC state declared
in each of the CPU models, each ISA defines its own PCState type which has
exactly the elements it needs. A cross product of canned PCState classes are
defined in the new "generic" ISA directory for ISAs with/without delay slots
and microcode. These are either typedef-ed or subclassed by each ISA. To read
or write this structure through a *Context, you use the new pcState() accessor
which reads or writes depending on whether it has an argument. If you just
want the address of the current or next instruction or the current micro PC,
you can get those through read-only accessors on either the PCState type or
the *Contexts. These are instAddr(), nextInstAddr(), and microPC(). Note the
move away from readPC. That name is ambiguous since it's not clear whether or
not it should be the actual address to fetch from, or if it should have extra
bits in it like the PAL mode bit. Each class is free to define its own
functions to get at whatever values it needs however it needs to to be used in
ISA specific code. Eventually Alpha's PAL mode bit could be moved out of the
PC and into a separate field like ARM.
These types can be reset to a particular pc (where npc = pc +
sizeof(MachInst), nnpc = npc + sizeof(MachInst), upc = 0, nupc = 1 as
appropriate), printed, serialized, and compared. There is a branching()
function which encapsulates code in the CPU models that checked if an
instruction branched or not. Exactly what that means in the context of branch
delay slots which can skip an instruction when not taken is ambiguous, and
ideally this function and its uses can be eliminated. PCStates also generally
know how to advance themselves in various ways depending on if they point at
an instruction, a microop, or the last microop of a macroop. More on that
later.
Ideally, accessing all the PCs at once when setting them will improve
performance of M5 even though more data needs to be moved around. This is
because often all the PCs need to be manipulated together, and by getting them
all at once you avoid multiple function calls. Also, the PCs of a particular
thread will have spatial locality in the cache. Previously they were grouped
by element in arrays which spread out accesses.
Advancing the PC:
The PCs were previously managed entirely by the CPU which had to know about PC
semantics, try to figure out which dimension to increment the PC in, what to
set NPC/NNPC, etc. These decisions are best left to the ISA in conjunction
with the PC type itself. Because most of the information about how to
increment the PC (mainly what type of instruction it refers to) is contained
in the instruction object, a new advancePC virtual function was added to the
StaticInst class. Subclasses provide an implementation that moves around the
right element of the PC with a minimal amount of decision making. In ISAs like
Alpha, the instructions always simply assign NPC to PC without having to worry
about micropcs, nnpcs, etc. The added cost of a virtual function call should
be outweighed by not having to figure out as much about what to do with the
PCs and mucking around with the extra elements.
One drawback of making the StaticInsts advance the PC is that you have to
actually have one to advance the PC. This would, superficially, seem to
require decoding an instruction before fetch could advance. This is, as far as
I can tell, realistic. fetch would advance through memory addresses, not PCs,
perhaps predicting new memory addresses using existing ones. More
sophisticated decisions about control flow would be made later on, after the
instruction was decoded, and handed back to fetch. If branching needs to
happen, some amount of decoding needs to happen to see that it's a branch,
what the target is, etc. This could get a little more complicated if that gets
done by the predecoder, but I'm choosing to ignore that for now.
Variable length instructions:
To handle variable length instructions in x86 and ARM, the predecoder now
takes in the current PC by reference to the getExtMachInst function. It can
modify the PC however it needs to (by setting NPC to be the PC + instruction
length, for instance). This could be improved since the CPU doesn't know if
the PC was modified and always has to write it back.
ISA parser:
To support the new API, all PC related operand types were removed from the
parser and replaced with a PCState type. There are two warts on this
implementation. First, as with all the other operand types, the PCState still
has to have a valid operand type even though it doesn't use it. Second, using
syntax like PCS.npc(target) doesn't work for two reasons, this looks like the
syntax for operand type overriding, and the parser can't figure out if you're
reading or writing. Instructions that use the PCS operand (which I've
consistently called it) need to first read it into a local variable,
manipulate it, and then write it back out.
Return address stack:
The return address stack needed a little extra help because, in the presence
of branch delay slots, it has to merge together elements of the return PC and
the call PC. To handle that, a buildRetPC utility function was added. There
are basically only two versions in all the ISAs, but it didn't seem short
enough to put into the generic ISA directory. Also, the branch predictor code
in O3 and InOrder were adjusted so that they always store the PC of the actual
call instruction in the RAS, not the next PC. If the call instruction is a
microop, the next PC refers to the next microop in the same macroop which is
probably not desirable. The buildRetPC function advances the PC intelligently
to the next macroop (in an ISA specific way) so that that case works.
Change in stats:
There were no change in stats except in MIPS and SPARC in the O3 model. MIPS
runs in about 9% fewer ticks. SPARC runs with 30%-50% fewer ticks, which could
likely be improved further by setting call/return instruction flags and taking
advantage of the RAS.
TODO:
Add != operators to the PCState classes, defined trivially to be !(a==b).
Smooth out places where PCs are split apart, passed around, and put back
together later. I think this might happen in SPARC's fault code. Add ISA
specific constructors that allow setting PC elements without calling a bunch
of accessors. Try to eliminate the need for the branching() function. Factor
out Alpha's PAL mode pc bit into a separate flag field, and eliminate places
where it's blindly masked out or tested in the PC.
2010-10-31 08:07:20 +01:00
|
|
|
TheISA::PCState pcState = thread->pcState();
|
2015-09-30 18:14:19 +02:00
|
|
|
bool needToFetch = !isRomMicroPC(pcState.microPC()) &&
|
|
|
|
!curMacroStaticInst;
|
2006-05-16 23:36:50 +02:00
|
|
|
|
ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.
This change is a low level and pervasive reorganization of how PCs are managed
in M5. Back when Alpha was the only ISA, there were only 2 PCs to worry about,
the PC and the NPC, and the lsb of the PC signaled whether or not you were in
PAL mode. As other ISAs were added, we had to add an NNPC, micro PC and next
micropc, x86 and ARM introduced variable length instruction sets, and ARM
started to keep track of mode bits in the PC. Each CPU model handled PCs in
its own custom way that needed to be updated individually to handle the new
dimensions of variability, or, in the case of ARMs mode-bit-in-the-pc hack,
the complexity could be hidden in the ISA at the ISA implementation's expense.
Areas like the branch predictor hadn't been updated to handle branch delay
slots or micropcs, and it turns out that had introduced a significant (10s of
percent) performance bug in SPARC and to a lesser extend MIPS. Rather than
perpetuate the problem by reworking O3 again to handle the PC features needed
by x86, this change was introduced to rework PC handling in a more modular,
transparent, and hopefully efficient way.
PC type:
Rather than having the superset of all possible elements of PC state declared
in each of the CPU models, each ISA defines its own PCState type which has
exactly the elements it needs. A cross product of canned PCState classes are
defined in the new "generic" ISA directory for ISAs with/without delay slots
and microcode. These are either typedef-ed or subclassed by each ISA. To read
or write this structure through a *Context, you use the new pcState() accessor
which reads or writes depending on whether it has an argument. If you just
want the address of the current or next instruction or the current micro PC,
you can get those through read-only accessors on either the PCState type or
the *Contexts. These are instAddr(), nextInstAddr(), and microPC(). Note the
move away from readPC. That name is ambiguous since it's not clear whether or
not it should be the actual address to fetch from, or if it should have extra
bits in it like the PAL mode bit. Each class is free to define its own
functions to get at whatever values it needs however it needs to to be used in
ISA specific code. Eventually Alpha's PAL mode bit could be moved out of the
PC and into a separate field like ARM.
These types can be reset to a particular pc (where npc = pc +
sizeof(MachInst), nnpc = npc + sizeof(MachInst), upc = 0, nupc = 1 as
appropriate), printed, serialized, and compared. There is a branching()
function which encapsulates code in the CPU models that checked if an
instruction branched or not. Exactly what that means in the context of branch
delay slots which can skip an instruction when not taken is ambiguous, and
ideally this function and its uses can be eliminated. PCStates also generally
know how to advance themselves in various ways depending on if they point at
an instruction, a microop, or the last microop of a macroop. More on that
later.
Ideally, accessing all the PCs at once when setting them will improve
performance of M5 even though more data needs to be moved around. This is
because often all the PCs need to be manipulated together, and by getting them
all at once you avoid multiple function calls. Also, the PCs of a particular
thread will have spatial locality in the cache. Previously they were grouped
by element in arrays which spread out accesses.
Advancing the PC:
The PCs were previously managed entirely by the CPU which had to know about PC
semantics, try to figure out which dimension to increment the PC in, what to
set NPC/NNPC, etc. These decisions are best left to the ISA in conjunction
with the PC type itself. Because most of the information about how to
increment the PC (mainly what type of instruction it refers to) is contained
in the instruction object, a new advancePC virtual function was added to the
StaticInst class. Subclasses provide an implementation that moves around the
right element of the PC with a minimal amount of decision making. In ISAs like
Alpha, the instructions always simply assign NPC to PC without having to worry
about micropcs, nnpcs, etc. The added cost of a virtual function call should
be outweighed by not having to figure out as much about what to do with the
PCs and mucking around with the extra elements.
One drawback of making the StaticInsts advance the PC is that you have to
actually have one to advance the PC. This would, superficially, seem to
require decoding an instruction before fetch could advance. This is, as far as
I can tell, realistic. fetch would advance through memory addresses, not PCs,
perhaps predicting new memory addresses using existing ones. More
sophisticated decisions about control flow would be made later on, after the
instruction was decoded, and handed back to fetch. If branching needs to
happen, some amount of decoding needs to happen to see that it's a branch,
what the target is, etc. This could get a little more complicated if that gets
done by the predecoder, but I'm choosing to ignore that for now.
Variable length instructions:
To handle variable length instructions in x86 and ARM, the predecoder now
takes in the current PC by reference to the getExtMachInst function. It can
modify the PC however it needs to (by setting NPC to be the PC + instruction
length, for instance). This could be improved since the CPU doesn't know if
the PC was modified and always has to write it back.
ISA parser:
To support the new API, all PC related operand types were removed from the
parser and replaced with a PCState type. There are two warts on this
implementation. First, as with all the other operand types, the PCState still
has to have a valid operand type even though it doesn't use it. Second, using
syntax like PCS.npc(target) doesn't work for two reasons, this looks like the
syntax for operand type overriding, and the parser can't figure out if you're
reading or writing. Instructions that use the PCS operand (which I've
consistently called it) need to first read it into a local variable,
manipulate it, and then write it back out.
Return address stack:
The return address stack needed a little extra help because, in the presence
of branch delay slots, it has to merge together elements of the return PC and
the call PC. To handle that, a buildRetPC utility function was added. There
are basically only two versions in all the ISAs, but it didn't seem short
enough to put into the generic ISA directory. Also, the branch predictor code
in O3 and InOrder were adjusted so that they always store the PC of the actual
call instruction in the RAS, not the next PC. If the call instruction is a
microop, the next PC refers to the next microop in the same macroop which is
probably not desirable. The buildRetPC function advances the PC intelligently
to the next macroop (in an ISA specific way) so that that case works.
Change in stats:
There were no change in stats except in MIPS and SPARC in the O3 model. MIPS
runs in about 9% fewer ticks. SPARC runs with 30%-50% fewer ticks, which could
likely be improved further by setting call/return instruction flags and taking
advantage of the RAS.
TODO:
Add != operators to the PCState classes, defined trivially to be !(a==b).
Smooth out places where PCs are split apart, passed around, and put back
together later. I think this might happen in SPARC's fault code. Add ISA
specific constructors that allow setting PC elements without calling a bunch
of accessors. Try to eliminate the need for the branching() function. Factor
out Alpha's PAL mode pc bit into a separate flag field, and eliminate places
where it's blindly masked out or tested in the PC.
2010-10-31 08:07:20 +01:00
|
|
|
if (needToFetch) {
|
2012-11-02 17:32:01 +01:00
|
|
|
_status = BaseSimpleCPU::Running;
|
2008-10-13 04:32:06 +02:00
|
|
|
Request *ifetch_req = new Request();
|
2014-01-24 22:29:30 +01:00
|
|
|
ifetch_req->taskId(taskId());
|
2015-09-30 18:14:19 +02:00
|
|
|
ifetch_req->setThreadContext(thread->contextId(), curThread);
|
2009-02-25 19:16:15 +01:00
|
|
|
setupFetchRequest(ifetch_req);
|
2011-05-05 03:38:27 +02:00
|
|
|
DPRINTF(SimpleCPU, "Translating address %#x\n", ifetch_req->getVaddr());
|
2015-09-30 18:14:19 +02:00
|
|
|
thread->itb->translateTiming(ifetch_req, thread->getTC(),
|
|
|
|
&fetchTranslation, BaseTLB::Execute);
|
2009-02-25 19:16:15 +01:00
|
|
|
} else {
|
|
|
|
_status = IcacheWaitResponse;
|
|
|
|
completeIfetch(NULL);
|
|
|
|
|
2014-10-16 11:49:41 +02:00
|
|
|
updateCycleCounts();
|
2009-02-25 19:16:15 +01:00
|
|
|
}
|
|
|
|
}
|
2006-05-16 23:36:50 +02:00
|
|
|
|
2009-02-25 19:16:15 +01:00
|
|
|
|
|
|
|
void
|
2014-09-19 16:35:18 +02:00
|
|
|
TimingSimpleCPU::sendFetch(const Fault &fault, RequestPtr req,
|
|
|
|
ThreadContext *tc)
|
2009-02-25 19:16:15 +01:00
|
|
|
{
|
|
|
|
if (fault == NoFault) {
|
2011-05-05 03:38:27 +02:00
|
|
|
DPRINTF(SimpleCPU, "Sending fetch for addr %#x(pa: %#x)\n",
|
|
|
|
req->getVaddr(), req->getPaddr());
|
MEM: Remove the Broadcast destination from the packet
This patch simplifies the packet by removing the broadcast flag and
instead more firmly relying on (and enforcing) the semantics of
transactions in the classic memory system, i.e. request packets are
routed from a master to a slave based on the address, and when they
are created they have neither a valid source, nor destination. On
their way to the slave, the request packet is updated with a source
field for all modules that multiplex packets from multiple master
(e.g. a bus). When a request packet is turned into a response packet
(at the final slave), it moves the potentially populated source field
to the destination field, and the response packet is routed through
any multiplexing components back to the master based on the
destination field.
Modules that connect multiplexing components, such as caches and
bridges store any existing source and destination field in the sender
state as a stack (just as before).
The packet constructor is simplified in that there is no longer a need
to pass the Packet::Broadcast as the destination (this was always the
case for the classic memory system). In the case of Ruby, rather than
using the parameter to the constructor we now rely on setDest, as
there is already another three-argument constructor in the packet
class.
In many places where the packet information was printed as part of
DPRINTFs, request packets would be printed with a numeric "dest" that
would always be -1 (Broadcast) and that field is now removed from the
printing.
2012-04-14 11:45:55 +02:00
|
|
|
ifetch_pkt = new Packet(req, MemCmd::ReadReq);
|
2008-10-13 04:32:06 +02:00
|
|
|
ifetch_pkt->dataStatic(&inst);
|
2011-05-05 03:38:27 +02:00
|
|
|
DPRINTF(SimpleCPU, " -- pkt addr: %#x\n", ifetch_pkt->getAddr());
|
2008-10-13 04:32:06 +02:00
|
|
|
|
MEM: Separate requests and responses for timing accesses
This patch moves send/recvTiming and send/recvTimingSnoop from the
Port base class to the MasterPort and SlavePort, and also splits them
into separate member functions for requests and responses:
send/recvTimingReq, send/recvTimingResp, and send/recvTimingSnoopReq,
send/recvTimingSnoopResp. A master port sends requests and receives
responses, and also receives snoop requests and sends snoop
responses. A slave port has the reciprocal behaviour as it receives
requests and sends responses, and sends snoop requests and receives
snoop responses.
For all MemObjects that have only master ports or slave ports (but not
both), e.g. a CPU, or a PIO device, this patch merely adds more
clarity to what kind of access is taking place. For example, a CPU
port used to call sendTiming, and will now call
sendTimingReq. Similarly, a response previously came back through
recvTiming, which is now recvTimingResp. For the modules that have
both master and slave ports, e.g. the bus, the behaviour was
previously relying on branches based on pkt->isRequest(), and this is
now replaced with a direct call to the apprioriate member function
depending on the type of access. Please note that send/recvRetry is
still shared by all the timing accessors and remains in the Port base
class for now (to maintain the current bus functionality and avoid
changing the statistics of all regressions).
The packet queue is split into a MasterPort and SlavePort version to
facilitate the use of the new timing accessors. All uses of the
PacketQueue are updated accordingly.
With this patch, the type of packet (request or response) is now well
defined for each type of access, and asserts on pkt->isRequest() and
pkt->isResponse() are now moved to the appropriate send member
functions. It is also worth noting that sendTimingSnoopReq no longer
returns a boolean, as the semantics do not alow snoop requests to be
rejected or stalled. All these assumptions are now excplicitly part of
the port interface itself.
2012-05-01 19:40:42 +02:00
|
|
|
if (!icachePort.sendTimingReq(ifetch_pkt)) {
|
2009-02-25 19:16:15 +01:00
|
|
|
// Need to wait for retry
|
|
|
|
_status = IcacheRetry;
|
2006-05-16 23:36:50 +02:00
|
|
|
} else {
|
2009-02-25 19:16:15 +01:00
|
|
|
// Need to wait for cache to respond
|
|
|
|
_status = IcacheWaitResponse;
|
|
|
|
// ownership of packet transferred to memory system
|
|
|
|
ifetch_pkt = NULL;
|
2006-05-16 23:36:50 +02:00
|
|
|
}
|
|
|
|
} else {
|
2011-05-05 03:38:27 +02:00
|
|
|
DPRINTF(SimpleCPU, "Translation of addr %#x faulted\n", req->getVaddr());
|
2009-02-25 19:16:15 +01:00
|
|
|
delete req;
|
|
|
|
// fetch fault: advance directly to next instruction (fault handler)
|
2012-11-02 17:32:01 +01:00
|
|
|
_status = BaseSimpleCPU::Running;
|
2009-02-25 19:16:15 +01:00
|
|
|
advanceInst(fault);
|
2006-05-16 23:36:50 +02:00
|
|
|
}
|
2006-10-08 06:55:05 +02:00
|
|
|
|
2014-10-16 11:49:41 +02:00
|
|
|
updateCycleCounts();
|
2006-05-16 23:36:50 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
void
|
2014-09-19 16:35:18 +02:00
|
|
|
TimingSimpleCPU::advanceInst(const Fault &fault)
|
2006-05-16 23:36:50 +02:00
|
|
|
{
|
2015-09-30 18:14:19 +02:00
|
|
|
SimpleExecContext &t_info = *threadInfo[curThread];
|
|
|
|
|
2011-05-05 03:38:27 +02:00
|
|
|
if (_status == Faulting)
|
|
|
|
return;
|
|
|
|
|
|
|
|
if (fault != NoFault) {
|
|
|
|
advancePC(fault);
|
|
|
|
DPRINTF(SimpleCPU, "Fault occured, scheduling fetch event\n");
|
2013-04-22 19:20:31 +02:00
|
|
|
reschedule(fetchEvent, clockEdge(), true);
|
2011-05-05 03:38:27 +02:00
|
|
|
_status = Faulting;
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2015-09-30 18:14:19 +02:00
|
|
|
if (!t_info.stayAtPC)
|
2008-11-10 06:55:01 +01:00
|
|
|
advancePC(fault);
|
2006-05-16 23:36:50 +02:00
|
|
|
|
2013-01-07 19:05:46 +01:00
|
|
|
if (tryCompleteDrain())
|
|
|
|
return;
|
|
|
|
|
2012-11-02 17:32:01 +01:00
|
|
|
if (_status == BaseSimpleCPU::Running) {
|
2006-05-19 04:54:19 +02:00
|
|
|
// kick off fetch of next instruction... callback from icache
|
|
|
|
// response will cause that instruction to be executed,
|
|
|
|
// keeping the CPU running.
|
|
|
|
fetch();
|
|
|
|
}
|
2006-05-16 23:36:50 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
void
|
2006-10-20 09:10:12 +02:00
|
|
|
TimingSimpleCPU::completeIfetch(PacketPtr pkt)
|
2006-05-16 23:36:50 +02:00
|
|
|
{
|
2015-09-30 18:14:19 +02:00
|
|
|
SimpleExecContext& t_info = *threadInfo[curThread];
|
|
|
|
|
2011-05-05 03:38:27 +02:00
|
|
|
DPRINTF(SimpleCPU, "Complete ICache Fetch for addr %#x\n", pkt ?
|
|
|
|
pkt->getAddr() : 0);
|
|
|
|
|
2006-05-16 23:36:50 +02:00
|
|
|
// received a response from the icache: execute the received
|
|
|
|
// instruction
|
2008-10-13 04:32:06 +02:00
|
|
|
assert(!pkt || !pkt->isError());
|
2006-05-16 23:36:50 +02:00
|
|
|
assert(_status == IcacheWaitResponse);
|
2006-06-30 01:45:24 +02:00
|
|
|
|
2012-11-02 17:32:01 +01:00
|
|
|
_status = BaseSimpleCPU::Running;
|
2006-05-26 20:33:43 +02:00
|
|
|
|
2014-10-16 11:49:41 +02:00
|
|
|
updateCycleCounts();
|
2006-10-08 06:55:05 +02:00
|
|
|
|
2014-01-24 22:29:30 +01:00
|
|
|
if (pkt)
|
|
|
|
pkt->req->setAccessLatency();
|
|
|
|
|
|
|
|
|
2006-05-16 23:36:50 +02:00
|
|
|
preExecute();
|
2010-11-08 20:58:22 +01:00
|
|
|
if (curStaticInst && curStaticInst->isMemRef()) {
|
2006-05-16 23:36:50 +02:00
|
|
|
// load or store: just send to dcache
|
2015-09-30 18:14:19 +02:00
|
|
|
Fault fault = curStaticInst->initiateAcc(&t_info, traceData);
|
2011-02-12 01:29:35 +01:00
|
|
|
|
|
|
|
// If we're not running now the instruction will complete in a dcache
|
|
|
|
// response callback or the instruction faulted and has started an
|
|
|
|
// ifetch
|
2012-11-02 17:32:01 +01:00
|
|
|
if (_status == BaseSimpleCPU::Running) {
|
2009-02-25 19:16:15 +01:00
|
|
|
if (fault != NoFault && traceData) {
|
2007-08-27 05:29:09 +02:00
|
|
|
// If there was a fault, we shouldn't trace this instruction.
|
|
|
|
delete traceData;
|
|
|
|
traceData = NULL;
|
2006-10-08 19:53:24 +02:00
|
|
|
}
|
2007-08-27 05:25:42 +02:00
|
|
|
|
2006-05-26 20:33:43 +02:00
|
|
|
postExecute();
|
2007-10-01 08:55:27 +02:00
|
|
|
// @todo remove me after debugging with legion done
|
|
|
|
if (curStaticInst && (!curStaticInst->isMicroop() ||
|
|
|
|
curStaticInst->isFirstMicroop()))
|
|
|
|
instCnt++;
|
2006-05-26 20:33:43 +02:00
|
|
|
advanceInst(fault);
|
|
|
|
}
|
2008-11-10 06:55:01 +01:00
|
|
|
} else if (curStaticInst) {
|
2006-05-16 23:36:50 +02:00
|
|
|
// non-memory instruction: execute completely now
|
2015-09-30 18:14:19 +02:00
|
|
|
Fault fault = curStaticInst->execute(&t_info, traceData);
|
2007-08-27 05:25:42 +02:00
|
|
|
|
|
|
|
// keep an instruction count
|
|
|
|
if (fault == NoFault)
|
|
|
|
countInst();
|
2010-08-26 02:10:43 +02:00
|
|
|
else if (traceData && !DTRACE(ExecFaulting)) {
|
2007-08-27 05:29:09 +02:00
|
|
|
delete traceData;
|
|
|
|
traceData = NULL;
|
|
|
|
}
|
2007-08-27 05:25:42 +02:00
|
|
|
|
2006-05-26 20:33:43 +02:00
|
|
|
postExecute();
|
2007-10-01 08:55:27 +02:00
|
|
|
// @todo remove me after debugging with legion done
|
|
|
|
if (curStaticInst && (!curStaticInst->isMicroop() ||
|
2015-09-30 18:14:19 +02:00
|
|
|
curStaticInst->isFirstMicroop()))
|
2007-10-01 08:55:27 +02:00
|
|
|
instCnt++;
|
2006-05-26 20:33:43 +02:00
|
|
|
advanceInst(fault);
|
2008-11-10 06:55:01 +01:00
|
|
|
} else {
|
|
|
|
advanceInst(NoFault);
|
2006-05-16 23:36:50 +02:00
|
|
|
}
|
2006-11-14 23:22:32 +01:00
|
|
|
|
2008-10-13 04:32:06 +02:00
|
|
|
if (pkt) {
|
|
|
|
delete pkt->req;
|
|
|
|
delete pkt;
|
|
|
|
}
|
2006-05-16 23:36:50 +02:00
|
|
|
}
|
|
|
|
|
2006-07-21 01:00:40 +02:00
|
|
|
void
|
|
|
|
TimingSimpleCPU::IcachePort::ITickEvent::process()
|
|
|
|
{
|
|
|
|
cpu->completeIfetch(pkt);
|
|
|
|
}
|
2006-05-16 23:36:50 +02:00
|
|
|
|
|
|
|
bool
|
MEM: Separate requests and responses for timing accesses
This patch moves send/recvTiming and send/recvTimingSnoop from the
Port base class to the MasterPort and SlavePort, and also splits them
into separate member functions for requests and responses:
send/recvTimingReq, send/recvTimingResp, and send/recvTimingSnoopReq,
send/recvTimingSnoopResp. A master port sends requests and receives
responses, and also receives snoop requests and sends snoop
responses. A slave port has the reciprocal behaviour as it receives
requests and sends responses, and sends snoop requests and receives
snoop responses.
For all MemObjects that have only master ports or slave ports (but not
both), e.g. a CPU, or a PIO device, this patch merely adds more
clarity to what kind of access is taking place. For example, a CPU
port used to call sendTiming, and will now call
sendTimingReq. Similarly, a response previously came back through
recvTiming, which is now recvTimingResp. For the modules that have
both master and slave ports, e.g. the bus, the behaviour was
previously relying on branches based on pkt->isRequest(), and this is
now replaced with a direct call to the apprioriate member function
depending on the type of access. Please note that send/recvRetry is
still shared by all the timing accessors and remains in the Port base
class for now (to maintain the current bus functionality and avoid
changing the statistics of all regressions).
The packet queue is split into a MasterPort and SlavePort version to
facilitate the use of the new timing accessors. All uses of the
PacketQueue are updated accordingly.
With this patch, the type of packet (request or response) is now well
defined for each type of access, and asserts on pkt->isRequest() and
pkt->isResponse() are now moved to the appropriate send member
functions. It is also worth noting that sendTimingSnoopReq no longer
returns a boolean, as the semantics do not alow snoop requests to be
rejected or stalled. All these assumptions are now excplicitly part of
the port interface itself.
2012-05-01 19:40:42 +02:00
|
|
|
TimingSimpleCPU::IcachePort::recvTimingResp(PacketPtr pkt)
|
2006-05-16 23:36:50 +02:00
|
|
|
{
|
2015-02-03 20:25:27 +01:00
|
|
|
DPRINTF(SimpleCPU, "Received fetch response %#x\n", pkt->getAddr());
|
|
|
|
// we should only ever see one response per cycle since we only
|
|
|
|
// issue a new request once this response is sunk
|
|
|
|
assert(!tickEvent.scheduled());
|
2012-08-22 17:39:59 +02:00
|
|
|
// delay processing of returned data until next CPU clock edge
|
2015-02-03 20:25:27 +01:00
|
|
|
tickEvent.schedule(pkt, cpu->clockEdge());
|
MEM: Separate snoops and normal memory requests/responses
This patch introduces port access methods that separates snoop
request/responses from normal memory request/responses. The
differentiation is made for functional, atomic and timing accesses and
builds on the introduction of master and slave ports.
Before the introduction of this patch, the packets belonging to the
different phases of the protocol (request -> [forwarded snoop request
-> snoop response]* -> response) all use the same port access
functions, even though the snoop packets flow in the opposite
direction to the normal packet. That is, a coherent master sends
normal request and receives responses, but receives snoop requests and
sends snoop responses (vice versa for the slave). These two distinct
phases now use different access functions, as described below.
Starting with the functional access, a master sends a request to a
slave through sendFunctional, and the request packet is turned into a
response before the call returns. In a system without cache coherence,
this is all that is needed from the functional interface. For the
cache-coherent scenario, a slave also sends snoop requests to coherent
masters through sendFunctionalSnoop, with responses returned within
the same packet pointer. This is currently used by the bus and caches,
and the LSQ of the O3 CPU. The send/recvFunctional and
send/recvFunctionalSnoop are moved from the Port super class to the
appropriate subclass.
Atomic accesses follow the same flow as functional accesses, with
request being sent from master to slave through sendAtomic. In the
case of cache-coherent ports, a slave can send snoop requests to a
master through sendAtomicSnoop. Just as for the functional access
methods, the atomic send and receive member functions are moved to the
appropriate subclasses.
The timing access methods are different from the functional and atomic
in that requests and responses are separated in time and
send/recvTiming are used for both directions. Hence, a master uses
sendTiming to send a request to a slave, and a slave uses sendTiming
to send a response back to a master, at a later point in time. Snoop
requests and responses travel in the opposite direction, similar to
what happens in functional and atomic accesses. With the introduction
of this patch, it is possible to determine the direction of packets in
the bus, and no longer necessary to look for both a master and a slave
port with the requested port id.
In contrast to the normal recvFunctional, recvAtomic and recvTiming
that are pure virtual functions, the recvFunctionalSnoop,
recvAtomicSnoop and recvTimingSnoop have a default implementation that
calls panic. This is to allow non-coherent master and slave ports to
not implement these functions.
2012-04-14 11:45:07 +02:00
|
|
|
|
2007-05-08 00:58:38 +02:00
|
|
|
return true;
|
2006-05-16 23:36:50 +02:00
|
|
|
}
|
|
|
|
|
2006-05-31 00:57:42 +02:00
|
|
|
void
|
2015-03-02 10:00:35 +01:00
|
|
|
TimingSimpleCPU::IcachePort::recvReqRetry()
|
2006-05-16 23:36:50 +02:00
|
|
|
{
|
|
|
|
// we shouldn't get a retry unless we have a packet that we're
|
|
|
|
// waiting to transmit
|
|
|
|
assert(cpu->ifetch_pkt != NULL);
|
|
|
|
assert(cpu->_status == IcacheRetry);
|
2006-10-20 09:10:12 +02:00
|
|
|
PacketPtr tmp = cpu->ifetch_pkt;
|
MEM: Separate requests and responses for timing accesses
This patch moves send/recvTiming and send/recvTimingSnoop from the
Port base class to the MasterPort and SlavePort, and also splits them
into separate member functions for requests and responses:
send/recvTimingReq, send/recvTimingResp, and send/recvTimingSnoopReq,
send/recvTimingSnoopResp. A master port sends requests and receives
responses, and also receives snoop requests and sends snoop
responses. A slave port has the reciprocal behaviour as it receives
requests and sends responses, and sends snoop requests and receives
snoop responses.
For all MemObjects that have only master ports or slave ports (but not
both), e.g. a CPU, or a PIO device, this patch merely adds more
clarity to what kind of access is taking place. For example, a CPU
port used to call sendTiming, and will now call
sendTimingReq. Similarly, a response previously came back through
recvTiming, which is now recvTimingResp. For the modules that have
both master and slave ports, e.g. the bus, the behaviour was
previously relying on branches based on pkt->isRequest(), and this is
now replaced with a direct call to the apprioriate member function
depending on the type of access. Please note that send/recvRetry is
still shared by all the timing accessors and remains in the Port base
class for now (to maintain the current bus functionality and avoid
changing the statistics of all regressions).
The packet queue is split into a MasterPort and SlavePort version to
facilitate the use of the new timing accessors. All uses of the
PacketQueue are updated accordingly.
With this patch, the type of packet (request or response) is now well
defined for each type of access, and asserts on pkt->isRequest() and
pkt->isResponse() are now moved to the appropriate send member
functions. It is also worth noting that sendTimingSnoopReq no longer
returns a boolean, as the semantics do not alow snoop requests to be
rejected or stalled. All these assumptions are now excplicitly part of
the port interface itself.
2012-05-01 19:40:42 +02:00
|
|
|
if (sendTimingReq(tmp)) {
|
2006-05-31 00:57:42 +02:00
|
|
|
cpu->_status = IcacheWaitResponse;
|
|
|
|
cpu->ifetch_pkt = NULL;
|
|
|
|
}
|
2006-05-16 23:36:50 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
void
|
2006-10-20 09:10:12 +02:00
|
|
|
TimingSimpleCPU::completeDataAccess(PacketPtr pkt)
|
2006-05-16 23:36:50 +02:00
|
|
|
{
|
|
|
|
// received a response from the dcache: complete the load or store
|
|
|
|
// instruction
|
2007-06-30 19:16:18 +02:00
|
|
|
assert(!pkt->isError());
|
2010-08-13 02:16:02 +02:00
|
|
|
assert(_status == DcacheWaitResponse || _status == DTBWaitResponse ||
|
|
|
|
pkt->req->getFlags().isSet(Request::NO_ACCESS));
|
2006-05-16 23:36:50 +02:00
|
|
|
|
2014-01-24 22:29:30 +01:00
|
|
|
pkt->req->setAccessLatency();
|
2014-10-16 11:49:41 +02:00
|
|
|
|
|
|
|
updateCycleCounts();
|
2006-10-08 06:55:05 +02:00
|
|
|
|
2008-11-10 06:56:28 +01:00
|
|
|
if (pkt->senderState) {
|
|
|
|
SplitFragmentSenderState * send_state =
|
|
|
|
dynamic_cast<SplitFragmentSenderState *>(pkt->senderState);
|
|
|
|
assert(send_state);
|
|
|
|
delete pkt->req;
|
|
|
|
delete pkt;
|
|
|
|
PacketPtr big_pkt = send_state->bigPkt;
|
|
|
|
delete send_state;
|
2016-02-07 02:21:18 +01:00
|
|
|
|
2008-11-10 06:56:28 +01:00
|
|
|
SplitMainSenderState * main_send_state =
|
|
|
|
dynamic_cast<SplitMainSenderState *>(big_pkt->senderState);
|
|
|
|
assert(main_send_state);
|
|
|
|
// Record the fact that this packet is no longer outstanding.
|
|
|
|
assert(main_send_state->outstanding != 0);
|
|
|
|
main_send_state->outstanding--;
|
|
|
|
|
|
|
|
if (main_send_state->outstanding) {
|
|
|
|
return;
|
|
|
|
} else {
|
|
|
|
delete main_send_state;
|
|
|
|
big_pkt->senderState = NULL;
|
|
|
|
pkt = big_pkt;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2012-11-02 17:32:01 +01:00
|
|
|
_status = BaseSimpleCPU::Running;
|
2008-11-10 06:56:28 +01:00
|
|
|
|
2015-09-30 18:14:19 +02:00
|
|
|
Fault fault = curStaticInst->completeAcc(pkt, threadInfo[curThread],
|
|
|
|
traceData);
|
2006-05-16 23:36:50 +02:00
|
|
|
|
2007-08-27 05:25:42 +02:00
|
|
|
// keep an instruction count
|
|
|
|
if (fault == NoFault)
|
|
|
|
countInst();
|
2007-08-27 05:29:09 +02:00
|
|
|
else if (traceData) {
|
|
|
|
// If there was a fault, we shouldn't trace this instruction.
|
|
|
|
delete traceData;
|
|
|
|
traceData = NULL;
|
|
|
|
}
|
2007-08-27 05:25:42 +02:00
|
|
|
|
2006-05-26 20:33:43 +02:00
|
|
|
delete pkt->req;
|
|
|
|
delete pkt;
|
|
|
|
|
|
|
|
postExecute();
|
2006-10-10 01:13:06 +02:00
|
|
|
|
2006-05-26 20:33:43 +02:00
|
|
|
advanceInst(fault);
|
2006-05-16 23:36:50 +02:00
|
|
|
}
|
|
|
|
|
2014-10-16 11:49:41 +02:00
|
|
|
void
|
|
|
|
TimingSimpleCPU::updateCycleCounts()
|
|
|
|
{
|
|
|
|
const Cycles delta(curCycle() - previousCycle);
|
|
|
|
|
|
|
|
numCycles += delta;
|
|
|
|
ppCycles->notify(delta);
|
|
|
|
|
|
|
|
previousCycle = curCycle();
|
|
|
|
}
|
|
|
|
|
2014-01-24 22:29:30 +01:00
|
|
|
void
|
|
|
|
TimingSimpleCPU::DcachePort::recvTimingSnoopReq(PacketPtr pkt)
|
|
|
|
{
|
2015-09-30 18:14:19 +02:00
|
|
|
for (ThreadID tid = 0; tid < cpu->numThreads; tid++) {
|
|
|
|
if (cpu->getCpuAddrMonitor(tid)->doMonitor(pkt)) {
|
2015-09-30 18:14:19 +02:00
|
|
|
cpu->wakeup(tid);
|
2015-09-30 18:14:19 +02:00
|
|
|
}
|
2014-11-06 12:42:22 +01:00
|
|
|
}
|
2015-09-30 18:14:19 +02:00
|
|
|
|
|
|
|
for (auto &t_info : cpu->threadInfo) {
|
|
|
|
TheISA::handleLockedSnoop(t_info->thread, pkt, cacheBlockMask);
|
|
|
|
}
|
2014-01-24 22:29:30 +01:00
|
|
|
}
|
|
|
|
|
2014-11-06 12:42:22 +01:00
|
|
|
void
|
|
|
|
TimingSimpleCPU::DcachePort::recvFunctionalSnoop(PacketPtr pkt)
|
|
|
|
{
|
2015-09-30 18:14:19 +02:00
|
|
|
for (ThreadID tid = 0; tid < cpu->numThreads; tid++) {
|
2016-02-07 02:21:19 +01:00
|
|
|
if (cpu->getCpuAddrMonitor(tid)->doMonitor(pkt)) {
|
2015-09-30 18:14:19 +02:00
|
|
|
cpu->wakeup(tid);
|
2015-09-30 18:14:19 +02:00
|
|
|
}
|
2014-11-06 12:42:22 +01:00
|
|
|
}
|
|
|
|
}
|
2014-01-24 22:29:30 +01:00
|
|
|
|
2006-05-16 23:36:50 +02:00
|
|
|
bool
|
MEM: Separate requests and responses for timing accesses
This patch moves send/recvTiming and send/recvTimingSnoop from the
Port base class to the MasterPort and SlavePort, and also splits them
into separate member functions for requests and responses:
send/recvTimingReq, send/recvTimingResp, and send/recvTimingSnoopReq,
send/recvTimingSnoopResp. A master port sends requests and receives
responses, and also receives snoop requests and sends snoop
responses. A slave port has the reciprocal behaviour as it receives
requests and sends responses, and sends snoop requests and receives
snoop responses.
For all MemObjects that have only master ports or slave ports (but not
both), e.g. a CPU, or a PIO device, this patch merely adds more
clarity to what kind of access is taking place. For example, a CPU
port used to call sendTiming, and will now call
sendTimingReq. Similarly, a response previously came back through
recvTiming, which is now recvTimingResp. For the modules that have
both master and slave ports, e.g. the bus, the behaviour was
previously relying on branches based on pkt->isRequest(), and this is
now replaced with a direct call to the apprioriate member function
depending on the type of access. Please note that send/recvRetry is
still shared by all the timing accessors and remains in the Port base
class for now (to maintain the current bus functionality and avoid
changing the statistics of all regressions).
The packet queue is split into a MasterPort and SlavePort version to
facilitate the use of the new timing accessors. All uses of the
PacketQueue are updated accordingly.
With this patch, the type of packet (request or response) is now well
defined for each type of access, and asserts on pkt->isRequest() and
pkt->isResponse() are now moved to the appropriate send member
functions. It is also worth noting that sendTimingSnoopReq no longer
returns a boolean, as the semantics do not alow snoop requests to be
rejected or stalled. All these assumptions are now excplicitly part of
the port interface itself.
2012-05-01 19:40:42 +02:00
|
|
|
TimingSimpleCPU::DcachePort::recvTimingResp(PacketPtr pkt)
|
2006-05-16 23:36:50 +02:00
|
|
|
{
|
2015-02-03 20:25:27 +01:00
|
|
|
DPRINTF(SimpleCPU, "Received load/store response %#x\n", pkt->getAddr());
|
2006-07-21 01:00:40 +02:00
|
|
|
|
2015-02-03 20:25:27 +01:00
|
|
|
// The timing CPU is not really ticked, instead it relies on the
|
|
|
|
// memory system (fetch and load/store) to set the pace.
|
|
|
|
if (!tickEvent.scheduled()) {
|
|
|
|
// Delay processing of returned data until next CPU clock edge
|
|
|
|
tickEvent.schedule(pkt, cpu->clockEdge());
|
|
|
|
return true;
|
2012-08-22 17:39:59 +02:00
|
|
|
} else {
|
2015-02-03 20:25:27 +01:00
|
|
|
// In the case of a split transaction and a cache that is
|
|
|
|
// faster than a CPU we could get two responses in the
|
|
|
|
// same tick, delay the second one
|
2015-03-02 10:00:35 +01:00
|
|
|
if (!retryRespEvent.scheduled())
|
|
|
|
cpu->schedule(retryRespEvent, cpu->clockEdge(Cycles(1)));
|
2015-02-03 20:25:27 +01:00
|
|
|
return false;
|
2006-10-18 00:50:19 +02:00
|
|
|
}
|
2006-05-16 23:36:50 +02:00
|
|
|
}
|
|
|
|
|
2006-07-21 01:00:40 +02:00
|
|
|
void
|
|
|
|
TimingSimpleCPU::DcachePort::DTickEvent::process()
|
|
|
|
{
|
|
|
|
cpu->completeDataAccess(pkt);
|
|
|
|
}
|
|
|
|
|
2006-05-31 00:57:42 +02:00
|
|
|
void
|
2015-03-02 10:00:35 +01:00
|
|
|
TimingSimpleCPU::DcachePort::recvReqRetry()
|
2006-05-16 23:36:50 +02:00
|
|
|
{
|
|
|
|
// we shouldn't get a retry unless we have a packet that we're
|
|
|
|
// waiting to transmit
|
|
|
|
assert(cpu->dcache_pkt != NULL);
|
|
|
|
assert(cpu->_status == DcacheRetry);
|
2006-10-20 09:10:12 +02:00
|
|
|
PacketPtr tmp = cpu->dcache_pkt;
|
2008-11-10 06:56:28 +01:00
|
|
|
if (tmp->senderState) {
|
|
|
|
// This is a packet from a split access.
|
|
|
|
SplitFragmentSenderState * send_state =
|
|
|
|
dynamic_cast<SplitFragmentSenderState *>(tmp->senderState);
|
|
|
|
assert(send_state);
|
|
|
|
PacketPtr big_pkt = send_state->bigPkt;
|
2016-02-07 02:21:18 +01:00
|
|
|
|
2008-11-10 06:56:28 +01:00
|
|
|
SplitMainSenderState * main_send_state =
|
|
|
|
dynamic_cast<SplitMainSenderState *>(big_pkt->senderState);
|
|
|
|
assert(main_send_state);
|
|
|
|
|
MEM: Separate requests and responses for timing accesses
This patch moves send/recvTiming and send/recvTimingSnoop from the
Port base class to the MasterPort and SlavePort, and also splits them
into separate member functions for requests and responses:
send/recvTimingReq, send/recvTimingResp, and send/recvTimingSnoopReq,
send/recvTimingSnoopResp. A master port sends requests and receives
responses, and also receives snoop requests and sends snoop
responses. A slave port has the reciprocal behaviour as it receives
requests and sends responses, and sends snoop requests and receives
snoop responses.
For all MemObjects that have only master ports or slave ports (but not
both), e.g. a CPU, or a PIO device, this patch merely adds more
clarity to what kind of access is taking place. For example, a CPU
port used to call sendTiming, and will now call
sendTimingReq. Similarly, a response previously came back through
recvTiming, which is now recvTimingResp. For the modules that have
both master and slave ports, e.g. the bus, the behaviour was
previously relying on branches based on pkt->isRequest(), and this is
now replaced with a direct call to the apprioriate member function
depending on the type of access. Please note that send/recvRetry is
still shared by all the timing accessors and remains in the Port base
class for now (to maintain the current bus functionality and avoid
changing the statistics of all regressions).
The packet queue is split into a MasterPort and SlavePort version to
facilitate the use of the new timing accessors. All uses of the
PacketQueue are updated accordingly.
With this patch, the type of packet (request or response) is now well
defined for each type of access, and asserts on pkt->isRequest() and
pkt->isResponse() are now moved to the appropriate send member
functions. It is also worth noting that sendTimingSnoopReq no longer
returns a boolean, as the semantics do not alow snoop requests to be
rejected or stalled. All these assumptions are now excplicitly part of
the port interface itself.
2012-05-01 19:40:42 +02:00
|
|
|
if (sendTimingReq(tmp)) {
|
2008-11-10 06:56:28 +01:00
|
|
|
// If we were able to send without retrying, record that fact
|
|
|
|
// and try sending the other fragment.
|
|
|
|
send_state->clearFromParent();
|
|
|
|
int other_index = main_send_state->getPendingFragment();
|
|
|
|
if (other_index > 0) {
|
|
|
|
tmp = main_send_state->fragments[other_index];
|
|
|
|
cpu->dcache_pkt = tmp;
|
|
|
|
if ((big_pkt->isRead() && cpu->handleReadPacket(tmp)) ||
|
|
|
|
(big_pkt->isWrite() && cpu->handleWritePacket())) {
|
|
|
|
main_send_state->fragments[other_index] = NULL;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
cpu->_status = DcacheWaitResponse;
|
|
|
|
// memory system takes ownership of packet
|
|
|
|
cpu->dcache_pkt = NULL;
|
|
|
|
}
|
|
|
|
}
|
MEM: Separate requests and responses for timing accesses
This patch moves send/recvTiming and send/recvTimingSnoop from the
Port base class to the MasterPort and SlavePort, and also splits them
into separate member functions for requests and responses:
send/recvTimingReq, send/recvTimingResp, and send/recvTimingSnoopReq,
send/recvTimingSnoopResp. A master port sends requests and receives
responses, and also receives snoop requests and sends snoop
responses. A slave port has the reciprocal behaviour as it receives
requests and sends responses, and sends snoop requests and receives
snoop responses.
For all MemObjects that have only master ports or slave ports (but not
both), e.g. a CPU, or a PIO device, this patch merely adds more
clarity to what kind of access is taking place. For example, a CPU
port used to call sendTiming, and will now call
sendTimingReq. Similarly, a response previously came back through
recvTiming, which is now recvTimingResp. For the modules that have
both master and slave ports, e.g. the bus, the behaviour was
previously relying on branches based on pkt->isRequest(), and this is
now replaced with a direct call to the apprioriate member function
depending on the type of access. Please note that send/recvRetry is
still shared by all the timing accessors and remains in the Port base
class for now (to maintain the current bus functionality and avoid
changing the statistics of all regressions).
The packet queue is split into a MasterPort and SlavePort version to
facilitate the use of the new timing accessors. All uses of the
PacketQueue are updated accordingly.
With this patch, the type of packet (request or response) is now well
defined for each type of access, and asserts on pkt->isRequest() and
pkt->isResponse() are now moved to the appropriate send member
functions. It is also worth noting that sendTimingSnoopReq no longer
returns a boolean, as the semantics do not alow snoop requests to be
rejected or stalled. All these assumptions are now excplicitly part of
the port interface itself.
2012-05-01 19:40:42 +02:00
|
|
|
} else if (sendTimingReq(tmp)) {
|
2006-05-31 00:57:42 +02:00
|
|
|
cpu->_status = DcacheWaitResponse;
|
2006-10-08 19:53:24 +02:00
|
|
|
// memory system takes ownership of packet
|
2006-05-31 00:57:42 +02:00
|
|
|
cpu->dcache_pkt = NULL;
|
|
|
|
}
|
2006-05-16 23:36:50 +02:00
|
|
|
}
|
|
|
|
|
2008-10-09 13:58:24 +02:00
|
|
|
TimingSimpleCPU::IprEvent::IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu,
|
|
|
|
Tick t)
|
|
|
|
: pkt(_pkt), cpu(_cpu)
|
2007-10-01 08:55:27 +02:00
|
|
|
{
|
2008-10-09 13:58:24 +02:00
|
|
|
cpu->schedule(this, t);
|
2007-10-01 08:55:27 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
TimingSimpleCPU::IprEvent::process()
|
|
|
|
{
|
|
|
|
cpu->completeDataAccess(pkt);
|
|
|
|
}
|
|
|
|
|
|
|
|
const char *
|
2008-02-06 22:32:40 +01:00
|
|
|
TimingSimpleCPU::IprEvent::description() const
|
2007-10-01 08:55:27 +02:00
|
|
|
{
|
|
|
|
return "Timing Simple CPU Delay IPR event";
|
|
|
|
}
|
|
|
|
|
2006-05-16 23:36:50 +02:00
|
|
|
|
2008-01-02 22:46:22 +01:00
|
|
|
void
|
|
|
|
TimingSimpleCPU::printAddr(Addr a)
|
|
|
|
{
|
|
|
|
dcachePort.printAddr(a);
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2006-05-16 23:36:50 +02:00
|
|
|
////////////////////////////////////////////////////////////////////////
|
|
|
|
//
|
|
|
|
// TimingSimpleCPU Simulation Object
|
|
|
|
//
|
2007-07-24 06:51:38 +02:00
|
|
|
TimingSimpleCPU *
|
|
|
|
TimingSimpleCPUParams::create()
|
2006-05-16 23:36:50 +02:00
|
|
|
{
|
2008-08-11 21:22:16 +02:00
|
|
|
return new TimingSimpleCPU(this);
|
2006-05-16 23:36:50 +02:00
|
|
|
}
|