2007-06-23 01:03:42 +02:00
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/*
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2007-11-13 22:58:16 +01:00
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* Copyright (c) 2007 MIPS Technologies, Inc.
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2007-06-23 01:03:42 +02:00
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Jaidev Patwardhan
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*/
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#ifndef __ARCH_MIPS_PRA_CONSTANTS_HH__
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#define __ARCH_MIPS_PRA_CONSTANTS_HH__
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#include "arch/mips/types.hh"
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2009-07-21 05:14:15 +02:00
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#include "base/bitunion.hh"
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2007-06-23 01:03:42 +02:00
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namespace MipsISA
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{
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2009-07-21 05:14:15 +02:00
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BitUnion32(IndexReg)
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Bitfield<31> p;
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// Need to figure out how to put in the TLB specific bits here
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// For now, we assume that the entire length is used by the index
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// field In reality, Index_HI = N-1, where
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// N = Ceiling(log2(TLB Entries))
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Bitfield<30, 0> index;
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EndBitUnion(IndexReg)
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BitUnion32(RandomReg)
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// This has a problem similar to the IndexReg index field. We'll keep
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// both consistent at 30 for now
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Bitfield<30, 0> random;
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EndBitUnion(RandomReg)
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BitUnion64(EntryLoReg)
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Bitfield<63, 30> fill;
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Bitfield<29, 6> pfn; // Page frame number
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Bitfield<5, 3> c; // Coherency attribute
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Bitfield<2> d; // Dirty Bit
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Bitfield<1> v; // Valid Bit
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Bitfield<0> g; // Global Bit
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EndBitUnion(EntryLoReg)
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BitUnion64(ContextReg)
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Bitfield<63, 23> pteBase;
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Bitfield<22, 4> badVPN2;
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// Bits 3-0 are 0
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EndBitUnion(ContextReg)
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BitUnion32(PageMaskReg)
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// Bits 31-29 are 0
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Bitfield<28, 13> mask;
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Bitfield<12, 11> maskx;
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// Bits 10-0 are zero
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EndBitUnion(PageMaskReg)
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BitUnion32(PageGrainReg)
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Bitfield<31, 30> aseUp;
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Bitfield<29> elpa;
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Bitfield<28> esp;
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// Bits 27-13 are zeros
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Bitfield<12, 8> aseDn;
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// Bits 7-0 are zeros
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EndBitUnion(PageGrainReg)
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BitUnion32(WiredReg)
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// See note on Index register above
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Bitfield<30, 0> wired;
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EndBitUnion(WiredReg)
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BitUnion32(HWREnaReg)
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Bitfield<31, 30> impl;
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Bitfield<3, 0> mask;
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EndBitUnion(HWREnaReg)
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BitUnion64(EntryHiReg)
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Bitfield<63, 62> r;
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Bitfield<61, 40> fill;
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Bitfield<39, 13> vpn2;
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Bitfield<12, 11> vpn2x;
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Bitfield<7, 0> asid;
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EndBitUnion(EntryHiReg)
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BitUnion32(StatusReg)
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SubBitUnion(cu, 31, 28)
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Bitfield<31> cu3;
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Bitfield<30> cu2;
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Bitfield<29> cu1;
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Bitfield<28> cu0;
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EndSubBitUnion(cu)
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Bitfield<27> rp;
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Bitfield<26> fr;
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Bitfield<25> re;
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Bitfield<24> mx;
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Bitfield<23> px;
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Bitfield<22> bev;
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Bitfield<21> ts;
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Bitfield<20> sr;
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Bitfield<19> nmi;
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// Bit 18 is zero
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Bitfield<17, 16> impl;
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Bitfield<15, 10> ipl;
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2009-07-21 10:09:05 +02:00
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SubBitUnion(im, 15, 8)
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Bitfield<15> im7;
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Bitfield<14> im6;
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Bitfield<13> im5;
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Bitfield<12> im4;
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Bitfield<11> im3;
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Bitfield<10> im2;
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Bitfield<9> im1;
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Bitfield<8> im0;
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EndSubBitUnion(im)
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2009-07-21 05:14:15 +02:00
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Bitfield<7> kx;
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Bitfield<6> sx;
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Bitfield<5> ux;
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Bitfield<4, 3> ksu;
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Bitfield<4> um;
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Bitfield<3> r0;
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Bitfield<2> erl;
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Bitfield<1> exl;
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Bitfield<0> ie;
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EndBitUnion(StatusReg)
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BitUnion32(IntCtlReg)
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Bitfield<31, 29> ipti;
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Bitfield<28, 26> ippci;
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// Bits 26-10 are zeros
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Bitfield<9, 5> vs;
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// Bits 4-0 are zeros
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EndBitUnion(IntCtlReg)
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BitUnion32(SRSCtlReg)
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// Bits 31-30 are zeros
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Bitfield<29, 26> hss;
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// Bits 25-22 are zeros
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Bitfield<21, 18> eicss;
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// Bits 17-16 are zeros
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Bitfield<15, 12> ess;
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// Bits 11-10 are zeros
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Bitfield<9, 6> pss;
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// Bits 5-4 are zeros
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Bitfield<3, 0> css;
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EndBitUnion(SRSCtlReg)
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BitUnion32(SRSMapReg)
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Bitfield<31, 28> ssv7;
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Bitfield<27, 24> ssv6;
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Bitfield<23, 20> ssv5;
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Bitfield<19, 16> ssv4;
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Bitfield<15, 12> ssv3;
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Bitfield<11, 8> ssv2;
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Bitfield<7, 4> ssv1;
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Bitfield<3, 0> ssv0;
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EndBitUnion(SRSMapReg)
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BitUnion32(CauseReg)
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Bitfield<31> bd;
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Bitfield<30> ti;
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Bitfield<29, 28> ce;
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Bitfield<27> dc;
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Bitfield<26> pci;
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// Bits 25-24 are zeros
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Bitfield<23> iv;
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Bitfield<22> wp;
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// Bits 21-16 are zeros
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Bitfield<15, 10> ripl;
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2009-07-21 10:09:05 +02:00
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SubBitUnion(ip, 15, 8)
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Bitfield<15> ip7;
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Bitfield<14> ip6;
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Bitfield<13> ip5;
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Bitfield<12> ip4;
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Bitfield<11> ip3;
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Bitfield<10> ip2;
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Bitfield<9> ip1;
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Bitfield<8> ip0;
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EndSubBitUnion(ip);
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2009-07-21 05:14:15 +02:00
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// Bit 7 is zero
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Bitfield<6, 2> excCode;
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// Bits 1-0 are zeros
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EndBitUnion(CauseReg)
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BitUnion32(PRIdReg)
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Bitfield<31, 24> coOp;
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Bitfield<23, 16> coId;
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Bitfield<15, 8> procId;
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Bitfield<7, 0> rev;
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EndBitUnion(PRIdReg)
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BitUnion32(EBaseReg)
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// Bit 31 is one
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// Bit 30 is zero
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Bitfield<29, 12> exceptionBase;
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// Bits 11-10 are zeros
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Bitfield<9, 9> cpuNum;
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EndBitUnion(EBaseReg)
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BitUnion32(ConfigReg)
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Bitfield<31> m;
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Bitfield<30, 28> k23;
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Bitfield<27, 25> ku;
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Bitfield<24, 16> impl;
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Bitfield<15> be;
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Bitfield<14, 13> at;
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Bitfield<12, 10> ar;
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Bitfield<9, 7> mt;
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// Bits 6-4 are zeros
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Bitfield<3> vi;
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Bitfield<2, 0> k0;
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EndBitUnion(ConfigReg)
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BitUnion32(Config1Reg)
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Bitfield<31> m;
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Bitfield<30, 25> mmuSize;
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Bitfield<24, 22> is;
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Bitfield<21, 19> il;
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Bitfield<18, 16> ia;
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Bitfield<15, 13> ds;
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Bitfield<12, 10> dl;
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Bitfield<9, 7> da;
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Bitfield<6> c2;
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Bitfield<5> md;
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Bitfield<4> pc;
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Bitfield<3> wr;
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Bitfield<2> ca;
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Bitfield<1> ep;
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Bitfield<0> fp;
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EndBitUnion(Config1Reg)
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BitUnion32(Config2Reg)
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Bitfield<31> m;
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Bitfield<30, 28> tu;
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Bitfield<27, 24> ts;
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Bitfield<23, 20> tl;
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Bitfield<19, 16> ta;
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Bitfield<15, 12> su;
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Bitfield<11, 8> ss;
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Bitfield<7, 4> sl;
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Bitfield<3, 0> sa;
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EndBitUnion(Config2Reg)
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BitUnion32(Config3Reg)
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Bitfield<31> m;
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// Bits 30-11 are zeros
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Bitfield<10> dspp;
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// Bits 9-8 are zeros
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Bitfield<7> lpa;
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Bitfield<6> veic;
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Bitfield<5> vint;
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Bitfield<4> sp;
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// Bit 3 is zero
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Bitfield<2> mt;
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Bitfield<1> sm;
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Bitfield<0> tl;
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EndBitUnion(Config3Reg)
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BitUnion64(WatchLoReg)
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Bitfield<63, 3> vaddr;
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Bitfield<2> i;
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Bitfield<1> r;
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Bitfield<0> w;
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EndBitUnion(WatchLoReg)
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BitUnion32(WatchHiReg)
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Bitfield<31> m;
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Bitfield<30> g;
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// Bits 29-24 are zeros
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Bitfield<23, 16> asid;
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// Bits 15-12 are zeros
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Bitfield<11, 3> mask;
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Bitfield<2> i;
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Bitfield<1> r;
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Bitfield<0> w;
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EndBitUnion(WatchHiReg)
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BitUnion32(PerfCntCtlReg)
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Bitfield<31> m;
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Bitfield<30> w;
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// Bits 29-11 are zeros
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Bitfield<10, 5> event;
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Bitfield<4> ie;
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Bitfield<3> u;
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Bitfield<2> s;
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Bitfield<1> k;
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Bitfield<0> exl;
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EndBitUnion(PerfCntCtlReg)
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BitUnion32(CacheErrReg)
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Bitfield<31> er;
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Bitfield<30> ec;
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Bitfield<29> ed;
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Bitfield<28> et;
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Bitfield<27> es;
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Bitfield<26> ee;
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Bitfield<25> eb;
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Bitfield<24, 22> impl;
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Bitfield<22, 0> index;
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EndBitUnion(CacheErrReg)
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BitUnion32(TagLoReg)
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Bitfield<31, 8> pTagLo;
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Bitfield<7, 6> pState;
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Bitfield<5> l;
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Bitfield<4, 3> impl;
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// Bits 2-1 are zeros
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Bitfield<0> p;
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EndBitUnion(TagLoReg)
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2007-06-23 01:03:42 +02:00
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} // namespace MipsISA
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#endif
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