gem5/build_opts/ARM_FS

TARGET_ISA = 'arm'
CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU'
FULL_SYSTEM = 1
PROTOCOL = 'MI_example'
ARM: Boilerplate full-system code. --HG-- rename : src/arch/sparc/interrupts.hh => src/arch/arm/interrupts.hh rename : src/arch/sparc/kernel_stats.hh => src/arch/arm/kernel_stats.hh rename : src/arch/sparc/stacktrace.cc => src/arch/arm/stacktrace.cc rename : src/arch/sparc/system.cc => src/arch/arm/system.cc rename : src/arch/sparc/system.hh => src/arch/arm/system.hh rename : src/dev/sparc/T1000.py => src/dev/arm/Versatile.py rename : src/dev/sparc/t1000.cc => src/dev/arm/versatile.cc rename : src/dev/sparc/t1000.hh => src/dev/arm/versatile.hh 2009-11-18 01:02:08 +01:00			`TARGET_ISA = 'arm'`
ARM: Compile O3 CPU by default 2010-11-15 21:04:04 +01:00			`CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU'`
ARM: Boilerplate full-system code. --HG-- rename : src/arch/sparc/interrupts.hh => src/arch/arm/interrupts.hh rename : src/arch/sparc/kernel_stats.hh => src/arch/arm/kernel_stats.hh rename : src/arch/sparc/stacktrace.cc => src/arch/arm/stacktrace.cc rename : src/arch/sparc/system.cc => src/arch/arm/system.cc rename : src/arch/sparc/system.hh => src/arch/arm/system.hh rename : src/dev/sparc/T1000.py => src/dev/arm/Versatile.py rename : src/dev/sparc/t1000.cc => src/dev/arm/versatile.cc rename : src/dev/sparc/t1000.hh => src/dev/arm/versatile.hh 2009-11-18 01:02:08 +01:00			`FULL_SYSTEM = 1`
m5: Added PROTOCOL default for regress fix 2010-02-01 07:21:01 +01:00			`PROTOCOL = 'MI_example'`