839 lines
26 KiB
Text
839 lines
26 KiB
Text
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/*
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* Copyright (c) 1999-2005 Mark D. Hill and David A. Wood
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* $Id: MOSI_directory_1level-cache.sm 1.18 04/09/07 13:52:52-05:00 mikem@maya.cs.wisc.edu $
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*
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*/
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machine(L1Cache, "MOSI Directory Optimized") {
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MessageBuffer requestFromCache, network="To", virtual_network="0", ordered="false";
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MessageBuffer responseFromCache, network="To", virtual_network="2", ordered="false";
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MessageBuffer forwardedRequestToCache, network="From", virtual_network="1", ordered="true";
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MessageBuffer responseToCache, network="From", virtual_network="2", ordered="false";
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// STATES
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enumeration(State, desc="Cache states", default="L1Cache_State_I") {
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// Base states
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I, desc="Idle";
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S, desc="Shared";
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O, desc="Owned";
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M, desc="Modified", format="!b";
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// Transient States
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MI, desc="modified, issued PUTX, have not seen response yet";
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OI, desc="owned, issued PUTX, have not seen response yet";
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IS, desc="idle, issued GETS, have not seen response yet";
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ISI, desc="idle, issued GETS, saw INV, have not seen data for GETS yet", format="!b";
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IM, desc="idle, issued GETX, have not seen response yet";
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IMI, desc="idle, issued GETX, saw forwarded GETX";
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IMO, desc="idle, issued GETX, saw forwarded GETS";
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IMOI, desc="idle, issued GETX, saw forwarded GETS, saw forwarded GETX";
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// Note: OM is a strange state, because it is waiting for the line
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// to be stolen away, or look like it has been stolen away. The
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// common case is that we see a forward from the directory that is
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// really from us, we forwarded the data to our dataqueue, and
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// everythings works fine.
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OM, desc="owned, issued GETX, have not seen response yet";
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}
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// EVENTS
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enumeration(Event, desc="Cache events") {
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Load, desc="Load request from the processor";
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Load_prefetch, desc="Load prefetch request from the processor";
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Ifetch, desc="I-fetch request from the processor";
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Store_prefetch, desc="Store prefetch request from the processor";
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Store, desc="Store request from the processor";
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Replacement, desc="Replacement", format="!r";
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Forwarded_GETS, "Forwarded GETS", desc="Directory forwards GETS to us";
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Forwarded_GETX, "Forwarded GETX", desc="Directory forwards GETX to us";
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INV, "INV", desc="Invalidation", format="!r";
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Proc_ack, "Proc ack", desc="Ack from proc";
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Proc_last_ack, "Proc last ack", desc="Last ack", format="!r";
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Data_ack_0, "Data ack 0", desc="Data with ack count = 0";
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Data_ack_not_0, "Data ack not 0", desc="Data with ack count != 0 (but haven't seen all acks first";
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Data_ack_not_0_last, "Data ack not 0 last", desc="Data with ack count != 0 after having received all acks";
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Dir_WB_ack, "WB ack", desc="Writeback ack from dir";
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}
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// TYPES
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// CacheEntry
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structure(Entry, desc="...", interface="AbstractCacheEntry") {
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State CacheState, desc="cache state";
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DataBlock DataBlk, desc="data for the block";
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}
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// TBE fields
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structure(TBE, desc="...") {
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Address Address, desc="Physical address for this TBE";
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State TBEState, desc="Transient state";
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DataBlock DataBlk, desc="Buffer for the data block";
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int NumPendingAcks, desc="Number of acks that this processor is waiting for";
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NetDest ForwardGetS_IDs, desc="Set of the processors to forward the block";
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MachineID ForwardGetX_ID, desc="ID of the processor to forward the block";
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int ForwardGetX_AckCount, desc="Number of acks the GetX we are forwarded needs";
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bool isPrefetch, desc="Set if this was caused by a prefetch";
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}
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external_type(CacheMemory) {
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bool cacheAvail(Address);
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Address cacheProbe(Address);
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void allocate(Address);
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void deallocate(Address);
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Entry lookup(Address);
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void changePermission(Address, AccessPermission);
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bool isTagPresent(Address);
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}
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external_type(TBETable) {
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TBE lookup(Address);
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void allocate(Address);
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void deallocate(Address);
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bool isPresent(Address);
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}
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MessageBuffer mandatoryQueue, ordered="false", abstract_chip_ptr="true";
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MessageBuffer optionalQueue, ordered="false", abstract_chip_ptr="true";
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Sequencer sequencer, abstract_chip_ptr="true", constructor_hack="i";
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StoreBuffer storeBuffer, abstract_chip_ptr="true", constructor_hack="i";
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TBETable TBEs, template_hack="<L1Cache_TBE>";
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CacheMemory cacheMemory, template_hack="<L1Cache_Entry>", constructor_hack='L1_CACHE_NUM_SETS_BITS,L1_CACHE_ASSOC,MachineType_L1Cache,int_to_string(i)+"_unified L1"', abstract_chip_ptr="true";
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State getState(Address addr) {
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if(TBEs.isPresent(addr)) {
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return TBEs[addr].TBEState;
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} else if (cacheMemory.isTagPresent(addr)) {
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return cacheMemory[addr].CacheState;
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}
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return State:I;
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}
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void setState(Address addr, State state) {
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if (TBEs.isPresent(addr)) {
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TBEs[addr].TBEState := state;
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}
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if (cacheMemory.isTagPresent(addr)) {
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cacheMemory[addr].CacheState := state;
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// Set permission
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if ((state == State:I) || (state == State:MI) || (state == State:OI)) {
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cacheMemory.changePermission(addr, AccessPermission:Invalid);
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} else if (state == State:S || state == State:O) {
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cacheMemory.changePermission(addr, AccessPermission:Read_Only);
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} else if (state == State:M) {
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cacheMemory.changePermission(addr, AccessPermission:Read_Write);
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} else {
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cacheMemory.changePermission(addr, AccessPermission:Busy);
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}
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}
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}
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// ** OUT_PORTS **
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out_port(requestNetwork_out, RequestMsg, requestFromCache);
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out_port(responseNetwork_out, ResponseMsg, responseFromCache);
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// ** IN_PORTS **
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// Response Network
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in_port(responseNetwork_in, ResponseMsg, responseToCache) {
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if (responseNetwork_in.isReady()) {
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peek(responseNetwork_in, ResponseMsg) {
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if(in_msg.Type == CoherenceResponseType:DATA) {
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if(in_msg.NumPendingAcks == 0) {
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trigger(Event:Data_ack_0, in_msg.Address);
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} else {
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if(in_msg.NumPendingAcks + TBEs[in_msg.Address].NumPendingAcks != 0) {
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trigger(Event:Data_ack_not_0, in_msg.Address);
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} else {
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trigger(Event:Data_ack_not_0_last, in_msg.Address);
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}
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}
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} else if(in_msg.Type == CoherenceResponseType:ACK) {
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if(TBEs[in_msg.Address].NumPendingAcks != 1){
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trigger(Event:Proc_ack, in_msg.Address);
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} else {
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trigger(Event:Proc_last_ack, in_msg.Address);
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}
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}
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}
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}
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}
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// Forwarded Request network
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in_port(forwardedRequestNetwork_in, RequestMsg, forwardedRequestToCache) {
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if(forwardedRequestNetwork_in.isReady()) {
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peek(forwardedRequestNetwork_in, RequestMsg) {
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if(in_msg.Type == CoherenceRequestType:GETS) {
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trigger(Event:Forwarded_GETS, in_msg.Address);
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} else if (in_msg.Type == CoherenceRequestType:GETX) {
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trigger(Event:Forwarded_GETX, in_msg.Address);
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} else if (in_msg.Type == CoherenceRequestType:INV) {
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trigger(Event:INV, in_msg.Address);
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} else if (in_msg.Type == CoherenceRequestType:WB_ACK) {
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trigger(Event:Dir_WB_ack, in_msg.Address);
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} else {
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error("Invalid forwarded request type");
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}
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}
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}
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}
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// Mandatory Queue
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in_port(mandatoryQueue_in, CacheMsg, mandatoryQueue, desc="...") {
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if (mandatoryQueue_in.isReady()) {
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peek(mandatoryQueue_in, CacheMsg) {
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if (cacheMemory.cacheAvail(in_msg.Address) == false) {
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trigger(Event:Replacement, cacheMemory.cacheProbe(in_msg.Address));
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} else {
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if (in_msg.Type == CacheRequestType:LD) {
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trigger(Event:Load, in_msg.Address);
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} else if (in_msg.Type == CacheRequestType:IFETCH) {
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trigger(Event:Ifetch, in_msg.Address);
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} else if ((in_msg.Type == CacheRequestType:ST) || (in_msg.Type == CacheRequestType:ATOMIC)) {
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trigger(Event:Store, in_msg.Address);
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} else {
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error("Invalid CacheRequestType");
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}
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}
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}
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}
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}
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// Optional Queue
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in_port(optionalQueue_in, CacheMsg, optionalQueue, desc="...") {
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if (optionalQueue_in.isReady()) {
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peek(optionalQueue_in, CacheMsg) {
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if (cacheMemory.cacheAvail(in_msg.Address) == false) {
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trigger(Event:Replacement, cacheMemory.cacheProbe(in_msg.Address));
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} else {
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if (in_msg.Type == CacheRequestType:LD) {
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trigger(Event:Load_prefetch, in_msg.Address);
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} else if (in_msg.Type == CacheRequestType:IFETCH) {
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trigger(Event:Load_prefetch, in_msg.Address);
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} else if ((in_msg.Type == CacheRequestType:ST) || (in_msg.Type == CacheRequestType:ATOMIC)) {
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trigger(Event:Store_prefetch, in_msg.Address);
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} else {
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error("Invalid CacheRequestType");
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}
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}
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}
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}
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}
|
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// ACTIONS
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action(a_issueGETS, "a", desc="Issue GETS") {
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enqueue(requestNetwork_out, RequestMsg, latency="ISSUE_LATENCY") {
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out_msg.Address := address;
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out_msg.Type := CoherenceRequestType:GETS;
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out_msg.Requestor := machineID;
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out_msg.Destination.add(map_Address_to_Directory(address));
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|
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out_msg.MessageSize := MessageSizeType:Control;
|
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}
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|
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}
|
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|
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action(b_issueGETX, "b", desc="Issue GETX") {
|
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|
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enqueue(requestNetwork_out, RequestMsg, latency="ISSUE_LATENCY") {
|
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|
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out_msg.Address := address;
|
||
|
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out_msg.Type := CoherenceRequestType:GETX;
|
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|
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out_msg.Requestor := machineID;
|
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|
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out_msg.Destination.add(map_Address_to_Directory(address));
|
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|
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out_msg.MessageSize := MessageSizeType:Control;
|
||
|
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}
|
||
|
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}
|
||
|
|
|
||
|
|
action(d_issuePUTX, "d", desc="Issue PUTX") {
|
||
|
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enqueue(requestNetwork_out, RequestMsg, latency="ISSUE_LATENCY") {
|
||
|
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out_msg.Address := address;
|
||
|
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out_msg.Type := CoherenceRequestType:PUTX;
|
||
|
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out_msg.Requestor := machineID;
|
||
|
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out_msg.Destination.add(map_Address_to_Directory(address));
|
||
|
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out_msg.DataBlk := cacheMemory[address].DataBlk;
|
||
|
|
out_msg.MessageSize := MessageSizeType:Data;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
action(e_dataFromCacheToRequestor, "e", desc="Send data from cache to requestor") {
|
||
|
|
peek(forwardedRequestNetwork_in, RequestMsg) {
|
||
|
|
enqueue(responseNetwork_out, ResponseMsg, latency="CACHE_RESPONSE_LATENCY") {
|
||
|
|
out_msg.Address := address;
|
||
|
|
out_msg.Type := CoherenceResponseType:DATA;
|
||
|
|
out_msg.Sender := machineID;
|
||
|
|
out_msg.SenderMachine := MachineType:L1Cache;
|
||
|
|
out_msg.NumPendingAcks := in_msg.NumPendingAcks; // Needed when in state O and we see a GetX
|
||
|
|
out_msg.Destination.add(in_msg.Requestor);
|
||
|
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out_msg.DestMachine := MachineType:L1Cache;
|
||
|
|
DEBUG_EXPR(out_msg.Destination);
|
||
|
|
out_msg.DataBlk := cacheMemory[address].DataBlk;
|
||
|
|
out_msg.MessageSize := MessageSizeType:Data;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
action(g_allocateCacheBlock, "g", desc="Allocate cache block") {
|
||
|
|
if (cacheMemory.isTagPresent(address) == false) {
|
||
|
|
cacheMemory.allocate(address);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
action(h_load_hit, "h", desc="If not prefetch, notify sequencer the load completed.") {
|
||
|
|
DEBUG_EXPR(cacheMemory[address].DataBlk);
|
||
|
|
if((TBEs.isPresent(address) == false) || (TBEs[address].isPrefetch == false)) {
|
||
|
|
// Non-prefetch
|
||
|
|
sequencer.readCallback(address, cacheMemory[address].DataBlk);
|
||
|
|
} else {
|
||
|
|
// Prefetch - don't call back
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
action(hh_store_hit, "\h", desc="If not prefetch, notify sequencer that store completed.") {
|
||
|
|
DEBUG_EXPR(cacheMemory[address].DataBlk);
|
||
|
|
if((TBEs.isPresent(address) == false) || (TBEs[address].isPrefetch == false)) {
|
||
|
|
// Non-prefetch
|
||
|
|
sequencer.writeCallback(address, cacheMemory[address].DataBlk);
|
||
|
|
} else {
|
||
|
|
// Prefetch - don't call back
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
action(i_allocateTBE, "i", desc="Allocate TBE (isPrefetch=0, number of invalidates=0)") {
|
||
|
|
check_allocate(TBEs);
|
||
|
|
TBEs.allocate(address);
|
||
|
|
TBEs[address].NumPendingAcks := 0; // default value
|
||
|
|
TBEs[address].isPrefetch := false;
|
||
|
|
TBEs[address].ForwardGetS_IDs.clear();
|
||
|
|
}
|
||
|
|
|
||
|
|
action(j_setPrefetchBit, "j", desc="Set prefetch bit") {
|
||
|
|
TBEs[address].isPrefetch := true;
|
||
|
|
}
|
||
|
|
|
||
|
|
action(k_popMandatoryQueue, "k", desc="Pop mandatory queue.") {
|
||
|
|
mandatoryQueue_in.dequeue();
|
||
|
|
}
|
||
|
|
|
||
|
|
action(l_popForwardedRequestQueue, "l", desc="Pop incoming forwarded request queue") {
|
||
|
|
forwardedRequestNetwork_in.dequeue();
|
||
|
|
}
|
||
|
|
|
||
|
|
action(m_popOptionalQueue, "m", desc="Pop optional queue") {
|
||
|
|
optionalQueue_in.dequeue();
|
||
|
|
}
|
||
|
|
|
||
|
|
action(o_popIncomingResponseQueue, "o", desc="Pop Incoming Response queue") {
|
||
|
|
responseNetwork_in.dequeue();
|
||
|
|
}
|
||
|
|
|
||
|
|
action(p_addNumberOfPendingAcks, "p", desc="Add number of pending acks to TBE") {
|
||
|
|
peek(responseNetwork_in, ResponseMsg) {
|
||
|
|
DEBUG_EXPR(TBEs[address].NumPendingAcks);
|
||
|
|
TBEs[address].NumPendingAcks := TBEs[address].NumPendingAcks + in_msg.NumPendingAcks;
|
||
|
|
DEBUG_EXPR(in_msg.NumPendingAcks);
|
||
|
|
DEBUG_EXPR(TBEs[address].NumPendingAcks);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
action(q_decrementNumberOfPendingAcks, "q", desc="Decrement number of pending invalidations by one") {
|
||
|
|
DEBUG_EXPR(TBEs[address].NumPendingAcks);
|
||
|
|
TBEs[address].NumPendingAcks := TBEs[address].NumPendingAcks - 1;
|
||
|
|
DEBUG_EXPR(TBEs[address].NumPendingAcks);
|
||
|
|
}
|
||
|
|
|
||
|
|
action(s_deallocateTBE, "s", desc="Deallocate TBE") {
|
||
|
|
TBEs.deallocate(address);
|
||
|
|
}
|
||
|
|
|
||
|
|
action(t_sendAckToInvalidator, "t", desc="Send ack to invalidator") {
|
||
|
|
peek(forwardedRequestNetwork_in, RequestMsg) {
|
||
|
|
enqueue(responseNetwork_out, ResponseMsg, latency="NULL_LATENCY") {
|
||
|
|
out_msg.Address := address;
|
||
|
|
out_msg.Type := CoherenceResponseType:ACK;
|
||
|
|
out_msg.Sender := machineID;
|
||
|
|
out_msg.SenderMachine := MachineType:L1Cache;
|
||
|
|
out_msg.Destination.add(in_msg.Requestor);
|
||
|
|
out_msg.DestMachine := MachineType:L1Cache;
|
||
|
|
DEBUG_EXPR(out_msg.Destination);
|
||
|
|
out_msg.NumPendingAcks := 0;
|
||
|
|
out_msg.MessageSize := MessageSizeType:Control;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
action(u_writeDataToCache, "u", desc="Write data to cache") {
|
||
|
|
peek(responseNetwork_in, ResponseMsg) {
|
||
|
|
cacheMemory[address].DataBlk := in_msg.DataBlk;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
action(x_copyDataFromCacheToTBE, "x", desc="Copy data from cache to TBE") {
|
||
|
|
TBEs[address].DataBlk := cacheMemory[address].DataBlk;
|
||
|
|
}
|
||
|
|
|
||
|
|
action(y_dataFromTBEToRequestor, "y", desc="Send data from TBE to requestor") {
|
||
|
|
peek(forwardedRequestNetwork_in, RequestMsg) {
|
||
|
|
enqueue(responseNetwork_out, ResponseMsg, latency="NULL_LATENCY") {
|
||
|
|
out_msg.Address := address;
|
||
|
|
out_msg.Type := CoherenceResponseType:DATA;
|
||
|
|
out_msg.Sender := machineID;
|
||
|
|
out_msg.SenderMachine := MachineType:L1Cache;
|
||
|
|
out_msg.NumPendingAcks := in_msg.NumPendingAcks; // Needed when in state MS and we see a GetX
|
||
|
|
out_msg.Destination.add(in_msg.Requestor);
|
||
|
|
out_msg.DestMachine := MachineType:L1Cache;
|
||
|
|
DEBUG_EXPR(out_msg.Destination);
|
||
|
|
out_msg.DataBlk := TBEs[address].DataBlk;
|
||
|
|
out_msg.MessageSize := MessageSizeType:Data;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
action(z_stall, "z", desc="Stall") {
|
||
|
|
}
|
||
|
|
|
||
|
|
action(dd_recordGetSForwardID, "\d", desc="Record forwarded GetS for future forwarding") {
|
||
|
|
peek(forwardedRequestNetwork_in, RequestMsg) {
|
||
|
|
TBEs[address].ForwardGetS_IDs.add(in_msg.Requestor);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
action(ee_dataFromCacheToGetSForwardIDs, "\e", desc="Send data from cache to GetS ForwardIDs") {
|
||
|
|
// FIXME - In some cases this should be from the TBE, not the cache.
|
||
|
|
enqueue(responseNetwork_out, ResponseMsg, latency="NULL_LATENCY") {
|
||
|
|
out_msg.Address := address;
|
||
|
|
out_msg.Type := CoherenceResponseType:DATA;
|
||
|
|
out_msg.Sender := machineID;
|
||
|
|
out_msg.SenderMachine := MachineType:L1Cache;
|
||
|
|
out_msg.Destination := TBEs[address].ForwardGetS_IDs;
|
||
|
|
out_msg.DestMachine := MachineType:L1Cache;
|
||
|
|
DEBUG_EXPR(out_msg.Destination);
|
||
|
|
out_msg.DataBlk := cacheMemory[address].DataBlk;
|
||
|
|
out_msg.NumPendingAcks := 0;
|
||
|
|
out_msg.MessageSize := MessageSizeType:Data;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
action(ff_deallocateCacheBlock, "\f", desc="Deallocate cache block. Sets the cache to invalid, allowing a replacement in parallel with a fetch.") {
|
||
|
|
cacheMemory.deallocate(address);
|
||
|
|
}
|
||
|
|
|
||
|
|
action(gg_dataFromCacheToGetXForwardID, "\g", desc="Send data from cache to GetX ForwardID") {
|
||
|
|
// FIXME - In some cases this should be from the TBE, not the cache.
|
||
|
|
enqueue(responseNetwork_out, ResponseMsg, latency="NULL_LATENCY") {
|
||
|
|
out_msg.Address := address;
|
||
|
|
out_msg.Type := CoherenceResponseType:DATA;
|
||
|
|
out_msg.Sender := machineID;
|
||
|
|
out_msg.SenderMachine := MachineType:L1Cache;
|
||
|
|
out_msg.Destination.add(TBEs[address].ForwardGetX_ID);
|
||
|
|
out_msg.DestMachine := MachineType:L1Cache;
|
||
|
|
DEBUG_EXPR(out_msg.Destination);
|
||
|
|
out_msg.DataBlk := cacheMemory[address].DataBlk;
|
||
|
|
out_msg.NumPendingAcks := TBEs[address].ForwardGetX_AckCount;
|
||
|
|
out_msg.MessageSize := MessageSizeType:Data;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
action(ii_recordGetXForwardID, "\i", desc="Record forwarded GetX and ack count for future forwarding") {
|
||
|
|
peek(forwardedRequestNetwork_in, RequestMsg) {
|
||
|
|
TBEs[address].ForwardGetX_ID := in_msg.Requestor;
|
||
|
|
TBEs[address].ForwardGetX_AckCount := in_msg.NumPendingAcks;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
//*****************************************************
|
||
|
|
// TRANSITIONS
|
||
|
|
//*****************************************************
|
||
|
|
|
||
|
|
// Transitions for Load/Store/Prefetch/Replacement from transient states
|
||
|
|
transition({OM, OI, IS, ISI, IM, IMO, IMOI, IMI, MI}, {Load, Load_prefetch, Ifetch, Store, Store_prefetch, Replacement}) {
|
||
|
|
z_stall;
|
||
|
|
}
|
||
|
|
|
||
|
|
// Transitions from Idle
|
||
|
|
transition(I, {Load,Ifetch}, IS) {
|
||
|
|
g_allocateCacheBlock;
|
||
|
|
i_allocateTBE;
|
||
|
|
a_issueGETS;
|
||
|
|
k_popMandatoryQueue;
|
||
|
|
}
|
||
|
|
|
||
|
|
transition(I, {Load_prefetch}, IS) {
|
||
|
|
g_allocateCacheBlock;
|
||
|
|
i_allocateTBE;
|
||
|
|
j_setPrefetchBit;
|
||
|
|
a_issueGETS;
|
||
|
|
m_popOptionalQueue;
|
||
|
|
}
|
||
|
|
|
||
|
|
transition(I, Store, IM) {
|
||
|
|
g_allocateCacheBlock;
|
||
|
|
i_allocateTBE;
|
||
|
|
b_issueGETX;
|
||
|
|
k_popMandatoryQueue;
|
||
|
|
}
|
||
|
|
|
||
|
|
transition(I, Store_prefetch, IM) {
|
||
|
|
g_allocateCacheBlock;
|
||
|
|
i_allocateTBE;
|
||
|
|
j_setPrefetchBit;
|
||
|
|
b_issueGETX;
|
||
|
|
m_popOptionalQueue;
|
||
|
|
}
|
||
|
|
|
||
|
|
transition(I, Replacement) {
|
||
|
|
ff_deallocateCacheBlock;
|
||
|
|
}
|
||
|
|
|
||
|
|
transition(I, INV) {
|
||
|
|
t_sendAckToInvalidator;
|
||
|
|
l_popForwardedRequestQueue;
|
||
|
|
}
|
||
|
|
|
||
|
|
// Transitions from Shared
|
||
|
|
transition({S, O}, {Load,Ifetch}) {
|
||
|
|
h_load_hit;
|
||
|
|
k_popMandatoryQueue;
|
||
|
|
}
|
||
|
|
|
||
|
|
transition({S, O, M}, Load_prefetch) {
|
||
|
|
m_popOptionalQueue;
|
||
|
|
}
|
||
|
|
|
||
|
|
transition(S, Store, IM) {
|
||
|
|
i_allocateTBE;
|
||
|
|
b_issueGETX;
|
||
|
|
k_popMandatoryQueue;
|
||
|
|
}
|
||
|
|
|
||
|
|
transition(S, Store_prefetch, IM) {
|
||
|
|
i_allocateTBE;
|
||
|
|
j_setPrefetchBit;
|
||
|
|
b_issueGETX;
|
||
|
|
m_popOptionalQueue;
|
||
|
|
}
|
||
|
|
|
||
|
|
transition(S, Replacement, I) {
|
||
|
|
ff_deallocateCacheBlock;
|
||
|
|
}
|
||
|
|
|
||
|
|
transition(S, INV, I) {
|
||
|
|
t_sendAckToInvalidator;
|
||
|
|
l_popForwardedRequestQueue;
|
||
|
|
}
|
||
|
|
|
||
|
|
// Transitions from Modified
|
||
|
|
transition(M, {Load, Ifetch}) {
|
||
|
|
h_load_hit;
|
||
|
|
k_popMandatoryQueue;
|
||
|
|
}
|
||
|
|
|
||
|
|
transition(M, Store) {
|
||
|
|
hh_store_hit;
|
||
|
|
k_popMandatoryQueue;
|
||
|
|
}
|
||
|
|
|
||
|
|
transition(M, Store_prefetch) {
|
||
|
|
m_popOptionalQueue;
|
||
|
|
}
|
||
|
|
|
||
|
|
transition(M, Replacement, MI) {
|
||
|
|
i_allocateTBE;
|
||
|
|
d_issuePUTX;
|
||
|
|
x_copyDataFromCacheToTBE;
|
||
|
|
ff_deallocateCacheBlock;
|
||
|
|
}
|
||
|
|
|
||
|
|
transition(M, Forwarded_GETS, O) {
|
||
|
|
e_dataFromCacheToRequestor;
|
||
|
|
l_popForwardedRequestQueue;
|
||
|
|
}
|
||
|
|
|
||
|
|
transition(M, Forwarded_GETX, I) {
|
||
|
|
e_dataFromCacheToRequestor;
|
||
|
|
l_popForwardedRequestQueue;
|
||
|
|
}
|
||
|
|
|
||
|
|
// Transitions from O
|
||
|
|
transition(O, Store, OM) {
|
||
|
|
i_allocateTBE;
|
||
|
|
b_issueGETX;
|
||
|
|
k_popMandatoryQueue;
|
||
|
|
}
|
||
|
|
|
||
|
|
transition(O, Store_prefetch, OM) {
|
||
|
|
i_allocateTBE;
|
||
|
|
j_setPrefetchBit;
|
||
|
|
b_issueGETX;
|
||
|
|
m_popOptionalQueue;
|
||
|
|
}
|
||
|
|
|
||
|
|
transition(O, Replacement, OI){
|
||
|
|
i_allocateTBE;
|
||
|
|
d_issuePUTX;
|
||
|
|
x_copyDataFromCacheToTBE;
|
||
|
|
ff_deallocateCacheBlock;
|
||
|
|
}
|
||
|
|
|
||
|
|
transition(O, Forwarded_GETS) {
|
||
|
|
e_dataFromCacheToRequestor;
|
||
|
|
l_popForwardedRequestQueue;
|
||
|
|
}
|
||
|
|
|
||
|
|
transition(O, Forwarded_GETX, I) {
|
||
|
|
e_dataFromCacheToRequestor;
|
||
|
|
l_popForwardedRequestQueue;
|
||
|
|
}
|
||
|
|
|
||
|
|
// transitions from OI
|
||
|
|
|
||
|
|
transition(OI, Forwarded_GETS) {
|
||
|
|
y_dataFromTBEToRequestor;
|
||
|
|
l_popForwardedRequestQueue;
|
||
|
|
}
|
||
|
|
|
||
|
|
transition(OI, Forwarded_GETX) {
|
||
|
|
y_dataFromTBEToRequestor;
|
||
|
|
l_popForwardedRequestQueue;
|
||
|
|
}
|
||
|
|
|
||
|
|
transition(OI, Dir_WB_ack, I) {
|
||
|
|
s_deallocateTBE;
|
||
|
|
l_popForwardedRequestQueue;
|
||
|
|
}
|
||
|
|
|
||
|
|
// Transitions from IS
|
||
|
|
|
||
|
|
transition(IS, INV, ISI) {
|
||
|
|
t_sendAckToInvalidator;
|
||
|
|
l_popForwardedRequestQueue;
|
||
|
|
}
|
||
|
|
|
||
|
|
transition(IS, Data_ack_0, S) {
|
||
|
|
u_writeDataToCache;
|
||
|
|
h_load_hit;
|
||
|
|
s_deallocateTBE;
|
||
|
|
o_popIncomingResponseQueue;
|
||
|
|
}
|
||
|
|
|
||
|
|
// transitions from ISI
|
||
|
|
|
||
|
|
// in ISI, could get data from the Proc whose GETX caused INV to go from IS to ISI
|
||
|
|
// or, could get data from Dir if Dir's data lost race to Dir's INV
|
||
|
|
// or, could get data from Dir, if my GETS took forever to get to Dir, and the GETX
|
||
|
|
// processor already wrote it back
|
||
|
|
|
||
|
|
transition(ISI, Data_ack_0, I) {
|
||
|
|
u_writeDataToCache;
|
||
|
|
h_load_hit;
|
||
|
|
s_deallocateTBE;
|
||
|
|
o_popIncomingResponseQueue;
|
||
|
|
}
|
||
|
|
|
||
|
|
transition(ISI, INV) {
|
||
|
|
t_sendAckToInvalidator;
|
||
|
|
l_popForwardedRequestQueue;
|
||
|
|
}
|
||
|
|
|
||
|
|
// Transitions from IM
|
||
|
|
|
||
|
|
transition(IM, INV) { // do not need to go to IMI, since INV is for earlier epoch
|
||
|
|
t_sendAckToInvalidator;
|
||
|
|
l_popForwardedRequestQueue;
|
||
|
|
}
|
||
|
|
|
||
|
|
transition({IM, IMO}, Forwarded_GETS, IMO) {
|
||
|
|
dd_recordGetSForwardID;
|
||
|
|
l_popForwardedRequestQueue;
|
||
|
|
}
|
||
|
|
|
||
|
|
transition(IM, Forwarded_GETX, IMI) {
|
||
|
|
ii_recordGetXForwardID;
|
||
|
|
l_popForwardedRequestQueue;
|
||
|
|
}
|
||
|
|
|
||
|
|
transition(IM, {Data_ack_0, Data_ack_not_0_last}, M) {
|
||
|
|
u_writeDataToCache;
|
||
|
|
hh_store_hit;
|
||
|
|
s_deallocateTBE;
|
||
|
|
o_popIncomingResponseQueue;
|
||
|
|
}
|
||
|
|
|
||
|
|
transition(IM, Data_ack_not_0) {
|
||
|
|
u_writeDataToCache;
|
||
|
|
p_addNumberOfPendingAcks;
|
||
|
|
o_popIncomingResponseQueue;
|
||
|
|
}
|
||
|
|
|
||
|
|
transition(IM, Proc_ack) {
|
||
|
|
q_decrementNumberOfPendingAcks;
|
||
|
|
o_popIncomingResponseQueue;
|
||
|
|
}
|
||
|
|
|
||
|
|
transition(IM, Proc_last_ack, M) {
|
||
|
|
hh_store_hit;
|
||
|
|
s_deallocateTBE;
|
||
|
|
o_popIncomingResponseQueue;
|
||
|
|
}
|
||
|
|
|
||
|
|
// transitions from IMO
|
||
|
|
|
||
|
|
transition(IMO, Forwarded_GETX, IMOI) {
|
||
|
|
ii_recordGetXForwardID;
|
||
|
|
l_popForwardedRequestQueue;
|
||
|
|
}
|
||
|
|
|
||
|
|
transition(IMO, {Data_ack_0, Data_ack_not_0_last}, O) {
|
||
|
|
u_writeDataToCache;
|
||
|
|
hh_store_hit;
|
||
|
|
ee_dataFromCacheToGetSForwardIDs;
|
||
|
|
s_deallocateTBE;
|
||
|
|
o_popIncomingResponseQueue;
|
||
|
|
}
|
||
|
|
|
||
|
|
transition(IMO, Data_ack_not_0) {
|
||
|
|
u_writeDataToCache;
|
||
|
|
p_addNumberOfPendingAcks;
|
||
|
|
o_popIncomingResponseQueue;
|
||
|
|
}
|
||
|
|
|
||
|
|
transition(IMO, Proc_ack) {
|
||
|
|
q_decrementNumberOfPendingAcks;
|
||
|
|
o_popIncomingResponseQueue;
|
||
|
|
}
|
||
|
|
|
||
|
|
transition(IMO, Proc_last_ack, O) {
|
||
|
|
hh_store_hit;
|
||
|
|
ee_dataFromCacheToGetSForwardIDs;
|
||
|
|
s_deallocateTBE;
|
||
|
|
o_popIncomingResponseQueue;
|
||
|
|
}
|
||
|
|
|
||
|
|
// transitions from IMI
|
||
|
|
|
||
|
|
transition(IMI, {Data_ack_0, Data_ack_not_0_last}, I) {
|
||
|
|
u_writeDataToCache;
|
||
|
|
hh_store_hit;
|
||
|
|
gg_dataFromCacheToGetXForwardID;
|
||
|
|
s_deallocateTBE;
|
||
|
|
o_popIncomingResponseQueue;
|
||
|
|
}
|
||
|
|
|
||
|
|
transition(IMI, Data_ack_not_0) {
|
||
|
|
u_writeDataToCache;
|
||
|
|
p_addNumberOfPendingAcks;
|
||
|
|
o_popIncomingResponseQueue;
|
||
|
|
}
|
||
|
|
|
||
|
|
transition(IMI, Proc_ack) {
|
||
|
|
q_decrementNumberOfPendingAcks;
|
||
|
|
o_popIncomingResponseQueue;
|
||
|
|
}
|
||
|
|
|
||
|
|
transition(IMI, Proc_last_ack, I) {
|
||
|
|
hh_store_hit;
|
||
|
|
gg_dataFromCacheToGetXForwardID;
|
||
|
|
s_deallocateTBE;
|
||
|
|
o_popIncomingResponseQueue;
|
||
|
|
}
|
||
|
|
|
||
|
|
// transitions from IMOI
|
||
|
|
|
||
|
|
transition(IMOI, {Data_ack_0, Data_ack_not_0_last}, I) {
|
||
|
|
u_writeDataToCache;
|
||
|
|
hh_store_hit;
|
||
|
|
ee_dataFromCacheToGetSForwardIDs;
|
||
|
|
gg_dataFromCacheToGetXForwardID;
|
||
|
|
s_deallocateTBE;
|
||
|
|
o_popIncomingResponseQueue;
|
||
|
|
}
|
||
|
|
|
||
|
|
transition(IMOI, Data_ack_not_0) {
|
||
|
|
u_writeDataToCache;
|
||
|
|
p_addNumberOfPendingAcks;
|
||
|
|
o_popIncomingResponseQueue;
|
||
|
|
}
|
||
|
|
|
||
|
|
transition(IMOI, Proc_ack) {
|
||
|
|
q_decrementNumberOfPendingAcks;
|
||
|
|
o_popIncomingResponseQueue;
|
||
|
|
}
|
||
|
|
|
||
|
|
transition(IMOI, Proc_last_ack, I) {
|
||
|
|
hh_store_hit;
|
||
|
|
ee_dataFromCacheToGetSForwardIDs;
|
||
|
|
gg_dataFromCacheToGetXForwardID;
|
||
|
|
s_deallocateTBE;
|
||
|
|
o_popIncomingResponseQueue;
|
||
|
|
}
|
||
|
|
|
||
|
|
// Transitions from OM
|
||
|
|
transition(OM, Proc_ack) {
|
||
|
|
q_decrementNumberOfPendingAcks;
|
||
|
|
o_popIncomingResponseQueue;
|
||
|
|
}
|
||
|
|
|
||
|
|
transition(OM, Forwarded_GETS) {
|
||
|
|
e_dataFromCacheToRequestor;
|
||
|
|
l_popForwardedRequestQueue;
|
||
|
|
}
|
||
|
|
|
||
|
|
transition(OM, Forwarded_GETX, IM) {
|
||
|
|
e_dataFromCacheToRequestor;
|
||
|
|
l_popForwardedRequestQueue;
|
||
|
|
}
|
||
|
|
|
||
|
|
// Transitions from MI
|
||
|
|
|
||
|
|
transition(MI, Forwarded_GETS) {
|
||
|
|
y_dataFromTBEToRequestor;
|
||
|
|
l_popForwardedRequestQueue;
|
||
|
|
}
|
||
|
|
|
||
|
|
transition(MI, Forwarded_GETX) {
|
||
|
|
y_dataFromTBEToRequestor;
|
||
|
|
l_popForwardedRequestQueue;
|
||
|
|
}
|
||
|
|
|
||
|
|
transition(MI, Dir_WB_ack, I) {
|
||
|
|
s_deallocateTBE;
|
||
|
|
l_popForwardedRequestQueue;
|
||
|
|
}
|
||
|
|
}
|