gem5/tests/simple-timing.py

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Halfway through setting up new test structure... committing so O can move to my laptop. tests/SConscript: Start to simplify. --HG-- rename : tests/test1/ref/alpha/detailed/config.ini => tests/quick/eio1/ref/alpha/eio/detailed/config.ini rename : tests/test1/ref/alpha/detailed/config.out => tests/quick/eio1/ref/alpha/eio/detailed/config.out rename : tests/test1/ref/alpha/detailed/m5stats.txt => tests/quick/eio1/ref/alpha/eio/detailed/m5stats.txt rename : tests/test1/ref/alpha/detailed/stderr => tests/quick/eio1/ref/alpha/eio/detailed/stderr rename : tests/test1/ref/alpha/detailed/stdout => tests/quick/eio1/ref/alpha/eio/detailed/stdout rename : tests/test1/ref/alpha/atomic/config.ini => tests/quick/eio1/ref/alpha/eio/simple-atomic/config.ini rename : tests/test1/ref/alpha/atomic/config.out => tests/quick/eio1/ref/alpha/eio/simple-atomic/config.out rename : tests/test1/ref/alpha/atomic/m5stats.txt => tests/quick/eio1/ref/alpha/eio/simple-atomic/m5stats.txt rename : tests/test1/ref/alpha/atomic/stderr => tests/quick/eio1/ref/alpha/eio/simple-atomic/stderr rename : tests/test1/ref/alpha/atomic/stdout => tests/quick/eio1/ref/alpha/eio/simple-atomic/stdout rename : tests/test1/ref/alpha/timing/config.ini => tests/quick/eio1/ref/alpha/eio/simple-timing/config.ini rename : tests/test1/ref/alpha/timing/config.out => tests/quick/eio1/ref/alpha/eio/simple-timing/config.out rename : tests/test1/ref/alpha/timing/m5stats.txt => tests/quick/eio1/ref/alpha/eio/simple-timing/m5stats.txt rename : tests/test1/ref/alpha/timing/stderr => tests/quick/eio1/ref/alpha/eio/simple-timing/stderr rename : tests/test1/ref/alpha/timing/stdout => tests/quick/eio1/ref/alpha/eio/simple-timing/stdout extra : convert_revision : 924d2ee29d2a2709135ff8e5c5822fe47a8a60f6
2006-08-16 15:45:46 +02:00
import m5
from m5.objects import *
m5.AddToPath('../configs/common')
from SEConfig import *
class MyCache(BaseCache):
assoc = 2
block_size = 64
latency = 1
mshrs = 10
tgts_per_mshr = 5
cpu = TimingSimpleCPU()
cpu.icache = MyCache(size = '128kB')
cpu.dcache = MyCache(size = '256kB')
cpu.l2cache = MyCache(size = '2MB')
cpu.icache_port = cpu.icache.cpu_side
cpu.dcache_port = cpu.dcache.cpu_side
root = makeSESystem(cpu)