2008-10-07 06:53:25 +02:00
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October 6, 2008: m5_2.0_beta6
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--------------------
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New Features
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1. Support for gcc 4.3
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2. Core m5 code in libm5 for integration with other simulators
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3. Preliminary support for X86 SE mode
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4. Additional system calls emulated
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5. m5term updated to work on OS X
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6. Ability to disable listen sockets
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7. Event queue performance improvements and rewrite
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8. Better errors for unconnected memory ports
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Bug fixes
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1. ALPHA_SE O3 perlbmk benchmark
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2. Translation bug where O3 could fetch from uncachable memory
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3. Many minor bugs
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2007-04-27 20:53:14 +02:00
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Outstanding issues for 2.0 release:
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--------------------
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2008-10-07 06:53:25 +02:00
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1. Statistics cleanup
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2. Improve regression system
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3. Testing
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4. Validation
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2007-10-31 06:21:54 +01:00
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2008-02-26 23:28:31 +01:00
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March 1, 2008: m5_2.0_beta5
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--------------------
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New Features
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1. Rick Strong's Simpoints config changes
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2. Support for FSU ARM port
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3. EXTRAS= option allow architectures to be specified
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Bug fixes
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1. Bus timing more realistic
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2. Cache writeback, LL/SC fixes
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3. Minor IGbE NIC fixes
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4. O3 op latency fix
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5. SPARC TLB demap fixes
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6. SPARC SE memory layout fixes
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7. Variety of MIPS fixes
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2007-11-02 02:07:49 +01:00
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Nov 4, 2007: m5_2.0_beta4
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2007-10-31 06:21:54 +01:00
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New Features
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2007-11-02 02:07:49 +01:00
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1. New cache model
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2. Use of a I/O cache between devices and memory
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3. Ability to include compiled code with EXTRAS=
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4. Python creation of params structures for initialization
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5. Ability to remotely debug in SE
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2007-10-31 06:21:54 +01:00
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Bug fixes:
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1. Fix SE serialization
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2. SPARC_FS booting with TimingSimpleCPU
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3. Rename cycles() to ticks()
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4. Various SPARC ISA fixes
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5. Draining code for checkpointing
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6. Various performance improvements
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2007-04-27 20:53:14 +02:00
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2007-11-02 02:07:49 +01:00
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Possible Incompatibilities:
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1. Real TLBs are now used in SE mode. This is more accurate however it could
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cause some problems if you've modified the way page handling is done in
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SE mode.
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2. There have been many changes to the way the SCons files work. SimObjects,
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sources files, and trace flags are all specified in the SConscript files.
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To see how to add your sources take a look at one of them.
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3. Python is now used to created the parameter structs that were created
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manually before. The parameters listed in a py file are turned into
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2007-11-02 02:18:08 +01:00
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a header file with the same name (e.g. BadDevice.py -> BadDevice.hh).
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With this change the structs can be populated automatically and the
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2007-11-02 02:07:49 +01:00
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ugly macros to define and create SimObjects at the bottem of source
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files are gone. The parameter structs also automatically inherit
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parameters from their parents.
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2007-05-17 04:09:18 +02:00
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May 16, 2007: m5_2.0_beta3
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2007-04-13 19:33:32 +02:00
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--------------------
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New Features
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1. Some support for SPARC full-system simulation
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2007-05-17 04:09:18 +02:00
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2. Reworking of trace facitities (parameter names changed, variadic macros
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removed)
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3. Scons script cleanups
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4. Some support for compiling with Intel CC
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2007-04-13 19:33:32 +02:00
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Bug fixes since beta 2:
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1. Many SPARC linux syscall emulation support fixes
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2. Multiprocessor linux boot using the detailed O3 CPU module
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2007-05-17 04:09:18 +02:00
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3. Workaround for DMA bug (final solution to be released with 2.0f)
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4. Simulator performance and memory leak fixes
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5. Fixed issue where console could stop printing in ALPHA_FS
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6. Fix issues with remote debugging
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7. Several compile fixes, including gcc 4.1
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8. Many other minor fixes and enhancements
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2006-11-28 22:02:13 +01:00
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Nov. 28, 2006: m5_2.0_beta2
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--------------------
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Bug fixes since beta 1:
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1. Many cache issues resolved
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2. Uni-coherence fixes in full-system
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3. LL/SC Support
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4. Draining/Switchover
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5. Functional Accesses
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6. Bus now has real timing
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2007-04-13 19:33:32 +02:00
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7. Single config file for all SpecCPU2000 benchmarks
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2006-11-28 22:02:13 +01:00
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8. Several other minor bug fixes and enhancements
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2006-08-25 21:17:25 +02:00
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Aug. 25, 2006: m5_2.0_beta patch 1
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--------------------
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Handful of minor bug fixes for m5_2.0_beta,
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along with a few new regression tests.
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2006-08-15 17:49:15 +02:00
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Aug. 15, 2006: m5_2.0_beta
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2006-06-29 22:52:47 +02:00
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--------------------
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Major update to M5 including:
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- New CPU model
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2006-08-15 00:15:53 +02:00
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- New memory system
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2006-06-29 22:52:47 +02:00
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- More extensive python integration
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- Preliminary syscall emulation support for MIPS and SPARC
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2006-08-15 17:49:15 +02:00
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This is a *beta* release, meaning that some features are not complete,
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and some features from M5 1.X aren't currently supported (e.g., MP
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coherence). We are working to address these limitations and hope to
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have a complete 2.0 release soon.
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2006-06-29 22:52:47 +02:00
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2005-10-06 19:59:05 +02:00
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Oct. 8, 2005: m5_1.1
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--------------------
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Update release for IOSCA workshop mini-tutorial. New features include:
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- Preliminary FreeBSD support
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- Integration of regression tests into scons build framework
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- Several bug fixes and better compatibility for Cygwin hosts
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- Major cleanup of Alpha system code (console, PAL, etc.) to make
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it easier for others to build/modify
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- Fixes to enable compilation under g++ 4.0
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- Numerous minor bug fixes
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June 10, 2005: m5_1.0_web
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-------------------------
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The 1.0 release posted on Sourceforge after the ISCA tutorial contains
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just a few very minor fixes relative to the CD.
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June 5, 2005: m5_1.0_tutorial
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-----------------------------
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First non-beta release. This release was on the CD distributed at the
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ISCA tutorial. Major enhancements relative to beta releases include
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Linux support and Python-based configuration language.
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June 17, 2004: m5_1.0_beta2
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---------------------------
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Stealth-mode beta bug-fix update, not widely advertised.
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Oct. 17, 2003: m5_1.0_beta1
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---------------------------
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Early beta release.
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