system.cpu.iew.wb_sent 322610085 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 319598124 # cumulative count of insts written-back
system.cpu.iew.wb_producers 256503247 # num instructions producing a value
system.cpu.iew.wb_consumers 435667509 # num instructions consuming a value
system.cpu.iew.wb_rate 1.546580 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.588759 # average fanout of values written-back
system.cpu.commit.commitSquashedInsts 269290512 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 1245 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 6746174 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 163890954 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.350675 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.933271 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 67206524 41.01% 41.01% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 54940140 33.52% 74.53% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 13261155 8.09% 82.62% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 10687834 6.52% 89.14% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 5446779 3.32% 92.47% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 3132108 1.91% 94.38% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 1092307 0.67% 95.04% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 1156922 0.71% 95.75% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 6967185 4.25% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 163890954 # Number of insts commited each cycle
system.cpu.commit.committedInsts 132071192 # Number of instructions committed
system.cpu.commit.committedOps 221363384 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 77165304 # Number of memory references committed
system.cpu.commit.loads 56649587 # Number of loads committed
system.cpu.commit.membars 0 # Number of memory barriers committed
system.cpu.commit.branches 12326938 # Number of branches committed
system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions.
system.cpu.commit.int_insts 219019985 # Number of committed integer instructions.
system.cpu.commit.function_calls 797818 # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass 1176721 0.53% 0.53% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu 134111832 60.58% 61.12% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult 772953 0.35% 61.47% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv 7031501 3.18% 64.64% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd 1105073 0.50% 65.14% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 65.14% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 65.14% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult 0 0.00% 65.14% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 65.14% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 65.14% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 65.14% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 65.14% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 65.14% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 65.14% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 65.14% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 65.14% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult 0 0.00% 65.14% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 65.14% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift 0 0.00% 65.14% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 65.14% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 65.14% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 65.14% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 65.14% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 65.14% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 65.14% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 65.14% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 65.14% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.14% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.14% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.14% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead 56649587 25.59% 90.73% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite 20515717 9.27% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 221363384 # Class of committed instruction
system.cpu.commit.bw_lim_events 6967185 # number cycles where commit BW limit reached
system.cpu.rob.rob_reads 647577665 # The number of ROB reads
system.cpu.rob.rob_writes 1024269930 # The number of ROB writes
system.cpu.timesIdled 2819 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 194767 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 132071192 # Number of Instructions Simulated
system.cpu.committedOps 221363384 # Number of Ops (including micro ops) Simulated
system.cpu.cpi 1.564674 # CPI: Cycles Per Instruction
system.cpu.cpi_total 1.564674 # CPI: Total CPI of All Threads
system.cpu.ipc 0.639111 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.639111 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 524516370 # number of integer regfile reads
system.cpu.int_regfile_writes 289029189 # number of integer regfile writes
system.cpu.fp_regfile_reads 4536413 # number of floating regfile reads
system.cpu.fp_regfile_writes 3331836 # number of floating regfile writes
system.cpu.cc_regfile_reads 107017358 # number of cc regfile reads
system.cpu.cc_regfile_writes 65774990 # number of cc regfile writes
system.cpu.misc_regfile_reads 176892429 # number of misc regfile reads
system.cpu.misc_regfile_writes 1689 # number of misc regfile writes
system.cpu.dcache.tags.replacements 72 # number of replacements
system.cpu.dcache.tags.tagsinuse 1525.498489 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 82766316 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 2113 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 39170.050166 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 1525.498489 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.372436 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.372436 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 2041 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 15 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 32 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 101 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3 409 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4 1484 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.498291 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 165539971 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 165539971 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 62251936 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 62251936 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 20513707 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 20513707 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 82765643 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 82765643 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 82765643 # number of overall hits
system.cpu.dcache.overall_hits::total 82765643 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 1262 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 1262 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 2024 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 2024 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 3286 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 3286 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 3286 # number of overall misses
system.cpu.dcache.overall_misses::total 3286 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 84231000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 84231000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 131983500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 131983500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 216214500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 216214500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 216214500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 216214500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 62253198 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 62253198 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 82768929 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 82768929 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 82768929 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 82768929 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000020 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.000020 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000099 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.000099 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.000040 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.000040 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.000040 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.000040 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66744.057052 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 66744.057052 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65209.239130 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 65209.239130 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 65798.691418 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 65798.691418 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 65798.691418 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 65798.691418 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 369 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 73 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 8 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 46.125000 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 36.500000 # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks 18 # number of writebacks
system.cpu.dcache.writebacks::total 18 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 661 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 661 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 7 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 7 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 668 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 668 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 668 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 668 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 601 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 601 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2017 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 2017 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 2618 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 2618 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 2618 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 2618 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 47710000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 47710000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 129636500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 129636500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 177346500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 177346500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 177346500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 177346500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000098 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000098 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.000032 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000032 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79384.359401 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79384.359401 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 64271.938523 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64271.938523 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 67741.214668 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 67741.214668 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67741.214668 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 67741.214668 # average overall mshr miss latency
system.cpu.icache.tags.replacements 6515 # number of replacements
system.cpu.icache.tags.tagsinuse 1663.291735 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 41248897 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 8499 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 4853.382398 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 1663.291735 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.812154 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.812154 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 1984 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 97 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 151 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 845 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 155 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 736 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.968750 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 82532972 # Number of tag accesses
system.cpu.icache.tags.data_accesses 82532972 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 41248897 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 41248897 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 41248897 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 41248897 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 41248897 # number of overall hits
system.cpu.icache.overall_hits::total 41248897 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 13089 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 13089 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 13089 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 13089 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 13089 # number of overall misses
system.cpu.icache.overall_misses::total 13089 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 485791000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 485791000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 485791000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 485791000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 485791000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 485791000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 41261986 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 41261986 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 41261986 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 41261986 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 41261986 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 41261986 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000317 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000317 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000317 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000317 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000317 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000317 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 37114.447246 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 37114.447246 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 37114.447246 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 37114.447246 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 37114.447246 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 37114.447246 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 2090 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 305 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 30 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs 69.666667 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets 305 # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks 6515 # number of writebacks
system.cpu.icache.writebacks::total 6515 # number of writebacks
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4088 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 4088 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 4088 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 4088 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 4088 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 4088 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 9001 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 9001 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 9001 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 9001 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 9001 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 9001 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 340708000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 340708000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 340708000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 340708000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 340708000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 340708000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000218 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000218 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000218 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000218 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000218 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000218 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37852.238640 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37852.238640 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37852.238640 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 37852.238640 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37852.238640 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 37852.238640 # average overall mshr miss latency
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 2796.844278 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 11471 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 4155 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 2.760770 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 4.971138 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2402.103394 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 389.769746 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.000152 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.073306 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.011895 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.085353 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 4155 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 151 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 992 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 147 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2824 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.126801 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 146881 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 146881 # Number of data accesses
system.cpu.l2cache.WritebackDirty_hits::writebacks 18 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 18 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 6469 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 6469 # number of WritebackClean hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data 5 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 5 # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 6 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 6 # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 4877 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 4877 # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 68 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 68 # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst 4877 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 74 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 4951 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 4877 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 74 # number of overall hits
system.cpu.l2cache.overall_hits::total 4951 # number of overall hits
system.cpu.l2cache.UpgradeReq_misses::cpu.data 500 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 500 # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 1507 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 1507 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3617 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 3617 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 532 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 532 # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst 3617 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 2039 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 5656 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 3617 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 2039 # number of overall misses
system.cpu.l2cache.overall_misses::total 5656 # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 112056000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 112056000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 275028000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 275028000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 45953000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 45953000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 275028000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 158009000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 433037000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 275028000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 158009000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 433037000 # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks 18 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total 18 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks 6469 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 6469 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 505 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 505 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1513 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 1513 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 8494 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 8494 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 600 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 600 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 8494 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 2113 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 10607 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 8494 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 2113 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 10607 # number of overall (read+write) accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.990099 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.990099 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.996034 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.996034 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.425830 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.425830 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.886667 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.886667 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.425830 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.964979 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.533233 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.425830 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.964979 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.533233 # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74357.000664 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74357.000664 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76037.600221 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76037.600221 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 86377.819549 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 86377.819549 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76037.600221 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77493.379107 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 76562.411598 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76037.600221 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77493.379107 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 76562.411598 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 500 # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total 500 # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1507 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 1507 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3617 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3617 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 532 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 532 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 3617 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 2039 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 5656 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3617 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 2039 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 5656 # number of overall MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 9503500 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 9503500 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 96986000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 96986000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 238858000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 238858000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 40633000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 40633000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 238858000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 137619000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 376477000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 238858000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 137619000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 376477000 # number of overall MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.990099 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.990099 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.996034 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.996034 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.425830 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.425830 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.886667 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.886667 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.425830 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964979 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.533233 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.425830 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964979 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.533233 # mshr miss rate for overall accesses
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19007 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19007 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64357.000664 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64357.000664 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66037.600221 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66037.600221 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76377.819549 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76377.819549 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66037.600221 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67493.379107 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66562.411598 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66037.600221 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67493.379107 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66562.411598 # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests 18206 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 7138 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 549 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadResp 9600 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 18 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 6515 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 54 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq 505 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp 505 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 1513 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 1513 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 9001 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 600 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 24009 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5308 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 29317 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 960512 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 136384 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 1096896 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 507 # Total snoops (count)