93 lines
2.5 KiB
C++
93 lines
2.5 KiB
C++
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/*
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* Copyright (c) 2014-2015 ARM Limited
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* All rights reserved
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* Authors: Andreas Sandberg
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*/
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#include "mali_midgard.hh"
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#include "regutils.hh"
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namespace NoMali {
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MaliMidgard::MaliMidgard(unsigned gpuType,
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unsigned major, unsigned minor, unsigned status)
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: MaliMidgard(GPU_ID_MAKE(gpuType, major, minor, status))
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{
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}
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MaliMidgard::MaliMidgard(uint32_t _gpuId)
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: GPU(gpuControl, jobControl, mmu),
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gpuControl(*this),
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jobControl(*this),
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mmu(*this),
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gpuId(_gpuId)
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{
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}
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MaliMidgard::~MaliMidgard()
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{
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}
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void
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MaliMidgard::setupControlIdRegisters(RegVector ®s)
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{
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regs[RegAddr(L2_FEATURES)] =
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(0x07 << 24) | // lg2 ext bus width
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(0x13 << 16) | // lg2 cache size
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(0x02 << 8) | // lg2 associativity
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(0x06); // lg2 line size
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regs[RegAddr(TILER_FEATURES)] =
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(0x8 << 8) | // Maximum no active hierarchy levels
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0x09; // lg2 bin size
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/* Coherent core group, but incoherent supergroup. 1 L2 slice. */
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regs[RegAddr(MEM_FEATURES)] = 0x1;
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regs[RegAddr(MMU_FEATURES)] = 0x2830;
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regs[RegAddr(AS_PRESENT)] = 0xff;
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regs[RegAddr(JS_PRESENT)] = 0x7;
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regs[RegAddr(JS0_FEATURES)] = 0x20e;
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regs[RegAddr(JS1_FEATURES)] = 0x1fe;
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regs[RegAddr(JS2_FEATURES)] = 0x7e;
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regs[RegAddr(TEXTURE_FEATURES_0)] = 0x00fe001e;
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regs[RegAddr(TEXTURE_FEATURES_1)] = 0xffff;
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regs[RegAddr(TEXTURE_FEATURES_2)] = 0x9f81ffff;
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regs[RegAddr(THREAD_MAX_THREADS)] = 0x100;
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regs[RegAddr(THREAD_MAX_WORKGROUP_SIZE)] = 0x100;
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regs[RegAddr(THREAD_MAX_BARRIER_SIZE)] = 0x100;
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regs[RegAddr(THREAD_FEATURES)] = 0x0a040400;
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regs.set64(RegAddr(SHADER_PRESENT_LO), 0xf);
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regs.set64(RegAddr(TILER_PRESENT_LO), 0x1);
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regs.set64(RegAddr(L2_PRESENT_LO), 0x1);
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}
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void
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MaliMidgard::GPUControlSpec::reset()
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{
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GPUControl::reset();
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regs[RegAddr(GPU_ID)] = midgard.gpuId;
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midgard.setupControlIdRegisters(regs);
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}
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};
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