gem5/build_opts/ARM

TARGET_ISA = 'arm'
CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,MinorCPU'
PROTOCOL = 'MI_example'
ARM: Boilerplate full-system code. --HG-- rename : src/arch/sparc/interrupts.hh => src/arch/arm/interrupts.hh rename : src/arch/sparc/kernel_stats.hh => src/arch/arm/kernel_stats.hh rename : src/arch/sparc/stacktrace.cc => src/arch/arm/stacktrace.cc rename : src/arch/sparc/system.cc => src/arch/arm/system.cc rename : src/arch/sparc/system.hh => src/arch/arm/system.hh rename : src/dev/sparc/T1000.py => src/dev/arm/Versatile.py rename : src/dev/sparc/t1000.cc => src/dev/arm/versatile.cc rename : src/dev/sparc/t1000.hh => src/dev/arm/versatile.hh 2009-11-18 01:02:08 +01:00			`TARGET_ISA = 'arm'`
cpu: `Minor' in-order CPU model This patch contains a new CPU model named `Minor'. Minor models a four stage in-order execution pipeline (fetch lines, decompose into macroops, decompose macroops into microops, execute). The model was developed to support the ARM ISA but should be fixable to support all the remaining gem5 ISAs. It currently also works for Alpha, and regressions are included for ARM and Alpha (including Linux boot). Documentation for the model can be found in src/doc/inside-minor.doxygen and its internal operations can be visualised using the Minorview tool utils/minorview.py. Minor was designed to be fairly simple and not to engage in a lot of instruction annotation. As such, it currently has very few gathered stats and may lack other gem5 features. Minor is faster than the o3 model. Sample results: Benchmark \| Stat host_seconds (s) ---------------+--------v--------v-------- (on ARM, opt) \| simple \| o3 \| minor \| timing \| timing \| timing ---------------+--------+--------+-------- 10.linux-boot \| 169 \| 1883 \| 1075 10.mcf \| 117 \| 967 \| 491 20.parser \| 668 \| 6315 \| 3146 30.eon \| 542 \| 3413 \| 2414 40.perlbmk \| 2339 \| 20905 \| 11532 50.vortex \| 122 \| 1094 \| 588 60.bzip2 \| 2045 \| 18061 \| 9662 70.twolf \| 207 \| 2736 \| 1036 2014-07-23 23:09:04 +02:00			`CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,MinorCPU'`
m5: Added PROTOCOL default for regress fix 2010-02-01 07:21:01 +01:00			`PROTOCOL = 'MI_example'`