71 lines
2.3 KiB
C++
71 lines
2.3 KiB
C++
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/*
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* Copyright (c) 2016, Dresden University of Technology (TU Dresden)
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
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* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Christian Menard
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*/
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#ifndef __GEM5_MASTER_TRANSACTOR_HH__
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#define __GEM5_MASTER_TRANSACTOR_HH__
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#include <tlm_utils/simple_target_socket.h>
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#include <systemc>
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#include <tlm>
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#include "sc_master_port.hh"
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#include "sim_control_if.hh"
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namespace Gem5SystemC
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{
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class Gem5MasterTransactor : public sc_core::sc_module
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{
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public:
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// module interface
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tlm_utils::simple_target_socket<SCMasterPort> socket;
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sc_core::sc_port<Gem5SimControlInterface> sim_control;
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private:
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std::string portName;
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public:
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SC_HAS_PROCESS(Gem5MasterTransactor);
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Gem5MasterTransactor(sc_core::sc_module_name name,
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const std::string& portName);
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void before_end_of_elaboration();
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};
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}
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#endif
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