gem5/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt

---------- Begin Simulation Statistics ----------
host_inst_rate                                   4413                       # Simulator instruction rate (inst/s)
host_mem_usage                                 204480                       # Number of bytes of host memory used
host_seconds                                     1.45                       # Real time elapsed on the host
host_tick_rate                               21040041                       # Simulator tick rate (ticks/s)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
sim_insts                                        6404                       # Number of instructions simulated
sim_seconds                                  0.000031                       # Number of seconds simulated
sim_ticks                                    30538000                       # Number of ticks simulated
system.cpu.AGEN-Unit.agens                       2050                       # Number of Address Generations
system.cpu.Branch-Predictor.BTBHitPct       29.967427                       # BTB Hit Percentage
system.cpu.Branch-Predictor.BTBHits                92                       # Number of BTB hits
system.cpu.Branch-Predictor.BTBLookups            307                       # Number of BTB lookups
system.cpu.Branch-Predictor.RASInCorrect            0                       # Number of incorrect RAS predictions.
system.cpu.Branch-Predictor.condIncorrect          529                       # Number of conditional branches incorrect
system.cpu.Branch-Predictor.condPredicted          750                       # Number of conditional branches predicted
system.cpu.Branch-Predictor.lookups              1051                       # Number of BP lookups
system.cpu.Branch-Predictor.predictedNotTaken          817                       # Number of Branches Predicted As Not Taken (False).
system.cpu.Branch-Predictor.predictedTaken          234                       # Number of Branches Predicted As Taken (True).
system.cpu.Branch-Predictor.usedRAS               124                       # Number of times the RAS was used to get a target.
system.cpu.Execution-Unit.executions             4354                       # Number of Instructions Executed.
system.cpu.Execution-Unit.mispredictPct     50.333016                       # Percentage of Incorrect Branches Predicts
system.cpu.Execution-Unit.mispredicted            529                       # Number of Branches Incorrectly Predicted
system.cpu.Execution-Unit.predicted               522                       # Number of Branches Incorrectly Predicted
system.cpu.Execution-Unit.predictedNotTakenIncorrect          523                       # Number of Branches Incorrectly Predicted As Not Taken).
system.cpu.Execution-Unit.predictedTakenIncorrect            6                       # Number of Branches Incorrectly Predicted As Taken.
system.cpu.Mult-Div-Unit.divides                    0                       # Number of Divide Operations Executed
system.cpu.Mult-Div-Unit.multiplies                 1                       # Number of Multipy Operations Executed
system.cpu.RegFile-Manager.regFileAccesses        12573                       # Number of Total Accesses (Read+Write) to the Register File
system.cpu.RegFile-Manager.regFileReads          7990                       # Number of Reads from Register File
system.cpu.RegFile-Manager.regFileWrites         4583                       # Number of Writes to Register File
system.cpu.RegFile-Manager.regForwards            311                       # Number of Registers Read Through Forwarding Logic
system.cpu.activity                         22.376672                       # Percentage of cycles cpu is active
system.cpu.comBranches                           1051                       # Number of Branches instructions committed
system.cpu.comFloats                                2                       # Number of Floating Point instructions committed
system.cpu.comInts                               3265                       # Number of Integer instructions committed
system.cpu.comLoads                              1185                       # Number of Load instructions committed
system.cpu.comNonSpec                              17                       # Number of Non-Speculative instructions committed
system.cpu.comNops                                 17                       # Number of Nop instructions committed
system.cpu.comStores                              865                       # Number of Store instructions committed
system.cpu.committedInsts                        6404                       # Number of Instructions Simulated (Per-Thread)
system.cpu.committedInsts_total                  6404                       # Number of Instructions Simulated (Total)
system.cpu.contextSwitches                          1                       # Number of context switches
system.cpu.cpi                               9.537320                       # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.cpi_total                         9.537320                       # CPI: Total CPI of All Threads
system.cpu.dcache.ReadReq_accesses               1185                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 56384.210526                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53384.210526                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits                   1090                       # number of ReadReq hits
system.cpu.dcache.ReadReq_miss_latency        5356500                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate          0.080169                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses                   95                       # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_miss_latency      5071500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate     0.080169                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses              95                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses               865                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 56068.493151                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53068.493151                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits                   792                       # number of WriteReq hits
system.cpu.dcache.WriteReq_miss_latency       4093000                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate         0.084393                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses                  73                       # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_miss_latency      3874000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate     0.084393                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses             73                       # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu.dcache.avg_refs                  11.202381                       # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.demand_accesses                2050                       # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 56247.023810                       # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 53247.023810                       # average overall mshr miss latency
system.cpu.dcache.demand_hits                    1882                       # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency         9449500                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate           0.081951                       # miss rate for demand accesses
system.cpu.dcache.demand_misses                   168                       # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency      8945500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate      0.081951                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses              168                       # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0                   0.025183                       # Average percentage of cache occupancy
system.cpu.dcache.occ_blocks::0            103.151125                       # Average occupied blocks per context
system.cpu.dcache.overall_accesses               2050                       # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 56247.023810                       # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 53247.023810                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits                   1882                       # number of overall hits
system.cpu.dcache.overall_miss_latency        9449500                       # number of overall miss cycles
system.cpu.dcache.overall_miss_rate          0.081951                       # miss rate for overall accesses
system.cpu.dcache.overall_misses                  168                       # number of overall misses
system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency      8945500                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate     0.081951                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses             168                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements                      0                       # number of replacements
system.cpu.dcache.sampled_refs                    168                       # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.tagsinuse                103.151125                       # Cycle average of tags in use
system.cpu.dcache.total_refs                     1882                       # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks                        0                       # number of writebacks
system.cpu.dtb.data_accesses                     2060                       # DTB accesses
system.cpu.dtb.data_acv                             0                       # DTB access violations
system.cpu.dtb.data_hits                         2050                       # DTB hits
system.cpu.dtb.data_misses                         10                       # DTB misses
system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
system.cpu.dtb.fetch_acv                            0                       # ITB acv
system.cpu.dtb.fetch_hits                           0                       # ITB hits
system.cpu.dtb.fetch_misses                         0                       # ITB misses
system.cpu.dtb.read_accesses                     1192                       # DTB read accesses
system.cpu.dtb.read_acv                             0                       # DTB read access violations
system.cpu.dtb.read_hits                         1185                       # DTB read hits
system.cpu.dtb.read_misses                          7                       # DTB read misses
system.cpu.dtb.write_accesses                     868                       # DTB write accesses
system.cpu.dtb.write_acv                            0                       # DTB write access violations
system.cpu.dtb.write_hits                         865                       # DTB write hits
system.cpu.dtb.write_misses                         3                       # DTB write misses
system.cpu.icache.ReadReq_accesses               7169                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 55703.071672                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 52873.684211                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits                   6876                       # number of ReadReq hits
system.cpu.icache.ReadReq_miss_latency       16321000                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate          0.040870                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses                  293                       # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits                 8                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency     15069000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate     0.039754                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses             285                       # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu.icache.avg_refs                  24.211268                       # Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.demand_accesses                7169                       # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency 55703.071672                       # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 52873.684211                       # average overall mshr miss latency
system.cpu.icache.demand_hits                    6876                       # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency        16321000                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate           0.040870                       # miss rate for demand accesses
system.cpu.icache.demand_misses                   293                       # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits                  8                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency     15069000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate      0.039754                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses              285                       # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.icache.occ_%::0                   0.063218                       # Average percentage of cache occupancy
system.cpu.icache.occ_blocks::0            129.469682                       # Average occupied blocks per context
system.cpu.icache.overall_accesses               7169                       # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 55703.071672                       # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 52873.684211                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.cpu.icache.overall_hits                   6876                       # number of overall hits
system.cpu.icache.overall_miss_latency       16321000                       # number of overall miss cycles
system.cpu.icache.overall_miss_rate          0.040870                       # miss rate for overall accesses
system.cpu.icache.overall_misses                  293                       # number of overall misses
system.cpu.icache.overall_mshr_hits                 8                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency     15069000                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate     0.039754                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses             285                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu.icache.replacements                      0                       # number of replacements
system.cpu.icache.sampled_refs                    284                       # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse                129.469682                       # Cycle average of tags in use
system.cpu.icache.total_refs                     6876                       # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks                        0                       # number of writebacks
system.cpu.idleCycles                           47410                       # Number of cycles cpu's stages were not processed
system.cpu.ipc                               0.104851                       # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.ipc_total                         0.104851                       # IPC: Total IPC of All Threads
system.cpu.itb.data_accesses                        0                       # DTB accesses
system.cpu.itb.data_acv                             0                       # DTB access violations
system.cpu.itb.data_hits                            0                       # DTB hits
system.cpu.itb.data_misses                          0                       # DTB misses
system.cpu.itb.fetch_accesses                    7186                       # ITB accesses
system.cpu.itb.fetch_acv                            0                       # ITB acv
system.cpu.itb.fetch_hits                        7169                       # ITB hits
system.cpu.itb.fetch_misses                        17                       # ITB misses
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.read_acv                             0                       # DTB read access violations
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.write_acv                            0                       # DTB write access violations
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.l2cache.ReadExReq_accesses              73                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 52068.493151                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40013.698630                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_miss_latency      3801000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate              1                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses                73                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency      2921000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate            1                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses           73                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses               380                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 52087.071240                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 39947.229551                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits                     1                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency      19741000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate         0.997368                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses                 379                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency     15140000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate     0.997368                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses            379                       # number of ReadReq MSHR misses
system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs                  0.002646                       # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.demand_accesses                453                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 52084.070796                       # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 39957.964602                       # average overall mshr miss latency
system.cpu.l2cache.demand_hits                      1                       # number of demand (read+write) hits
system.cpu.l2cache.demand_miss_latency       23542000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate          0.997792                       # miss rate for demand accesses
system.cpu.l2cache.demand_misses                  452                       # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency     18061000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate     0.997792                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses             452                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.l2cache.occ_%::0                  0.005668                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_blocks::0           185.735123                       # Average occupied blocks per context
system.cpu.l2cache.overall_accesses               453                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52084.070796                       # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 39957.964602                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits                     1                       # number of overall hits
system.cpu.l2cache.overall_miss_latency      23542000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate         0.997792                       # miss rate for overall accesses
system.cpu.l2cache.overall_misses                 452                       # number of overall misses
system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency     18061000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate     0.997792                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses            452                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements                     0                       # number of replacements
system.cpu.l2cache.sampled_refs                   378                       # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.tagsinuse               185.735123                       # Cycle average of tags in use
system.cpu.l2cache.total_refs                       1                       # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks                       0                       # number of writebacks
system.cpu.numCycles                            61077                       # number of cpu cycles simulated
system.cpu.runCycles                            13667                       # Number of cycles cpu stages are processed.
system.cpu.smtCommittedInsts                        0                       # Number of SMT Instructions Simulated (Per-Thread)
system.cpu.smtCycles                                0                       # Total number of cycles that the CPU was in SMT-mode
system.cpu.smt_cpi                           no_value                       # CPI: Total SMT-CPI
system.cpu.smt_ipc                           no_value                       # IPC: Total SMT-IPC
system.cpu.stage-0.idleCycles                   53891                       # Number of cycles 0 instructions are processed.
system.cpu.stage-0.runCycles                     7186                       # Number of cycles 1+ instructions are processed.
system.cpu.stage-0.utilization              11.765476                       # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage-1.idleCycles                   54525                       # Number of cycles 0 instructions are processed.
system.cpu.stage-1.runCycles                     6552                       # Number of cycles 1+ instructions are processed.
system.cpu.stage-1.utilization              10.727442                       # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage-2.idleCycles                   54607                       # Number of cycles 0 instructions are processed.
system.cpu.stage-2.runCycles                     6470                       # Number of cycles 1+ instructions are processed.
system.cpu.stage-2.utilization              10.593186                       # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage-3.idleCycles                   59024                       # Number of cycles 0 instructions are processed.
system.cpu.stage-3.runCycles                     2053                       # Number of cycles 1+ instructions are processed.
system.cpu.stage-3.utilization               3.361331                       # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage-4.idleCycles                   54673                       # Number of cycles 0 instructions are processed.
system.cpu.stage-4.runCycles                     6404                       # Number of cycles 1+ instructions are processed.
system.cpu.stage-4.utilization              10.485125                       # Percentage of cycles stage was utilized (processing insts).
system.cpu.threadCycles                         61077                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.workload.PROG:num_syscalls              17                       # Number of system calls

---------- End Simulation Statistics   ----------