2009-07-07 00:49:47 +02:00
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#ifndef DMASEQUENCER_H
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#define DMASEQUENCER_H
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#include <ostream>
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#include "mem/ruby/common/DataBlock.hh"
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#include "mem/ruby/system/RubyPort.hh"
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struct DMARequest {
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uint64_t start_paddr;
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int len;
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bool write;
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int bytes_completed;
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int bytes_issued;
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uint8* data;
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int64_t id;
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};
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class MessageBuffer;
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class AbstractController;
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class DMASequencer :public RubyPort {
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public:
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DMASequencer(const string & name);
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void init(const vector<string> & argv);
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/* external interface */
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int64_t makeRequest(const RubyRequest & request);
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2009-08-21 22:52:46 +02:00
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bool isReady(const RubyRequest & request, bool dont_set = false) { assert(0); return false;};
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2009-07-07 00:49:47 +02:00
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// void issueRequest(uint64_t paddr, uint8* data, int len, bool rw);
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bool busy() { return m_is_busy;}
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/* SLICC callback */
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void dataCallback(const DataBlock & dblk);
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void ackCallback();
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void printConfig(std::ostream & out);
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private:
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void issueNext();
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private:
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int m_version;
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AbstractController* m_controller;
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bool m_is_busy;
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2009-07-19 00:03:51 +02:00
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uint64_t m_data_block_mask;
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2009-07-07 00:49:47 +02:00
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DMARequest active_request;
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int num_active_requests;
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MessageBuffer* m_mandatory_q_ptr;
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};
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#endif // DMACONTROLLER_H
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