gem5/src/arch/alpha/isa.hh

/*
 * Copyright (c) 2009 The Regents of The University of Michigan
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
 * redistributions in binary form must reproduce the above copyright
 * notice, this list of conditions and the following disclaimer in the
 * documentation and/or other materials provided with the distribution;
 * neither the name of the copyright holders nor the names of its
 * contributors may be used to endorse or promote products derived from
 * this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 * Authors: Gabe Black
 */

#ifndef __ARCH_ALPHA_ISA_HH__
#define __ARCH_ALPHA_ISA_HH__

#include "arch/alpha/miscregfile.hh"
#include "arch/alpha/types.hh"

class Checkpoint;
class EventManager;

namespace AlphaISA
{
    class ISA
    {
      protected:
        MiscRegFile miscRegFile;

      public:

        void expandForMultithreading(ThreadID num_threads, unsigned num_vpes)
        {
            miscRegFile.expandForMultithreading(num_threads, num_vpes);
        }

        void reset(std::string core_name, ThreadID num_threads,
                unsigned num_vpes, BaseCPU *_cpu)
        {
            miscRegFile.reset(core_name, num_threads, num_vpes, _cpu);
        }

        int instAsid()
        {
            return miscRegFile.getInstAsid();
        }

        int dataAsid()
        {
            return miscRegFile.getDataAsid();
        }

        void clear();

        MiscReg readMiscRegNoEffect(int miscReg);
        MiscReg readMiscReg(int miscReg, ThreadContext *tc);

        void setMiscRegNoEffect(int miscReg, const MiscReg val);
        void setMiscReg(int miscReg, const MiscReg val,
                ThreadContext *tc);

        int
        flattenIntIndex(int reg)
        {
            return reg;
        }

        int
        flattenFloatIndex(int reg)
        {
            return reg;
        }

        void serialize(std::ostream &os);
        void unserialize(Checkpoint *cp, const std::string &section);

        ISA()
        {
            clear();
        }
    };
}

#endif