144 lines
4 KiB
C++
144 lines
4 KiB
C++
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#ifndef __CPU_O3_THREAD_STATE_HH__
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#define __CPU_O3_THREAD_STATE_HH__
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#include "arch/faults.hh"
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#include "arch/isa_traits.hh"
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#include "cpu/exec_context.hh"
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#include "cpu/thread_state.hh"
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class Event;
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class Process;
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#if FULL_SYSTEM
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class EndQuiesceEvent;
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class FunctionProfile;
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class ProfileNode;
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#else
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class Process;
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class FunctionalMemory;
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#endif
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// In the new CPU case this may be quite small...It depends on what I define
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// ThreadState to be. Currently it's only the state that exists within
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// ExecContext basically. Leaves the interface and manipulation up to the
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// CPU. Not sure this is useful/flexible...probably can be if I can avoid
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// including state here that parts of the pipeline can't modify directly,
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// or at least don't let them. The only problem is for state that's needed
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// per thread, per structure. I.e. rename table, memreqs.
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// On the other hand, it might be nice to not have to pay the extra pointer
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// lookup to get frequently used state such as a memreq (that isn't used much
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// elsewhere)...
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// Maybe this ozone thread state should only really have committed state?
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// I need to think about why I'm using this and what it's useful for. Clearly
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// has benefits for SMT; basically serves same use as CPUExecContext.
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// Makes the ExecContext proxy easier. Gives organization/central access point
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// to state of a thread that can be accessed normally (i.e. not in-flight
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// stuff within a OoO processor). Does this need an XC proxy within it?
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template <class Impl>
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struct O3ThreadState : public ThreadState {
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typedef ExecContext::Status Status;
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typedef typename Impl::FullCPU FullCPU;
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Status _status;
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// Current instruction?
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TheISA::MachInst inst;
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private:
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FullCPU *cpu;
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public:
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bool inSyscall;
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bool trapPending;
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#if FULL_SYSTEM
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O3ThreadState(FullCPU *_cpu, int _thread_num, FunctionalMemory *_mem)
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: ThreadState(-1, _thread_num, _mem),
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inSyscall(0), trapPending(0)
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{ }
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#else
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O3ThreadState(FullCPU *_cpu, int _thread_num, Process *_process, int _asid)
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: ThreadState(-1, _thread_num, NULL, _process, _asid),
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cpu(_cpu), inSyscall(0), trapPending(0)
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{ }
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O3ThreadState(FullCPU *_cpu, int _thread_num, FunctionalMemory *_mem,
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int _asid)
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: ThreadState(-1, _thread_num, _mem, NULL, _asid),
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cpu(_cpu), inSyscall(0), trapPending(0)
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{ }
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#endif
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ExecContext *xcProxy;
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ExecContext *getXCProxy() { return xcProxy; }
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Status status() const { return _status; }
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void setStatus(Status new_status) { _status = new_status; }
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#if !FULL_SYSTEM
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Fault dummyTranslation(MemReqPtr &req)
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{
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#if 0
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assert((req->vaddr >> 48 & 0xffff) == 0);
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#endif
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// put the asid in the upper 16 bits of the paddr
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req->paddr = req->vaddr & ~((Addr)0xffff << sizeof(Addr) * 8 - 16);
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req->paddr = req->paddr | (Addr)req->asid << sizeof(Addr) * 8 - 16;
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return NoFault;
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}
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Fault translateInstReq(MemReqPtr &req)
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{
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return dummyTranslation(req);
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}
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Fault translateDataReadReq(MemReqPtr &req)
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{
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return dummyTranslation(req);
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}
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Fault translateDataWriteReq(MemReqPtr &req)
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{
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return dummyTranslation(req);
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}
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bool validInstAddr(Addr addr)
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{ return process->validInstAddr(addr); }
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bool validDataAddr(Addr addr)
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{ return process->validDataAddr(addr); }
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#else
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Fault translateInstReq(MemReqPtr &req)
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{
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return cpu->itb->translate(req);
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}
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Fault translateDataReadReq(MemReqPtr &req)
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{
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return cpu->dtb->translate(req, false);
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}
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Fault translateDataWriteReq(MemReqPtr &req)
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{
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return cpu->dtb->translate(req, true);
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}
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#endif
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bool misspeculating() { return false; }
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void setInst(TheISA::MachInst _inst) { inst = _inst; }
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Counter readFuncExeInst() { return funcExeInst; }
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void setFuncExeInst(Counter new_val) { funcExeInst = new_val; }
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#if !FULL_SYSTEM
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void syscall() { process->syscall(xcProxy); }
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#endif
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};
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#endif // __CPU_O3_THREAD_STATE_HH__
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