124 lines
4.6 KiB
Python
124 lines
4.6 KiB
Python
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# Copyright (c) 2016, University of Kaiserslautern
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met:
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#
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# 1. Redistributions of source code must retain the above copyright notice,
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# this list of conditions and the following disclaimer.
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#
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# 2. Redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution.
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#
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# 3. Neither the name of the copyright holder nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
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# OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Matthias Jung
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import m5
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import optparse
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from m5.objects import *
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from m5.util import addToPath, fatal
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addToPath('../../configs/common/')
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from Caches import *
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# This configuration shows a simple setup of a Elastic Trace Player (eTraceCPU)
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# and an external TLM port for SystemC co-simulation.
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#
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# We assume a DRAM size of 512MB and L1 cache sizes of 32KB.
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#
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# Base System Architecture:
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#
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# +-----------+ ^
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# +-------------+ | eTraceCPU | |
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# | System Port | +-----+-----+ |
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# +------+------+ | $D1 | $I1 | |
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# | +--+--+--+--+ |
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# | | | | gem5 World
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# | | | | (see this file)
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# | | | |
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# +------v------------v-----v--+ |
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# | Membus | v
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# +----------------+-----------+ External Port (see sc_port.*)
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# | ^
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# +---v---+ | TLM World
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# | TLM | | (see sc_target.*)
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# +-------+ v
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#
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#
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# Create a system with a Crossbar and an Elastic Trace Player as CPU:
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# Setup System:
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system = System(cpu=TraceCPU(cpu_id=0),
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mem_mode='timing',
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mem_ranges = [AddrRange('512MB')],
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cache_line_size = 64)
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# Create a top-level voltage domain:
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system.voltage_domain = VoltageDomain()
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# Create a source clock for the system. This is used as the clock period for
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# xbar and memory:
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system.clk_domain = SrcClockDomain(clock = '1GHz',
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voltage_domain = system.voltage_domain)
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# Create a CPU voltage domain:
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system.cpu_voltage_domain = VoltageDomain()
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# Create a separate clock domain for the CPUs. In case of Trace CPUs this clock
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# is actually used only by the caches connected to the CPU:
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system.cpu_clk_domain = SrcClockDomain(clock = '1GHz',
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voltage_domain = system.cpu_voltage_domain)
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# Setup CPU and its L1 caches:
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system.cpu.createInterruptController()
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system.cpu.icache = L1_ICache(size="32kB")
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system.cpu.dcache = L1_DCache(size="32kB")
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system.cpu.icache.cpu_side = system.cpu.icache_port
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system.cpu.dcache.cpu_side = system.cpu.dcache_port
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# Assign input trace files to the eTraceCPU:
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system.cpu.instTraceFile="system.cpu.traceListener.inst.gz"
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system.cpu.dataTraceFile="system.cpu.traceListener.data.gz"
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# Setting up L1 BUS:
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system.membus = IOXBar(width = 16)
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system.physmem = SimpleMemory() # This must be instantiated, even if not needed
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# Create a external TLM port:
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system.tlm = ExternalSlave()
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system.tlm.addr_ranges = [AddrRange('512MB')]
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system.tlm.port_type = "tlm"
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system.tlm.port_data = "memory"
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# Connect everything:
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system.membus = SystemXBar()
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system.system_port = system.membus.slave
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system.cpu.icache.mem_side = system.membus.slave
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system.cpu.dcache.mem_side = system.membus.slave
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system.membus.master = system.tlm.port
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# Start the simulation:
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root = Root(full_system = False, system = system)
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root.system.mem_mode = 'timing'
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m5.instantiate()
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m5.simulate() #Simulation time specified later on commandline
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