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gem5/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt

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arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
---------- Begin Simulation Statistics ----------
sim_seconds 51.111167 # Number of seconds simulated
sim_ticks 51111167186000 # Number of ticks simulated
final_tick 51111167186000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1374172 # Simulator instruction rate (inst/s)
host_op_rate 1614949 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 71508211345 # Simulator tick rate (ticks/s)
host_mem_usage 650720 # Number of bytes of host memory used
host_seconds 714.76 # Real time elapsed on the host
sim_insts 982202425 # Number of instructions simulated
sim_ops 1154300154 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::realview.ide 441600 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.dtb.walker 674240 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 976256 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst 5095732 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 90778056 # Number of bytes read from this memory
system.physmem.bytes_read::total 97965884 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 5095732 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 5095732 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 65987904 # Number of bytes written to this memory
system.physmem.bytes_written::realview.ide 6826496 # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data 101336100 # Number of bytes written to this memory
system.physmem.bytes_written::total 174150500 # Number of bytes written to this memory
system.physmem.num_reads::realview.ide 6900 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.dtb.walker 10535 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 15254 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst 120028 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 1418420 # Number of read requests responded to by this memory
system.physmem.num_reads::total 1571137 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 1031061 # Number of write requests responded to by this memory
system.physmem.num_writes::realview.ide 106664 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data 1585628 # Number of write requests responded to by this memory
system.physmem.num_writes::total 2723353 # Number of write requests responded to by this memory
system.physmem.bw_read::realview.ide 8640 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.dtb.walker 13192 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 19101 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 99699 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 1776090 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 1916722 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 99699 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 99699 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1291066 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::realview.ide 133562 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 1982661 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 3407289 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1291066 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide 142202 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker 13192 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 19101 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 99699 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3758751 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 5324010 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bytes_read::cpu.inst 96 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst 96 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 96 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu.inst 24 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 29 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu.inst 2 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 3 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu.inst 2 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 2 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst 2 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s)
system.membus.trans_dist::ReadReq 581631 # Transaction distribution
system.membus.trans_dist::ReadResp 581631 # Transaction distribution
system.membus.trans_dist::WriteReq 33712 # Transaction distribution
system.membus.trans_dist::WriteResp 33712 # Transaction distribution
system.membus.trans_dist::Writeback 1031061 # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq 1689719 # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp 1689719 # Transaction distribution
system.membus.trans_dist::UpgradeReq 40041 # Transaction distribution
system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution
system.membus.trans_dist::UpgradeResp 40042 # Transaction distribution
system.membus.trans_dist::ReadExReq 1025075 # Transaction distribution
system.membus.trans_dist::ReadExResp 1025075 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122798 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6654 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7410875 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 7540385 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 231034 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 231034 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 7771419 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155928 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13308 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 264848480 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 265017848 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7392896 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 7392896 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 272410744 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 4290796 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::1 4290796 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 4290796 # Request fanout histogram
system.realview.ethernet.txBytes 966 # Bytes Transmitted
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.realview.ethernet.totBandwidth 151 # Total Bandwidth (bits/s)
system.realview.ethernet.totPackets 3 # Total Packets
system.realview.ethernet.totBytes 966 # Total Bytes
system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
system.realview.ethernet.txBandwidth 151 # Transmit Bandwidth (bits/s)
system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 1669 # Number of DMA write transactions.
system.iobus.trans_dist::ReadReq 40295 # Transaction distribution
system.iobus.trans_dist::ReadResp 40295 # Transaction distribution
system.iobus.trans_dist::WriteReq 136621 # Transaction distribution
system.iobus.trans_dist::WriteResp 29957 # Transaction distribution
system.iobus.trans_dist::WriteInvalidateResp 106664 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47916 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total 122798 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230954 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total 230954 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 353832 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47936 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total 155928 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334248 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total 7334248 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total 7492262 # Cumulative packet size per connected master and slave (bytes)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 183545113 # DTB read hits
system.cpu.dtb.read_misses 195347 # DTB read misses
system.cpu.dtb.write_hits 167775000 # DTB write hits
system.cpu.dtb.write_misses 71236 # DTB write misses
system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 49771 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 1139 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 82503 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 9078 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 21651 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 183740460 # DTB read accesses
system.cpu.dtb.write_accesses 167846236 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 351320113 # DTB hits
system.cpu.dtb.misses 266583 # DTB misses
system.cpu.dtb.accesses 351586696 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.itb.inst_hits 982679430 # ITB inst hits
system.cpu.itb.inst_misses 126834 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 11 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 49771 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 1139 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 58073 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 982806264 # ITB inst accesses
system.cpu.itb.hits 982679430 # DTB hits
system.cpu.itb.misses 126834 # DTB misses
system.cpu.itb.accesses 982806264 # DTB accesses
system.cpu.numCycles 102222351148 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 982202425 # Number of instructions committed
system.cpu.committedOps 1154300154 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 1057881248 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 881349 # Number of float alu accesses
system.cpu.num_func_calls 56834159 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 151623535 # number of instructions that are conditional controls
system.cpu.num_int_insts 1057881248 # number of integer instructions
system.cpu.num_fp_insts 881349 # number of float instructions
system.cpu.num_int_register_reads 1560758600 # number of times the integer registers were read
system.cpu.num_int_register_writes 840516230 # number of times the integer registers were written
system.cpu.num_fp_register_reads 1419767 # number of times the floating registers were read
system.cpu.num_fp_register_writes 748560 # number of times the floating registers were written
system.cpu.num_cc_register_reads 264018450 # number of times the CC registers were read
system.cpu.num_cc_register_writes 263440675 # number of times the CC registers were written
system.cpu.num_mem_refs 351539543 # number of memory refs
system.cpu.num_load_insts 183712417 # Number of load instructions
system.cpu.num_store_insts 167827126 # Number of store instructions
system.cpu.num_idle_cycles 101067404227.616409 # Number of idle cycles
system.cpu.num_busy_cycles 1154946920.383593 # Number of busy cycles
system.cpu.not_idle_fraction 0.011298 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.988702 # Percentage of idle cycles
system.cpu.Branches 219533477 # Number of branches fetched
system.cpu.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction
system.cpu.op_class::IntAlu 800832645 69.34% 69.34% # Class of executed instruction
system.cpu.op_class::IntMult 2354384 0.20% 69.54% # Class of executed instruction
system.cpu.op_class::IntDiv 100543 0.01% 69.55% # Class of executed instruction
system.cpu.op_class::FloatAdd 0 0.00% 69.55% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 69.55% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 69.55% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 69.55% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 69.55% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 69.55% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 69.55% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 69.55% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 69.55% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 69.55% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 69.55% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 69.55% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 69.55% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 69.55% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 69.55% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 69.55% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 69.55% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 8 0.00% 69.55% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 69.55% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 13 0.00% 69.55% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 21 0.00% 69.55% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 69.55% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 107822 0.01% 69.56% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 69.56% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 69.56% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 69.56% # Class of executed instruction
system.cpu.op_class::MemRead 183712417 15.91% 85.47% # Class of executed instruction
system.cpu.op_class::MemWrite 167827126 14.53% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 1154934980 # Class of executed instruction
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 16775 # number of quiesce instructions executed
system.cpu.icache.tags.replacements 14265263 # number of replacements
system.cpu.icache.tags.tagsinuse 511.984599 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 968528346 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 14265775 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 67.891744 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 6061930000 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 511.984599 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.999970 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.999970 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 184 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 239 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 89 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 997059906 # Number of tag accesses
system.cpu.icache.tags.data_accesses 997059906 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 968528346 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 968528346 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 968528346 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 968528346 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 968528346 # number of overall hits
system.cpu.icache.overall_hits::total 968528346 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 14265780 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 14265780 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 14265780 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 14265780 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 14265780 # number of overall misses
system.cpu.icache.overall_misses::total 14265780 # number of overall misses
system.cpu.icache.ReadReq_accesses::cpu.inst 982794126 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 982794126 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 982794126 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 982794126 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 982794126 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 982794126 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014516 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.014516 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.014516 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.014516 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.014516 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.014516 # miss rate for overall accesses
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 1249729 # number of replacements
system.cpu.l2cache.tags.tagsinuse 64613.042707 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 29358469 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 1311519 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 22.385089 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 13800320247500 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 36056.727460 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 328.031175 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 484.456162 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 6427.999826 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 21315.828084 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.550182 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.005005 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.007392 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.098083 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.325254 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.985917 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1023 450 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024 61340 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1023::0 2 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1023::1 4 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1023::2 5 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1023::4 439 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 314 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2192 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4810 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 53977 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1023 0.006866 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.935974 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 283403664 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 283403664 # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 505204 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 246769 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.inst 14188853 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 7449612 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 22390438 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 7859784 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 7859784 # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data 11730 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 11730 # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 1491359 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 1491359 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker 505204 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker 246769 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst 14188853 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 8940971 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 23881797 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker 505204 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker 246769 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst 14188853 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 8940971 # number of overall hits
system.cpu.l2cache.overall_hits::total 23881797 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 10535 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 15254 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.inst 76927 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 393333 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 496049 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data 39478 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 39478 # number of UpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 1 # number of SCUpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 1025635 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 1025635 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker 10535 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker 15254 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst 76927 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 1418968 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 1521684 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker 10535 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker 15254 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst 76927 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 1418968 # number of overall misses
system.cpu.l2cache.overall_misses::total 1521684 # number of overall misses
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 515739 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 262023 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.inst 14265780 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 7842945 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 22886487 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 7859784 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 7859784 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 51208 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 51208 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 1 # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::total 1 # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 2516994 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 2516994 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 515739 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker 262023 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst 14265780 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 10359939 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 25403481 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 515739 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker 262023 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 14265780 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 10359939 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 25403481 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.020427 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.058216 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.005392 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.050151 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.021674 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.770934 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.770934 # miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.407484 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.407484 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.020427 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.058216 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005392 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.136967 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.059901 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.020427 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.058216 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005392 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.136967 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.059901 # miss rate for overall accesses
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 1031061 # number of writebacks
system.cpu.l2cache.writebacks::total 1031061 # number of writebacks
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements 11606184 # number of replacements
system.cpu.dcache.tags.tagsinuse 511.999719 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 339855980 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 11606696 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 29.281027 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 511.999719 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 199 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 297 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 16 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 1417457465 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 1417457465 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 171111123 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 171111123 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 159073587 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 159073587 # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data 424480 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 424480 # number of SoftPFReq hits
system.cpu.dcache.WriteInvalidateReq_hits::cpu.data 1583055 # number of WriteInvalidateReq hits
system.cpu.dcache.WriteInvalidateReq_hits::total 1583055 # number of WriteInvalidateReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 4303648 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 4303648 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 4555648 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 4555648 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 330184710 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 330184710 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 330609190 # number of overall hits
system.cpu.dcache.overall_hits::total 330609190 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 6002953 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 6002953 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 2568202 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 2568202 # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data 1586188 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 1586188 # number of SoftPFReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 253804 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 253804 # number of LoadLockedReq misses
system.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses
system.cpu.dcache.demand_misses::cpu.data 8571155 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 8571155 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 10157343 # number of overall misses
system.cpu.dcache.overall_misses::total 10157343 # number of overall misses
system.cpu.dcache.ReadReq_accesses::cpu.data 177114076 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 177114076 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 161641789 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 161641789 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data 2010668 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 2010668 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.WriteInvalidateReq_accesses::cpu.data 1583055 # number of WriteInvalidateReq accesses(hits+misses)
system.cpu.dcache.WriteInvalidateReq_accesses::total 1583055 # number of WriteInvalidateReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4557452 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 4557452 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 4555649 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 4555649 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 338755865 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 338755865 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 340766533 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 340766533 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.033893 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.033893 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015888 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.015888 # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.788886 # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total 0.788886 # miss rate for SoftPFReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.055690 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.055690 # miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000000 # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.025302 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.025302 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.029807 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.029807 # miss rate for overall accesses
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 1583055 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 7859784 # number of writebacks
system.cpu.dcache.writebacks::total 7859784 # number of writebacks
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq 23338761 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 23338761 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq 33712 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp 33712 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 7859784 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1583055 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteInvalidateResp 1583055 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq 51208 # Transaction distribution
system.cpu.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp 51209 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 2516994 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 2516994 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 28617810 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 31982828 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 758208 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1548400 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 62907246 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 913182420 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1267567780 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 3032832 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6193600 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 2189976632 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 116124 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 35388588 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 5.003264 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.057040 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::5 35273071 99.67% 99.67% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::6 115517 0.33% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 35388588 # Request fanout histogram
system.iocache.tags.replacements 115459 # number of replacements
system.iocache.tags.tagsinuse 10.407111 # Cycle average of tags in use
system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 115475 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle 13082113302009 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet 3.554597 # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide 6.852514 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet 0.222162 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide 0.428282 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.650444 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses 1039650 # Number of tag accesses
system.iocache.tags.data_accesses 1039650 # Number of data accesses
system.iocache.WriteInvalidateReq_hits::realview.ide 106664 # number of WriteInvalidateReq hits
system.iocache.WriteInvalidateReq_hits::total 106664 # number of WriteInvalidateReq hits
system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
system.iocache.ReadReq_misses::realview.ide 8813 # number of ReadReq misses
system.iocache.ReadReq_misses::total 8850 # number of ReadReq misses
system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
system.iocache.demand_misses::realview.ide 8813 # number of demand (read+write) misses
system.iocache.demand_misses::total 8853 # number of demand (read+write) misses
system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
system.iocache.overall_misses::realview.ide 8813 # number of overall misses
system.iocache.overall_misses::total 8853 # number of overall misses
system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::realview.ide 8813 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 8850 # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::realview.ide 106664 # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::total 106664 # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
system.iocache.demand_accesses::realview.ide 8813 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 8853 # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
system.iocache.overall_accesses::realview.ide 8813 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 8853 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 106664 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
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