69 lines
3.5 KiB
Python
69 lines
3.5 KiB
Python
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# Copyright (c) 2013-2014 ARM Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Vasileios Spiliopoulos
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# Akash Bagdia
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from m5.params import *
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from m5.SimObject import SimObject
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from m5.proxy import *
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# The handler in its current form is design to be centeralized, one per system
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# and manages all the source clock domains (SrcClockDomain) it is configured to
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# handle. The specific voltage and frequency points are configured per clock
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# and voltage domain.
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class DVFSHandler(SimObject):
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type = 'DVFSHandler'
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cxx_header = "sim/dvfs_handler.hh"
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# List of controllable clock domains which in turn reference the appropriate
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# voltage domains
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domains = VectorParam.SrcClockDomain([], "list of domains")
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# System domain (its clock and voltage) is not controllable
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sys_clk_domain = Param.SrcClockDomain(Parent.clk_domain,
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"Clk domain in which the handler is instantiated")
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enable = Param.Bool(False, "Enable/Disable the handler")
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# The transition latency depends on how much time the PLLs and voltage
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# regualators takes to migrate from current levels to the new level, is
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# usally variable and hardware implementation dependent. In order to
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# accomodate this effect with ease, we provide a fixed transition latency
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# associated with all migrations. Configure this to maximum latency that
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# the hardware will take to migratate between any two perforamnce levels.
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transition_latency = Param.Latency('100us',
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"fixed latency for perf level migration")
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