72 lines
3.5 KiB
ArmAsm
72 lines
3.5 KiB
ArmAsm
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/*
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* Copyright (c) 2010 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Ali Saidi
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*/
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/*************************************************************************
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* Super simple bootloader
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* Preserve loaded values that we need to pass to the kernel (r0, r1, r2)
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* Additionally M5 puts the kernel start address in r3
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*
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* Upon executing this code:
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* r0 = 0, r1 = machine number, r2 = atags ptr
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* r3 = kernel start address
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*
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* CPU 0 should branch to the kernel start address and it's done with
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* the boot loader. Other CPUs need to start in a wfi loop. When CPU0 sends
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* an IPI the slave CPUs reads a register which CPU0 has programmed with the
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* boot address for the secondary cpu
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**************************************************************************/
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.text
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.globl _start
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.extern main
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_start:
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_entry:
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mrc p15, 0, r4, c0, c0, 5 // get the MPIDR register
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uxtb r4, r4 // isolate the lower 8 bits (affinity lvl 1)
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adds r4, r4, #0 // set flags for branch
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bxeq r3 // if it's 0 (CPU 0), branch to kernel
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pen:
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wfi // otherwise wait for an interrupt
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mov r4, #0x30 // Build address of the system controller
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movt r4, #0x1000 // flag register r4 = 0x10000030
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ldr r5, [r4] // load the value
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movs r5, r5 // set the flags on this value
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beq pen // if it's zero try again
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bx r5 // Jump to where we've been told
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bkpt // We should never get here
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