158 lines
5.9 KiB
C++
158 lines
5.9 KiB
C++
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/*
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* Copyright (c) 2014 Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Alexandru Dutu
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*/
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/**
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* @file
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* Declaration of a multi-level page table.
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*/
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#ifndef __MEM_MULTI_LEVEL_PAGE_TABLE_HH__
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#define __MEM_MULTI_LEVEL_PAGE_TABLE_HH__
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#include <string>
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#include "arch/isa_traits.hh"
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#include "arch/tlb.hh"
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#include "base/types.hh"
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#include "config/the_isa.hh"
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#include "mem/page_table.hh"
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#include "sim/serialize.hh"
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#include "sim/system.hh"
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/**
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* This class implements an in-memory multi-level page table that can be
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* configured to follow ISA specifications. It can be used instead of the
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* PageTable class in SE mode to allow CPU models (e.g. X86KvmCPU)
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* to do a normal page table walk.
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*
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* To reduce memory required to store the page table, a multi-level page
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* table stores its translations similarly with a radix tree. Let n be
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* the number of levels and {Ln, Ln-1, ..., L1, L0} a set that specifies
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* the number of entries for each level as base 2 logarithm values. A
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* multi-level page table will store its translations at level 0 (the
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* leaves of the tree) and it will be layed out in memory in the
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* following way:
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*
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* +------------------------------+
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* level n |Ln-1_E0|Ln-1_E1|...|Ln-1_E2^Ln|
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* +------------------------------+
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* / \
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* +------------------------+ +------------------------+
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* level n-1 |Ln-2_E0|...|Ln-2_E2^Ln-1| |Ln-2_E0|...|Ln-2_E2^Ln-1|
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* +------------------------+ +------------------------+
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* / \ / \
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* .
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* .
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* .
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* / / \
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* +------------------+ +------------+ +------------+
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* level 1 |L0_E1|...|L0_E2^L1| |...|L0_E2^L1| ... |...|L0_E2^L1|
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* +------------------+ +------------+ +------------+
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* , where
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* +------------------------------+
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* |Lk-1_E0|Lk-1_E1|...|Lk-1_E2^Lk|
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* +------------------------------+
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* is a level k entry that holds 2^Lk entries in Lk-1 level.
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*
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* Essentially, a level n entry will contain 2^Ln level n-1 entries,
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* a level n-1 entry will hold 2^Ln-1 level n-2 entries etc.
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*
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* The virtual address is split into offsets that index into the
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* different levels of the page table.
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*
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* +--------------------------------+
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* |LnOffset|...|L1Offset|PageOffset|
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* +--------------------------------+
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*
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* For example L0Offset will be formed by the bits in range
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* [log2(PageOffset), log2(PageOffset)+L0].
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*
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* For every level of the page table, from n to 1, the base address
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* of the entry is loaded, the offset in the virtual address for
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* that particular level is used to index into the entry which
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* will reveal the memory address of the entry in the next level.
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*
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* @see MultiLevelPageTable
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*/
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template <class ISAOps>
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class MultiLevelPageTable : public PageTableBase
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{
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/**
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* ISA specific operations
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*/
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ISAOps pTableISAOps;
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/**
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* Pointer to System object
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*/
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System *system;
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/**
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* Physical address to the last level of the page table
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*/
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Addr basePtr;
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/**
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* Vector with sizes of all levels in base 2 logarithmic
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*/
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const std::vector<uint8_t> logLevelSize;
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/**
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* Number of levels contained by the page table
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*/
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const uint64_t numLevels;
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/**
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* Method for walking the page table
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*
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* @param vaddr Virtual address that is being looked-up
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* @param allocate Specifies whether memory should be allocated while
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* walking the page table
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* @return PTE_addr The address of the found PTE
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* @retval true if the page table walk has succeded, false otherwhise
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*/
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bool walk(Addr vaddr, bool allocate, Addr &PTE_addr);
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public:
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MultiLevelPageTable(const std::string &__name, uint64_t _pid, System *_sys);
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~MultiLevelPageTable();
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void initState(ThreadContext* tc);
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void map(Addr vaddr, Addr paddr, int64_t size, bool clobber = false);
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void remap(Addr vaddr, int64_t size, Addr new_vaddr);
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void unmap(Addr vaddr, int64_t size);
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bool isUnmapped(Addr vaddr, int64_t size);
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bool lookup(Addr vaddr, TheISA::TlbEntry &entry);
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void serialize(std::ostream &os);
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void unserialize(Checkpoint *cp, const std::string §ion);
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};
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#endif // __MEM_MULTI_LEVEL_PAGE_TABLE_HH__
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