2007-03-30 00:39:34 +02:00
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---------- Begin Simulation Statistics ----------
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2007-06-22 21:06:10 +02:00
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host_inst_rate 697152 # Simulator instruction rate (inst/s)
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host_mem_usage 155896 # Number of bytes of host memory used
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host_seconds 349.77 # Real time elapsed on the host
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host_tick_rate 1027373651 # Simulator tick rate (ticks/s)
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2007-03-30 00:39:34 +02:00
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sim_freq 1000000000000 # Frequency of simulated ticks
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2007-06-22 21:06:10 +02:00
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sim_insts 243840172 # Number of instructions simulated
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sim_seconds 0.359341 # Number of seconds simulated
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sim_ticks 359340764000 # Number of ticks simulated
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system.cpu.dcache.ReadReq_accesses 82219469 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_avg_miss_latency 12000.343864 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11000.343864 # average ReadReq mshr miss latency
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system.cpu.dcache.ReadReq_hits 81326673 # number of ReadReq hits
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system.cpu.dcache.ReadReq_miss_latency 10713859000 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_rate 0.010859 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_misses 892796 # number of ReadReq misses
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system.cpu.dcache.ReadReq_mshr_miss_latency 9821063000 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate 0.010859 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_misses 892796 # number of ReadReq MSHR misses
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system.cpu.dcache.SwapReq_accesses 3886 # number of SwapReq accesses(hits+misses)
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system.cpu.dcache.SwapReq_avg_miss_latency 12500 # average SwapReq miss latency
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system.cpu.dcache.SwapReq_avg_mshr_miss_latency 11500 # average SwapReq mshr miss latency
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system.cpu.dcache.SwapReq_hits 3882 # number of SwapReq hits
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system.cpu.dcache.SwapReq_miss_latency 50000 # number of SwapReq miss cycles
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system.cpu.dcache.SwapReq_miss_rate 0.001029 # miss rate for SwapReq accesses
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system.cpu.dcache.SwapReq_misses 4 # number of SwapReq misses
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system.cpu.dcache.SwapReq_mshr_miss_latency 46000 # number of SwapReq MSHR miss cycles
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system.cpu.dcache.SwapReq_mshr_miss_rate 0.001029 # mshr miss rate for SwapReq accesses
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system.cpu.dcache.SwapReq_mshr_misses 4 # number of SwapReq MSHR misses
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system.cpu.dcache.WriteReq_accesses 22901836 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_avg_miss_latency 12623.899964 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency 11623.899964 # average WriteReq mshr miss latency
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system.cpu.dcache.WriteReq_hits 22855133 # number of WriteReq hits
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system.cpu.dcache.WriteReq_miss_latency 589574000 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_rate 0.002039 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_misses 46703 # number of WriteReq misses
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system.cpu.dcache.WriteReq_mshr_miss_latency 542871000 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_rate 0.002039 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_misses 46703 # number of WriteReq MSHR misses
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2007-03-30 00:39:34 +02:00
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system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
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2007-06-22 21:06:10 +02:00
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system.cpu.dcache.avg_refs 110.894471 # Average number of references to valid blocks.
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2007-03-30 00:39:34 +02:00
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system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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2007-06-22 21:06:10 +02:00
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system.cpu.dcache.demand_accesses 105121305 # number of demand (read+write) accesses
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system.cpu.dcache.demand_avg_miss_latency 12031.341172 # average overall miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency 11031.341172 # average overall mshr miss latency
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system.cpu.dcache.demand_hits 104181806 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_latency 11303433000 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_rate 0.008937 # miss rate for demand accesses
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system.cpu.dcache.demand_misses 939499 # number of demand (read+write) misses
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2007-03-30 00:39:34 +02:00
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system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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2007-06-22 21:06:10 +02:00
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system.cpu.dcache.demand_mshr_miss_latency 10363934000 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_rate 0.008937 # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_misses 939499 # number of demand (read+write) MSHR misses
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2007-03-30 00:39:34 +02:00
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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2007-06-22 21:06:10 +02:00
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system.cpu.dcache.overall_accesses 105121305 # number of overall (read+write) accesses
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system.cpu.dcache.overall_avg_miss_latency 12031.341172 # average overall miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency 11031.341172 # average overall mshr miss latency
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2007-03-30 00:39:34 +02:00
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
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2007-06-22 21:06:10 +02:00
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system.cpu.dcache.overall_hits 104181806 # number of overall hits
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system.cpu.dcache.overall_miss_latency 11303433000 # number of overall miss cycles
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system.cpu.dcache.overall_miss_rate 0.008937 # miss rate for overall accesses
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system.cpu.dcache.overall_misses 939499 # number of overall misses
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2007-03-30 00:39:34 +02:00
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system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
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2007-06-22 21:06:10 +02:00
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system.cpu.dcache.overall_mshr_miss_latency 10363934000 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_rate 0.008937 # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_misses 939499 # number of overall MSHR misses
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2007-03-30 00:39:34 +02:00
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system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
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system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
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system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
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system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
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system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
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system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
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system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
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system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
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system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
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2007-06-22 21:06:10 +02:00
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system.cpu.dcache.replacements 935407 # number of replacements
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system.cpu.dcache.sampled_refs 939503 # Sample count of references to valid blocks.
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2007-03-30 00:39:34 +02:00
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system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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2007-06-22 21:06:10 +02:00
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system.cpu.dcache.tagsinuse 3560.887601 # Cycle average of tags in use
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system.cpu.dcache.total_refs 104185688 # Total number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 134116230000 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.writebacks 94807 # number of writebacks
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system.cpu.icache.ReadReq_accesses 243840173 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_avg_miss_latency 13993.174061 # average ReadReq miss latency
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system.cpu.icache.ReadReq_avg_mshr_miss_latency 12993.174061 # average ReadReq mshr miss latency
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system.cpu.icache.ReadReq_hits 243839294 # number of ReadReq hits
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system.cpu.icache.ReadReq_miss_latency 12300000 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_rate 0.000004 # miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_misses 879 # number of ReadReq misses
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system.cpu.icache.ReadReq_mshr_miss_latency 11421000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate 0.000004 # mshr miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_mshr_misses 879 # number of ReadReq MSHR misses
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2007-03-30 00:39:34 +02:00
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system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
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2007-06-22 21:06:10 +02:00
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system.cpu.icache.avg_refs 277405.340159 # Average number of references to valid blocks.
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2007-03-30 00:39:34 +02:00
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system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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2007-06-22 21:06:10 +02:00
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system.cpu.icache.demand_accesses 243840173 # number of demand (read+write) accesses
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system.cpu.icache.demand_avg_miss_latency 13993.174061 # average overall miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency 12993.174061 # average overall mshr miss latency
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system.cpu.icache.demand_hits 243839294 # number of demand (read+write) hits
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system.cpu.icache.demand_miss_latency 12300000 # number of demand (read+write) miss cycles
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system.cpu.icache.demand_miss_rate 0.000004 # miss rate for demand accesses
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system.cpu.icache.demand_misses 879 # number of demand (read+write) misses
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2007-03-30 00:39:34 +02:00
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system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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2007-06-22 21:06:10 +02:00
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system.cpu.icache.demand_mshr_miss_latency 11421000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_rate 0.000004 # mshr miss rate for demand accesses
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system.cpu.icache.demand_mshr_misses 879 # number of demand (read+write) MSHR misses
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2007-03-30 00:39:34 +02:00
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system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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2007-06-22 21:06:10 +02:00
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system.cpu.icache.overall_accesses 243840173 # number of overall (read+write) accesses
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system.cpu.icache.overall_avg_miss_latency 13993.174061 # average overall miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency 12993.174061 # average overall mshr miss latency
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2007-03-30 00:39:34 +02:00
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system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
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2007-06-22 21:06:10 +02:00
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system.cpu.icache.overall_hits 243839294 # number of overall hits
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system.cpu.icache.overall_miss_latency 12300000 # number of overall miss cycles
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system.cpu.icache.overall_miss_rate 0.000004 # miss rate for overall accesses
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system.cpu.icache.overall_misses 879 # number of overall misses
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2007-03-30 00:39:34 +02:00
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system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
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2007-06-22 21:06:10 +02:00
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system.cpu.icache.overall_mshr_miss_latency 11421000 # number of overall MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_rate 0.000004 # mshr miss rate for overall accesses
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system.cpu.icache.overall_mshr_misses 879 # number of overall MSHR misses
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2007-03-30 00:39:34 +02:00
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system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
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system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
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system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
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system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
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system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
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system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
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|
|
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system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
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|
|
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system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
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|
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system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
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2007-06-22 21:06:10 +02:00
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|
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system.cpu.icache.replacements 25 # number of replacements
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system.cpu.icache.sampled_refs 879 # Sample count of references to valid blocks.
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2007-03-30 00:39:34 +02:00
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|
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system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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2007-06-22 21:06:10 +02:00
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|
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system.cpu.icache.tagsinuse 716.200092 # Cycle average of tags in use
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|
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system.cpu.icache.total_refs 243839294 # Total number of references to valid blocks.
|
2007-03-30 00:39:34 +02:00
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|
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.writebacks 0 # number of writebacks
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system.cpu.idle_fraction 0 # Percentage of idle cycles
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2007-06-22 21:06:10 +02:00
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|
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system.cpu.l2cache.ReadReq_accesses 940381 # number of ReadReq accesses(hits+misses)
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|
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system.cpu.l2cache.ReadReq_avg_miss_latency 13000 # average ReadReq miss latency
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|
|
|
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system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency
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|
|
|
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system.cpu.l2cache.ReadReq_hits 924777 # number of ReadReq hits
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|
|
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system.cpu.l2cache.ReadReq_miss_latency 202852000 # number of ReadReq miss cycles
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|
|
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system.cpu.l2cache.ReadReq_miss_rate 0.016593 # miss rate for ReadReq accesses
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|
|
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system.cpu.l2cache.ReadReq_misses 15604 # number of ReadReq misses
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|
|
|
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system.cpu.l2cache.ReadReq_mshr_miss_latency 171644000 # number of ReadReq MSHR miss cycles
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|
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system.cpu.l2cache.ReadReq_mshr_miss_rate 0.016593 # mshr miss rate for ReadReq accesses
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|
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system.cpu.l2cache.ReadReq_mshr_misses 15604 # number of ReadReq MSHR misses
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system.cpu.l2cache.Writeback_accesses 94807 # number of Writeback accesses(hits+misses)
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system.cpu.l2cache.Writeback_hits 94807 # number of Writeback hits
|
2007-03-30 00:39:34 +02:00
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|
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system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
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|
|
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system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
2007-06-22 21:06:10 +02:00
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|
|
system.cpu.l2cache.avg_refs 65.341195 # Average number of references to valid blocks.
|
2007-03-30 00:39:34 +02:00
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|
|
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
|
|
|
|
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system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
|
|
|
|
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system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
|
|
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
2007-06-22 21:06:10 +02:00
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|
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system.cpu.l2cache.demand_accesses 940381 # number of demand (read+write) accesses
|
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system.cpu.l2cache.demand_avg_miss_latency 13000 # average overall miss latency
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|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency
|
|
|
|
|
system.cpu.l2cache.demand_hits 924777 # number of demand (read+write) hits
|
|
|
|
|
system.cpu.l2cache.demand_miss_latency 202852000 # number of demand (read+write) miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_miss_rate 0.016593 # miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_misses 15604 # number of demand (read+write) misses
|
2007-03-30 00:39:34 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
2007-06-22 21:06:10 +02:00
|
|
|
system.cpu.l2cache.demand_mshr_miss_latency 171644000 # number of demand (read+write) MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.demand_mshr_miss_rate 0.016593 # mshr miss rate for demand accesses
|
|
|
|
|
system.cpu.l2cache.demand_mshr_misses 15604 # number of demand (read+write) MSHR misses
|
2007-03-30 00:39:34 +02:00
|
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
|
|
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
|
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
2007-06-22 21:06:10 +02:00
|
|
|
system.cpu.l2cache.overall_accesses 1035188 # number of overall (read+write) accesses
|
|
|
|
|
system.cpu.l2cache.overall_avg_miss_latency 13000 # average overall miss latency
|
|
|
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency
|
2007-03-30 00:39:34 +02:00
|
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
2007-06-22 21:06:10 +02:00
|
|
|
system.cpu.l2cache.overall_hits 1019584 # number of overall hits
|
|
|
|
|
system.cpu.l2cache.overall_miss_latency 202852000 # number of overall miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_miss_rate 0.015074 # miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_misses 15604 # number of overall misses
|
2007-03-30 00:39:34 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
2007-06-22 21:06:10 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_miss_latency 171644000 # number of overall MSHR miss cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_miss_rate 0.015074 # mshr miss rate for overall accesses
|
|
|
|
|
system.cpu.l2cache.overall_mshr_misses 15604 # number of overall MSHR misses
|
2007-03-30 00:39:34 +02:00
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
|
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
|
|
|
|
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
2007-06-22 21:06:10 +02:00
|
|
|
system.cpu.l2cache.replacements 0 # number of replacements
|
|
|
|
|
system.cpu.l2cache.sampled_refs 15604 # Sample count of references to valid blocks.
|
2007-03-30 00:39:34 +02:00
|
|
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
2007-06-22 21:06:10 +02:00
|
|
|
system.cpu.l2cache.tagsinuse 10833.027960 # Cycle average of tags in use
|
|
|
|
|
system.cpu.l2cache.total_refs 1019584 # Total number of references to valid blocks.
|
|
|
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
|
|
|
system.cpu.l2cache.writebacks 0 # number of writebacks
|
2007-03-30 00:39:34 +02:00
|
|
|
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
2007-06-22 21:06:10 +02:00
|
|
|
system.cpu.numCycles 359340764000 # number of cpu cycles simulated
|
|
|
|
|
system.cpu.num_insts 243840172 # Number of instructions executed
|
|
|
|
|
system.cpu.num_refs 105125191 # Number of memory references
|
|
|
|
|
system.cpu.workload.PROG:num_syscalls 428 # Number of system calls
|
2007-03-30 00:39:34 +02:00
|
|
|
|
|
|
|
|
---------- End Simulation Statistics ----------
|
