104 lines
4.1 KiB
C++
104 lines
4.1 KiB
C++
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/*
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* Copyright N) 2007 MIPS Technologies, Inc. All Rights Reserved
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*
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* This software is part of the M5 simulator.
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*
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* THIS IS A LEGAL AGREEMENT. BY DOWNLOADING, USING, COPYING, CREATING
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* DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
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* TO THESE TERMS AND CONDITIONS.
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*
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* Permission is granted to use, copy, create derivative works and
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* distribute this software and such derivative works for any purpose,
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* so long as (1) the copyright notice above, this grant of permission,
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* and the disclaimer below appear in all copies and derivative works
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* made, (2) the copyright notice above is augmented as appropriate to
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* reflect the addition of any new copyrightable work in a derivative
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* work (e.g., Copyright N) <Publication Year> Copyright Owner), and (3)
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* the name of MIPS Technologies, Inc. ($(B!H(BMIPS$(B!I(B) is not used in any
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* advertising or publicity pertaining to the use or distribution of
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* this software without specific, written prior authorization.
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*
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* THIS SOFTWARE IS PROVIDED $(B!H(BAS IS.$(B!I(B MIPS MAKES NO WARRANTIES AND
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* DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
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* OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
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* NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
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* IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
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* INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
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* ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
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* THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
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* IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
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* STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
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* POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
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*
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* Authors: Jaidev Patwardhan
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*
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*/
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#ifndef __ARCH_MIPS_PAGETABLE_H__
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#define __ARCH_MIPS_PAGETABLE_H__
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#include "arch/mips/isa_traits.hh"
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#include "arch/mips/utility.hh"
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#include "config/full_system.hh"
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namespace MipsISA {
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struct VAddr
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{
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static const int ImplBits = 43;
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static const Addr ImplMask = (ULL(1) << ImplBits) - 1;
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static const Addr UnImplMask = ~ImplMask;
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VAddr(Addr a) : addr(a) {}
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Addr addr;
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operator Addr() const { return addr; }
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const VAddr &operator=(Addr a) { addr = a; return *this; }
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Addr vpn() const { return (addr & ImplMask) >> PageShift; }
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Addr page() const { return addr & Page_Mask; }
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Addr offset() const { return addr & PageOffset; }
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Addr level3() const
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{ return MipsISA::PteAddr(addr >> PageShift); }
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Addr level2() const
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{ return MipsISA::PteAddr(addr >> NPtePageShift + PageShift); }
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Addr level1() const
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{ return MipsISA::PteAddr(addr >> 2 * NPtePageShift + PageShift); }
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};
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// ITB/DTB page table entry
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struct PTE
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{
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Addr Mask; // What parts of the VAddr (from bits 28..11) should be used in translation (includes Mask and MaskX from PageMask)
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Addr VPN; // Virtual Page Number (/2) (Includes VPN2 + VPN2X .. bits 31..11 from EntryHi)
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uint8_t asid; // Address Space ID (8 bits) // Lower 8 bits of EntryHi
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bool G; // Global Bit - Obtained by an *AND* of EntryLo0 and EntryLo1 G bit
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/* Contents of Entry Lo0 */
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Addr PFN0; // Physical Frame Number - Even
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bool D0; // Even entry Dirty Bit
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bool V0; // Even entry Valid Bit
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uint8_t C0; // Cache Coherency Bits - Even
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/* Contents of Entry Lo1 */
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Addr PFN1; // Physical Frame Number - Odd
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bool D1; // Odd entry Dirty Bit
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bool V1; // Odd entry Valid Bit
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uint8_t C1; // Cache Coherency Bits (3 bits)
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/* The next few variables are put in as optimizations to reduce TLB lookup overheads */
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/* For a given Mask, what is the address shift amount, and what is the OffsetMask */
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int AddrShiftAmount;
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int OffsetMask;
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bool Valid() { return (V0 | V1);};
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void serialize(std::ostream &os);
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void unserialize(Checkpoint *cp, const std::string §ion);
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};
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};
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#endif // __ARCH_MIPS_PAGETABLE_H__
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