gem5/src/arch/mips/interrupts.hh

/*
 * Copyright N) 2007 MIPS Technologies, Inc.  All Rights Reserved
 *
 * This software is part of the M5 simulator.
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 * so long as (1) the copyright notice above, this grant of permission,
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 * made, (2) the copyright notice above is augmented as appropriate to
 * reflect the addition of any new copyrightable work in a derivative
 * work (e.g., Copyright N) <Publication Year> Copyright Owner), and (3)
 * the name of MIPS Technologies, Inc. ($(B!H(BMIPS$(B!I(B) is not used in any
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 * Authors: Richard Strong
 */

#ifndef __ARCH_MIPS_INTERRUPT_HH__
#define __ARCH_MIPS_INTERRUPT_HH__


#include "arch/mips/faults.hh"
#include "base/compiler.hh"



namespace MipsISA
{
class Interrupts
{
    /*
      protected:
      uint8_t intstatus;
      bool oncputimerintr;
      public:
      Interrupts()
      {
      intstatus = 0;
      newInfoSet = false;
      oncputimerintr = false;

      }
      //  post(int int_num, int index) is responsible
      //  for posting an interrupt. It sets a bit
      //  in intstatus corresponding to Cause IP*. The
      //  MIPS register Cause is updated by updateIntrInfo
      //  which is called by check_interrupts
      //
      void post(int int_num, int index);
      // clear(int int_num, int index) is responsible
      //  for clearing an interrupt. It clear a bit
      //  in intstatus corresponding to Cause IP*. The
      //  MIPS register Cause is updated by updateIntrInfo
      //  which is called by check_interrupts
      //
      void clear(int int_num, int index);
      //  clear_all() is responsible
      //  for clearing all interrupts. It clears all bits
      //  in intstatus corresponding to Cause IP*. The
      //  MIPS register Cause is updated by updateIntrInfo
      //  which is called by check_interrupts
      //
      void clear_all();

      // getInterrupt(ThreadContext * tc) checks if an interrupt
      //  should be returned. It ands the interrupt mask and
      //  and interrupt pending bits to see if one exists. It
      //  also makes sure interrupts are enabled (IE) and
      //  that ERL and ERX are not set
      //
      Fault getInterrupt(ThreadContext * tc);

      // updateIntrInfo(ThreadContext *tc) const syncs the
      //  MIPS cause register with the instatus variable. instatus
      //  is essentially a copy of the MIPS cause[IP7:IP0]
      //
      void updateIntrInfo(ThreadContext *tc) const;
      void updateIntrInfoCpuTimerIntr(ThreadContext *tc) const;
      bool onCpuTimerInterrupt(ThreadContext *tc) const;

      uint64_t get_vec(int int_num);

      bool check_interrupts(ThreadContext * tc) const{
      //return (intstatus != 0) && !(tc->readPC() & 0x3);
      if (oncputimerintr == false){
      updateIntrInfo(tc);
      return ((intstatus != 0) || onCpuTimerInterrupt(tc));
      }
      else
      return true;

      }
    */


  protected:
    //uint8_t intstatus;
    //bool oncputimerintr;
  public:
    Interrupts()
    {
        //intstatus = 0;
        newInfoSet = false;
        //oncputimerintr = false;

    }
    //  post(int int_num, int index) is responsible
    //  for posting an interrupt. It sets a bit
    //  in intstatus corresponding to Cause IP*. The
    //  MIPS register Cause is updated by updateIntrInfo
    //  which is called by check_interrupts
    //
    void post(int int_num, ThreadContext* tc);
    void post(int int_num, int index);

    // clear(int int_num, int index) is responsible
    //  for clearing an interrupt. It clear a bit
    //  in intstatus corresponding to Cause IP*. The
    //  MIPS register Cause is updated by updateIntrInfo
    //  which is called by check_interrupts
    //
    void clear(int int_num, ThreadContext* tc);
    void clear(int int_num, int index);

    //  clear_all() is responsible
    //  for clearing all interrupts. It clears all bits
    //  in intstatus corresponding to Cause IP*. The
    //  MIPS register Cause is updated by updateIntrInfo
    //  which is called by check_interrupts
    //
    void clear_all(ThreadContext* tc);
    void clear_all();

    // getInterrupt(ThreadContext * tc) checks if an interrupt
    //  should be returned. It ands the interrupt mask and
    //  and interrupt pending bits to see if one exists. It
    //  also makes sure interrupts are enabled (IE) and
    //  that ERL and ERX are not set
    //
    Fault getInterrupt(ThreadContext * tc);

    // updateIntrInfo(ThreadContext *tc) const syncs the
    //  MIPS cause register with the instatus variable. instatus
    //  is essentially a copy of the MIPS cause[IP7:IP0]
    //
    void updateIntrInfo(ThreadContext *tc) const;
    bool interruptsPending(ThreadContext *tc) const;
    bool onCpuTimerInterrupt(ThreadContext *tc) const;

    uint64_t get_vec(int int_num);

    bool check_interrupts(ThreadContext * tc) const{
        return interruptsPending(tc);
    }


    void serialize(std::ostream &os)
    {
        fatal("Serialization of Interrupts Unimplemented for MIPS");
        //SERIALIZE_ARRAY(interrupts, NumInterruptLevels);
        //SERIALIZE_SCALAR(intstatus);
    }

    void unserialize(Checkpoint *cp, const std::string &section)
    {
        fatal("Unserialization of Interrupts Unimplemented for MIPS");
        //UNSERIALIZE_ARRAY(interrupts, NumInterruptLevels);
        //UNSERIALIZE_SCALAR(intstatus);
    }



  private:
    bool newInfoSet;
    int newIpl;
    int newSummary;

};

}

#endif