76 lines
3.7 KiB
Protocol Buffer
76 lines
3.7 KiB
Protocol Buffer
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// Copyright (c) 2013 ARM Limited
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// All rights reserved
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//
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// The license below extends only to copyright in the software and shall
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// not be construed as granting a license to any other intellectual
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// property including but not limited to intellectual property relating
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// to a hardware implementation of the functionality of the software
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// licensed hereunder. You may use the software subject to the license
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// terms below provided that you ensure that this notice is replicated
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// unmodified and in its entirety in all distributions of the software,
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// modified or unmodified, in source code or in binary form.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met: redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer;
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// redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution;
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// neither the name of the copyright holders nor the names of its
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// Authors: Radhika Jagtap
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// Put all the generated messages in a namespace
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package ProtoMessage;
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// Packet header for the o3cpu data dependency trace. The header fields are the
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// identifier describing what object captured the trace, the version of this
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// file format, the tick frequency of the object and the window size used to
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// limit the register dependencies during capture.
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message InstDepRecordHeader {
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required string obj_id = 1;
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optional uint32 ver = 2 [default = 0];
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required uint64 tick_freq = 3;
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required uint32 window_size = 4;
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}
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// Packet to encapsulate an instruction in the o3cpu data dependency trace.
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// The required fields include the instruction sequence number, whether it
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// is a load, and whether it is a store. The request related fields are
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// optional, namely address, size and flags. These exist only if the
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// instruction is a load or store. The dependency related information includes
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// a repeated field for order dependencies, a repeated field for register
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// dependencies and the computational delay with respect to the dependency
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// that completed last. A weight field is used to account for committed
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// instructions that were filtered out before writing the trace and is used
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// to estimate ROB occupancy during replay. An optional field is provided for
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// the instruction PC.
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message InstDepRecord {
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required uint64 seq_num = 1;
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required bool load = 2;
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required bool store = 3;
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optional uint64 addr = 4;
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optional uint32 size = 5;
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optional uint32 flags = 6;
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repeated uint64 rob_dep = 7;
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required uint64 comp_delay = 8;
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repeated uint64 reg_dep = 9;
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optional uint32 weight = 10;
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optional uint64 pc = 11;
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}
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