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gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt

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arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
---------- Begin Simulation Statistics ----------
sim_seconds 51.316753 # Number of seconds simulated
sim_ticks 51316753294500 # Number of ticks simulated
final_tick 51316753294500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 136598 # Simulator instruction rate (inst/s)
host_op_rate 160520 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 7792719388 # Simulator tick rate (ticks/s)
host_mem_usage 670460 # Number of bytes of host memory used
host_seconds 6585.22 # Real time elapsed on the host
sim_insts 899526584 # Number of instructions simulated
sim_ops 1057057755 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::realview.ide 436032 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.dtb.walker 324288 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 511488 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst 3575488 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 35714136 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 305664 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker 479488 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 3431104 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 34340592 # Number of bytes read from this memory
system.physmem.bytes_read::total 79118280 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 3575488 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 3431104 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 7006592 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 46041344 # Number of bytes written to this memory
system.physmem.bytes_written::realview.ide 6826496 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 50417380 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 49769472 # Number of bytes written to this memory
system.physmem.bytes_written::total 153054692 # Number of bytes written to this memory
system.physmem.num_reads::realview.ide 6813 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.dtb.walker 5067 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 7992 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst 55867 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 558041 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 4776 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker 7492 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 53611 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 536577 # Number of read requests responded to by this memory
system.physmem.num_reads::total 1236236 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 719396 # Number of write requests responded to by this memory
system.physmem.num_writes::realview.ide 106664 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 790023 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 777648 # Number of write requests responded to by this memory
system.physmem.num_writes::total 2393731 # Number of write requests responded to by this memory
system.physmem.bw_read::realview.ide 8497 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.dtb.walker 6319 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 9967 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst 69675 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 695955 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 5956 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker 9344 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 66861 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 669189 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 1541763 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 69675 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 66861 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 136536 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 897199 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::realview.ide 133027 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data 982474 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data 969848 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 2982548 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 897199 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide 141524 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 6319 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 9967 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 69675 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 1678429 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 5956 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker 9344 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 66861 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 1639037 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 4524311 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 1236236 # Number of read requests accepted
system.physmem.writeReqs 2393731 # Number of write requests accepted
system.physmem.readBursts 1236236 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 2393731 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 78915968 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 203136 # Total number of bytes read from write queue
system.physmem.bytesWritten 148972800 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 79118280 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 153054692 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 3174 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 66016 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 38473 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 78969 # Per bank write bursts
system.physmem.perBankRdBursts::1 76054 # Per bank write bursts
system.physmem.perBankRdBursts::2 70113 # Per bank write bursts
system.physmem.perBankRdBursts::3 71416 # Per bank write bursts
system.physmem.perBankRdBursts::4 73251 # Per bank write bursts
system.physmem.perBankRdBursts::5 79391 # Per bank write bursts
system.physmem.perBankRdBursts::6 70957 # Per bank write bursts
system.physmem.perBankRdBursts::7 70585 # Per bank write bursts
system.physmem.perBankRdBursts::8 72320 # Per bank write bursts
system.physmem.perBankRdBursts::9 103108 # Per bank write bursts
system.physmem.perBankRdBursts::10 75527 # Per bank write bursts
system.physmem.perBankRdBursts::11 73923 # Per bank write bursts
system.physmem.perBankRdBursts::12 74067 # Per bank write bursts
system.physmem.perBankRdBursts::13 84199 # Per bank write bursts
system.physmem.perBankRdBursts::14 79405 # Per bank write bursts
system.physmem.perBankRdBursts::15 79777 # Per bank write bursts
system.physmem.perBankWrBursts::0 143281 # Per bank write bursts
system.physmem.perBankWrBursts::1 127790 # Per bank write bursts
system.physmem.perBankWrBursts::2 148899 # Per bank write bursts
system.physmem.perBankWrBursts::3 137605 # Per bank write bursts
system.physmem.perBankWrBursts::4 197374 # Per bank write bursts
system.physmem.perBankWrBursts::5 124383 # Per bank write bursts
system.physmem.perBankWrBursts::6 109194 # Per bank write bursts
system.physmem.perBankWrBursts::7 129383 # Per bank write bursts
system.physmem.perBankWrBursts::8 151210 # Per bank write bursts
system.physmem.perBankWrBursts::9 186118 # Per bank write bursts
system.physmem.perBankWrBursts::10 208778 # Per bank write bursts
system.physmem.perBankWrBursts::11 141342 # Per bank write bursts
system.physmem.perBankWrBursts::12 123729 # Per bank write bursts
system.physmem.perBankWrBursts::13 141617 # Per bank write bursts
system.physmem.perBankWrBursts::14 124170 # Per bank write bursts
system.physmem.perBankWrBursts::15 132827 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 128 # Number of times write queue was full causing retry
system.physmem.totGap 51316752176000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 13 # Read request sizes (log2)
system.physmem.readPktSize::4 2 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 1236221 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 1 # Write request sizes (log2)
system.physmem.writePktSize::3 2572 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 2391158 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 748020 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 328495 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 109863 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 42754 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 1151 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 512 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 432 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 350 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 243 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 167 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 147 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 147 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 134 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 123 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 118 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 107 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 97 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 87 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 65 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 45 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 5 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 779 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 747 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 745 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 739 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 736 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 735 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 732 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 732 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 729 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 726 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 725 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 726 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 726 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 729 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 730 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 48235 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 79967 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 90575 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 105567 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 121035 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 143044 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 145669 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 159604 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 163480 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 180978 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 163179 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 154131 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 135532 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 135592 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 103470 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 98111 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 96185 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 91160 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 8423 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 6931 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 6049 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 5454 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 5353 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 5092 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 4812 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 4475 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 4359 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 4005 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 3822 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 3600 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 3551 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 3323 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 3157 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 3047 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 3111 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 2761 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 2716 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 2698 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 2720 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 2285 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 2049 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 1803 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 1616 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 1233 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 932 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 668 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 461 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 323 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 336 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 678102 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 336.067624 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 184.620268 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 366.767956 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 271362 40.02% 40.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 148250 21.86% 61.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 55753 8.22% 70.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 26626 3.93% 74.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 20429 3.01% 77.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 13236 1.95% 78.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 10909 1.61% 80.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 14852 2.19% 82.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 116685 17.21% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 678102 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 81261 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 15.173946 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 173.903253 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047 81255 99.99% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-4095 3 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::10240-12287 2 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::45056-47103 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 81261 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 81261 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 28.644737 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 24.485973 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 20.407420 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::0-7 56 0.07% 0.07% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::8-15 139 0.17% 0.24% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-23 47231 58.12% 58.36% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-31 7834 9.64% 68.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-39 13023 16.03% 84.03% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-47 3682 4.53% 88.56% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-55 2148 2.64% 91.20% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-63 950 1.17% 92.37% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-71 2747 3.38% 95.75% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-79 1058 1.30% 97.06% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-87 767 0.94% 98.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-95 240 0.30% 98.29% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-103 341 0.42% 98.71% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-111 185 0.23% 98.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-119 486 0.60% 99.54% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-127 8 0.01% 99.55% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-135 31 0.04% 99.59% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-143 23 0.03% 99.62% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-151 18 0.02% 99.64% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-159 31 0.04% 99.68% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-167 73 0.09% 99.77% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::168-175 62 0.08% 99.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-183 51 0.06% 99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::184-191 8 0.01% 99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::192-199 17 0.02% 99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::200-207 1 0.00% 99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::208-215 17 0.02% 99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::216-223 5 0.01% 99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::224-231 2 0.00% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::232-239 1 0.00% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::240-247 9 0.01% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::248-255 7 0.01% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::256-263 2 0.00% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::264-271 6 0.01% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::272-279 2 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 81261 # Writes before turning the bus around for reads
system.physmem.totQLat 27538646010 # Total ticks spent queuing
system.physmem.totMemAccLat 50658558510 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 6165310000 # Total ticks spent in databus transfers
system.physmem.avgQLat 22333.55 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 41083.55 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 1.54 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 2.90 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 1.54 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 2.98 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.03 # Data bus utilization in percentage
system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.31 # Average read queue length when enqueuing
system.physmem.avgWrQLen 10.42 # Average write queue length when enqueuing
system.physmem.readRowHits 964323 # Number of row buffer hits during reads
system.physmem.writeRowHits 1918333 # Number of row buffer hits during writes
system.physmem.readRowHitRate 78.21 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 82.41 # Row buffer hit rate for writes
system.physmem.avgGap 14136974.85 # Average gap between requests
system.physmem.pageHitRate 80.96 # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE 49243370940756 # Time in different power states
system.physmem.memoryStateTime::REF 1713579140000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem.memoryStateTime::ACT 359802419244 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem.actEnergy::0 2507478120 # Energy for activate commands per rank (pJ)
system.physmem.actEnergy::1 2618973000 # Energy for activate commands per rank (pJ)
system.physmem.preEnergy::0 1368167625 # Energy for precharge commands per rank (pJ)
system.physmem.preEnergy::1 1429003125 # Energy for precharge commands per rank (pJ)
system.physmem.readEnergy::0 4607662800 # Energy for read commands per rank (pJ)
system.physmem.readEnergy::1 5010142800 # Energy for read commands per rank (pJ)
system.physmem.writeEnergy::0 7244050320 # Energy for write commands per rank (pJ)
system.physmem.writeEnergy::1 7839445680 # Energy for write commands per rank (pJ)
system.physmem.refreshEnergy::0 3351760797840 # Energy for refresh commands per rank (pJ)
system.physmem.refreshEnergy::1 3351760797840 # Energy for refresh commands per rank (pJ)
system.physmem.actBackEnergy::0 1283842483380 # Energy for active background per rank (pJ)
system.physmem.actBackEnergy::1 1294175764575 # Energy for active background per rank (pJ)
system.physmem.preBackEnergy::0 29663873874750 # Energy for precharge background per rank (pJ)
system.physmem.preBackEnergy::1 29654809593000 # Energy for precharge background per rank (pJ)
system.physmem.totalEnergy::0 34315204514835 # Total energy per rank (pJ)
system.physmem.totalEnergy::1 34317643720020 # Total energy per rank (pJ)
system.physmem.averagePower::0 668.694001 # Core power per rank (mW)
system.physmem.averagePower::1 668.741533 # Core power per rank (mW)
system.realview.nvmem.bytes_read::cpu0.inst 768 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst 1408 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 2212 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst 768 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst 1408 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 2176 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst 12 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst 22 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 39 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst 15 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst 27 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 43 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst 15 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst 27 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 42 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst 15 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst 27 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 43 # Total bandwidth to/from this memory (bytes/s)
system.membus.trans_dist::ReadReq 532705 # Transaction distribution
system.membus.trans_dist::ReadResp 532705 # Transaction distribution
system.membus.trans_dist::WriteReq 33859 # Transaction distribution
system.membus.trans_dist::WriteResp 33859 # Transaction distribution
system.membus.trans_dist::Writeback 719396 # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq 1671762 # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp 1671762 # Transaction distribution
system.membus.trans_dist::UpgradeReq 38473 # Transaction distribution
system.membus.trans_dist::SCUpgradeReq 6 # Transaction distribution
system.membus.trans_dist::UpgradeResp 38479 # Transaction distribution
system.membus.trans_dist::ReadExReq 739347 # Transaction distribution
system.membus.trans_dist::ReadExResp 739347 # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 123190 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 78 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6864 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 6390536 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total 6520668 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 228990 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 228990 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 6749658 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156320 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 2212 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13728 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 224910444 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total 225082704 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7262528 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 7262528 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 232345232 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 2042 # Total snoops (count)
system.membus.snoop_fanout::samples 3647418 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::1 3647418 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 3647418 # Request fanout histogram
system.membus.reqLayer0.occupancy 99715500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 54328 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer2.occupancy 5596000 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer5.occupancy 23226177977 # Layer occupancy (ticks)
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
system.membus.respLayer2.occupancy 13225855665 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
system.membus.respLayer3.occupancy 186556779 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.l2c.tags.replacements 929985 # number of replacements
system.l2c.tags.tagsinuse 64575.668438 # Cycle average of tags in use
system.l2c.tags.total_refs 30861842 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 992077 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 31.108313 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 13810399676500 # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks 34297.192611 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker 188.067974 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker 294.738587 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst 4135.506905 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data 11979.022995 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker 180.539676 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker 275.280153 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst 3419.385027 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data 9805.934509 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.523334 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002870 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker 0.004497 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst 0.063103 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data 0.182785 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002755 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker 0.004200 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst 0.052176 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data 0.149627 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.985347 # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1023 456 # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024 61636 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::1 6 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::2 9 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::3 5 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4 436 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1 238 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2 2227 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3 5080 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4 54047 # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1023 0.006958 # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024 0.940491 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 289012546 # Number of tag accesses
system.l2c.tags.data_accesses 289012546 # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker 544051 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker 184997 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst 8073705 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data 3475971 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker 537537 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker 184939 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst 7954467 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data 3403637 # number of ReadReq hits
system.l2c.ReadReq_hits::total 24359304 # number of ReadReq hits
system.l2c.Writeback_hits::writebacks 7101304 # number of Writeback hits
system.l2c.Writeback_hits::total 7101304 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data 6521 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 6161 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 12682 # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data 6 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data 2 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total 8 # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data 714827 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 684126 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 1398953 # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker 544051 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker 184997 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst 8073705 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 4190798 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker 537537 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker 184939 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 7954467 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 4087763 # number of demand (read+write) hits
system.l2c.demand_hits::total 25758257 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker 544051 # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker 184997 # number of overall hits
system.l2c.overall_hits::cpu0.inst 8073705 # number of overall hits
system.l2c.overall_hits::cpu0.data 4190798 # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker 537537 # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker 184939 # number of overall hits
system.l2c.overall_hits::cpu1.inst 7954467 # number of overall hits
system.l2c.overall_hits::cpu1.data 4087763 # number of overall hits
system.l2c.overall_hits::total 25758257 # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker 5086 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker 8033 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.inst 43375 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data 182199 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker 4792 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.itb.walker 7524 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst 45500 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data 173082 # number of ReadReq misses
system.l2c.ReadReq_misses::total 469591 # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data 19389 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data 18469 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 37858 # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data 3 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data 3 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total 6 # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data 376161 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 363798 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 739959 # number of ReadExReq misses
system.l2c.demand_misses::cpu0.dtb.walker 5086 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker 8033 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst 43375 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 558360 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker 4792 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker 7524 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst 45500 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 536880 # number of demand (read+write) misses
system.l2c.demand_misses::total 1209550 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker 5086 # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker 8033 # number of overall misses
system.l2c.overall_misses::cpu0.inst 43375 # number of overall misses
system.l2c.overall_misses::cpu0.data 558360 # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker 4792 # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker 7524 # number of overall misses
system.l2c.overall_misses::cpu1.inst 45500 # number of overall misses
system.l2c.overall_misses::cpu1.data 536880 # number of overall misses
system.l2c.overall_misses::total 1209550 # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 402067961 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.itb.walker 620871486 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.inst 3358802499 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data 14928489876 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 371387969 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.itb.walker 584303733 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst 3543805470 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data 14055803105 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total 37865532099 # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data 215945240 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data 206928138 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 422873378 # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data 45998 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data 45998 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total 91996 # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data 33150632854 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data 32508892128 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 65659524982 # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker 402067961 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker 620871486 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst 3358802499 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data 48079122730 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker 371387969 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.itb.walker 584303733 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst 3543805470 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data 46564695233 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 103525057081 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker 402067961 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker 620871486 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst 3358802499 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data 48079122730 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker 371387969 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.itb.walker 584303733 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst 3543805470 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data 46564695233 # number of overall miss cycles
system.l2c.overall_miss_latency::total 103525057081 # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker 549137 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker 193030 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst 8117080 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data 3658170 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker 542329 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker 192463 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst 7999967 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data 3576719 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 24828895 # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks 7101304 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 7101304 # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 25910 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 24630 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 50540 # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data 9 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data 5 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total 14 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data 1090988 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data 1047924 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 2138912 # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker 549137 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker 193030 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst 8117080 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data 4749158 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker 542329 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker 192463 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst 7999967 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data 4624643 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 26967807 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker 549137 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker 193030 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst 8117080 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data 4749158 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker 542329 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker 192463 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst 7999967 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data 4624643 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 26967807 # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.009262 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.041615 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.inst 0.005344 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data 0.049806 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.008836 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.039093 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst 0.005688 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data 0.048391 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total 0.018913 # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.748321 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.749858 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.749070 # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.333333 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.600000 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total 0.428571 # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data 0.344789 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data 0.347161 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.345951 # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker 0.009262 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker 0.041615 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst 0.005344 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data 0.117570 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker 0.008836 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.itb.walker 0.039093 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst 0.005688 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data 0.116091 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.044852 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker 0.009262 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker 0.041615 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst 0.005344 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data 0.117570 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker 0.008836 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.itb.walker 0.039093 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst 0.005688 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data 0.116091 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.044852 # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 79053.865710 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 77290.114030 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 77436.368853 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 81935.081290 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 77501.662980 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 77658.656699 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 77885.834505 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 81208.924700 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 80635.131634 # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 11137.513023 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 11204.079160 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 11169.987268 # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 15332.666667 # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 15332.666667 # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total 15332.666667 # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 88128.840720 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 89359.732951 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 88734.004157 # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 79053.865710 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker 77290.114030 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 77436.368853 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 86107.748997 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 77501.662980 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.itb.walker 77658.656699 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 77885.834505 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 86732.035526 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 85589.729305 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 79053.865710 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 77290.114030 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 77436.368853 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 86107.748997 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 77501.662980 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.itb.walker 77658.656699 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 77885.834505 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 86732.035526 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 85589.729305 # average overall miss latency
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
system.l2c.writebacks::writebacks 719396 # number of writebacks
system.l2c.writebacks::total 719396 # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu0.dtb.walker 19 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu0.itb.walker 41 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu0.inst 1 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu0.data 10 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.dtb.walker 16 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.itb.walker 32 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.data 12 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total 131 # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.dtb.walker 19 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.itb.walker 41 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.data 10 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.dtb.walker 16 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.itb.walker 32 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.data 12 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total 131 # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.dtb.walker 19 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.itb.walker 41 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.data 10 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.dtb.walker 16 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.itb.walker 32 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.data 12 # number of overall MSHR hits
system.l2c.overall_mshr_hits::total 131 # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 5067 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 7992 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.inst 43374 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data 182189 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 4776 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 7492 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst 45500 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data 173070 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total 469460 # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data 19389 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data 18469 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total 37858 # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 3 # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 3 # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total 6 # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data 376161 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data 363798 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total 739959 # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker 5067 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker 7992 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst 43374 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data 558350 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker 4776 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.itb.walker 7492 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst 45500 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data 536868 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total 1209419 # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker 5067 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker 7992 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst 43374 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data 558350 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker 4776 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.itb.walker 7492 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst 45500 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data 536868 # number of overall MSHR misses
system.l2c.overall_mshr_misses::total 1209419 # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 337731462 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 518462986 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 2814140251 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data 12660420650 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 310477469 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 489154483 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 2972644030 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data 11900726415 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total 32003757746 # number of ReadReq MSHR miss cycles
system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu0.data 18731109098 # number of WriteInvalidateReq MSHR miss cycles
system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu1.data 18506673413 # number of WriteInvalidateReq MSHR miss cycles
system.l2c.WriteInvalidateReq_mshr_miss_latency::total 37237782511 # number of WriteInvalidateReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 194429364 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 185281438 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total 379710802 # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 30003 # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 30003 # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total 60006 # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 28452194992 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 27967189734 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total 56419384726 # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 337731462 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 518462986 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst 2814140251 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data 41112615642 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 310477469 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 489154483 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst 2972644030 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data 39867916149 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 88423142472 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 337731462 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 518462986 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst 2814140251 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data 41112615642 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 310477469 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 489154483 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst 2972644030 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data 39867916149 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 88423142472 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 654614249 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 3015317250 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 425309250 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2261474250 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 6356714999 # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 3033164500 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 2138382499 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total 5171546999 # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 654614249 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data 6048481750 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 425309250 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 4399856749 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 11528261998 # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.009227 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.041403 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.005344 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.049803 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.008806 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.038927 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.005688 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.048388 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total 0.018908 # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.748321 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.749858 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.749070 # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.333333 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.600000 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.428571 # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.344789 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.347161 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.345951 # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.009227 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.041403 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.005344 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data 0.117568 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.008806 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.038927 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.005688 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data 0.116089 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.044847 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.009227 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.041403 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.005344 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data 0.117568 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.008806 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.038927 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.005688 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.116089 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.044847 # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 66653.140320 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 64872.745996 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 64880.809955 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 69490.587522 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 65007.845268 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 65290.240657 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 65332.835824 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 68762.503120 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 68171.426205 # average ReadReq mshr miss latency
system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data inf # average WriteInvalidateReq mshr miss latency
system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data inf # average WriteInvalidateReq mshr miss latency
system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10027.818041 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10032.023282 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10029.869565 # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 75638.343667 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 76875.600564 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 76246.636268 # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 66653.140320 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 64872.745996 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 64880.809955 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 73632.337498 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 65007.845268 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 65290.240657 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 65332.835824 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 74260.183414 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 73112.083134 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 66653.140320 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 64872.745996 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 64880.809955 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 73632.337498 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 65007.845268 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 65290.240657 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 65332.835824 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 74260.183414 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 73112.083134 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.realview.ethernet.txBytes 966 # Bytes Transmitted
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.realview.ethernet.totBandwidth 151 # Total Bandwidth (bits/s)
system.realview.ethernet.totPackets 3 # Total Packets
system.realview.ethernet.totBytes 966 # Total Bytes
system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
system.realview.ethernet.txBandwidth 151 # Transmit Bandwidth (bits/s)
system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 18 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 1669 # Number of DMA write transactions.
system.toL2Bus.trans_dist::ReadReq 25440595 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 25432319 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 33859 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 33859 # Transaction distribution
system.toL2Bus.trans_dist::Writeback 7101304 # Transaction distribution
system.toL2Bus.trans_dist::WriteInvalidateReq 1671768 # Transaction distribution
system.toL2Bus.trans_dist::WriteInvalidateResp 1565098 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 50543 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq 14 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 50557 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 2138912 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 2138912 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 32275606 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 29216023 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 915477 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 2586660 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 64993766 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 1032811840 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1154800272 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 3083944 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 8731728 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total 2199427784 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops 664547 # Total snoops (count)
system.toL2Bus.snoop_fanout::samples 36349119 # Request fanout histogram
system.toL2Bus.snoop_fanout::mean 5.003178 # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev 0.056284 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::5 36233600 99.68% 99.68% # Request fanout histogram
system.toL2Bus.snoop_fanout::6 115519 0.32% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
system.toL2Bus.snoop_fanout::total 36349119 # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy 52855909091 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy 2566500 # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy 72684313037 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy 43208232692 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy 533902381 # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy 1509803178 # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.trans_dist::ReadReq 40375 # Transaction distribution
system.iobus.trans_dist::ReadResp 40375 # Transaction distribution
system.iobus.trans_dist::WriteReq 136543 # Transaction distribution
system.iobus.trans_dist::WriteResp 136733 # Transaction distribution
system.iobus.trans_dist::WriteInvalidateReq 190 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48308 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total 123190 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230946 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total 230946 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 354216 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48328 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total 156320 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334216 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total 7334216 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total 7492622 # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy 36706000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer27.occupancy 981411596 # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer0.occupancy 93124000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer3.occupancy 178989221 # Layer occupancy (ticks)
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks)
system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
system.cpu0.branchPred.lookups 132719565 # Number of BP lookups
system.cpu0.branchPred.condPredicted 89993236 # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect 5932836 # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups 90710148 # Number of BTB lookups
system.cpu0.branchPred.BTBHits 64716268 # Number of BTB hits
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct 71.344022 # BTB Hit Percentage
system.cpu0.branchPred.usedRAS 17452568 # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect 191045 # Number of incorrect RAS predictions.
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
system.cpu0.dtb.read_hits 106360367 # DTB read hits
system.cpu0.dtb.read_misses 615971 # DTB read misses
system.cpu0.dtb.write_hits 81393112 # DTB write hits
system.cpu0.dtb.write_misses 266071 # DTB write misses
system.cpu0.dtb.flush_tlb 1087 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 22107 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 543 # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries 56260 # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 229 # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults 9041 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults 57266 # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses 106976338 # DTB read accesses
system.cpu0.dtb.write_accesses 81659183 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
system.cpu0.dtb.hits 187753479 # DTB hits
system.cpu0.dtb.misses 882042 # DTB misses
system.cpu0.dtb.accesses 188635521 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu0.itb.inst_hits 95391690 # ITB inst hits
system.cpu0.itb.inst_misses 104013 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.flush_tlb 1087 # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid 22107 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 543 # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries 41837 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults 207435 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
system.cpu0.itb.inst_accesses 95495703 # ITB inst accesses
system.cpu0.itb.hits 95391690 # DTB hits
system.cpu0.itb.misses 104013 # DTB misses
system.cpu0.itb.accesses 95495703 # DTB accesses
system.cpu0.numCycles 684418323 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.fetch.icacheStallCycles 248384937 # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts 589536301 # Number of instructions fetch has processed
system.cpu0.fetch.Branches 132719565 # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches 82168836 # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles 395321090 # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles 13514905 # Number of cycles fetch has spent squashing
system.cpu0.fetch.TlbCycles 2556917 # Number of cycles fetch has spent waiting for tlb
system.cpu0.fetch.MiscStallCycles 20977 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingDrainCycles 5408 # Number of cycles fetch has spent waiting on pipes to drain
system.cpu0.fetch.PendingTrapStallCycles 5551519 # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles 175554 # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles 1648 # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines 95166614 # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes 3687085 # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.ItlbSquashes 41415 # Number of outstanding ITLB misses that were squashed
system.cpu0.fetch.rateDist::samples 658775231 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean 1.047637 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev 2.297009 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0 512971129 77.87% 77.87% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1 18432133 2.80% 80.67% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2 18348661 2.79% 83.45% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3 13411814 2.04% 85.49% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4 28741584 4.36% 89.85% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5 9038627 1.37% 91.22% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6 9794305 1.49% 92.71% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7 8428424 1.28% 93.99% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8 39608554 6.01% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total 658775231 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate 0.193916 # Number of branch fetches per cycle
system.cpu0.fetch.rate 0.861368 # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles 200994103 # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles 333361407 # Number of cycles decode is blocked
system.cpu0.decode.RunCycles 105045785 # Number of cycles decode is running
system.cpu0.decode.UnblockCycles 14028144 # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles 5343793 # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved 19697248 # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred 1433030 # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts 641923192 # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts 4435962 # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles 5343793 # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles 208785389 # Number of cycles rename is idle
system.cpu0.rename.BlockCycles 28964603 # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles 262496699 # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles 111103202 # Number of cycles rename is running
system.cpu0.rename.UnblockCycles 42079210 # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts 626316852 # Number of instructions processed by rename
system.cpu0.rename.ROBFullEvents 80050 # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents 2362679 # Number of times rename has blocked due to IQ full
system.cpu0.rename.LQFullEvents 1879089 # Number of times rename has blocked due to LQ full
system.cpu0.rename.SQFullEvents 21911490 # Number of times rename has blocked due to SQ full
system.cpu0.rename.FullRegisterEvents 5199 # Number of times there has been no free registers
system.cpu0.rename.RenamedOperands 599577423 # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups 966250594 # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups 740756106 # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups 877957 # Number of floating rename lookups
system.cpu0.rename.CommittedMaps 502593400 # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps 96984018 # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts 15462984 # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts 13497488 # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts 79320336 # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads 100980804 # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores 85727659 # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads 13927717 # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores 14882282 # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded 593862929 # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded 15564372 # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued 595387827 # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued 831090 # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined 76362787 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined 53001437 # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved 356285 # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples 658775231 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean 0.903780 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev 1.628017 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0 423143545 64.23% 64.23% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1 100533840 15.26% 79.49% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2 43588427 6.62% 86.11% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3 31078402 4.72% 90.83% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4 23328962 3.54% 94.37% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5 15913876 2.42% 96.78% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6 10814135 1.64% 98.43% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7 6320463 0.96% 99.38% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8 4053581 0.62% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total 658775231 # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu 2985575 25.28% 25.28% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult 23079 0.20% 25.48% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv 3324 0.03% 25.51% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd 0 0.00% 25.51% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp 0 0.00% 25.51% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt 0 0.00% 25.51% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult 0 0.00% 25.51% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv 0 0.00% 25.51% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 25.51% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd 0 0.00% 25.51% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 25.51% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu 0 0.00% 25.51% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp 0 0.00% 25.51% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt 0 0.00% 25.51% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc 0 0.00% 25.51% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult 0 0.00% 25.51% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 25.51% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift 0 0.00% 25.51% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 25.51% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 25.51% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 25.51% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 25.51% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 25.51% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 25.51% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 25.51% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc 2 0.00% 25.51% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 25.51% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.51% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 25.51% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead 5019003 42.51% 68.01% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite 3776946 31.99% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass 1 0.00% 0.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu 402885613 67.67% 67.67% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult 1422777 0.24% 67.91% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv 64552 0.01% 67.92% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd 67 0.00% 67.92% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 67.92% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 67.92% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 67.92% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 67.92% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 67.92% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 67.92% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 67.92% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 67.92% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 67.92% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 67.92% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 67.92% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 67.92% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 67.92% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 67.92% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.92% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 67.92% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.92% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.92% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.92% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.92% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.92% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc 58868 0.01% 67.93% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 67.93% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.93% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.93% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead 108485553 18.22% 86.15% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite 82470396 13.85% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total 595387827 # Type of FU issued
system.cpu0.iq.rate 0.869918 # Inst issue rate
system.cpu0.iq.fu_busy_cnt 11807929 # FU busy when requested
system.cpu0.iq.fu_busy_rate 0.019832 # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads 1861125914 # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes 685987174 # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses 571772727 # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads 1063990 # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes 505463 # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses 456200 # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses 606627126 # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses 568629 # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads 4761213 # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads 16799552 # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses 22497 # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation 714171 # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores 9156054 # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads 3900719 # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked 9933744 # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles 5343793 # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles 15674856 # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles 11567544 # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts 609566615 # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts 1794840 # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts 100980804 # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts 85727659 # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts 13194913 # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents 258499 # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents 11189475 # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents 714171 # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect 2685620 # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect 2322794 # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts 5008414 # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts 588648436 # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts 106351748 # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts 5872018 # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp 0 # number of swp insts executed
system.cpu0.iew.exec_nop 139314 # number of nop insts executed
system.cpu0.iew.exec_refs 187749395 # number of memory reference insts executed
system.cpu0.iew.exec_branches 108957932 # Number of branches executed
system.cpu0.iew.exec_stores 81397647 # Number of stores executed
system.cpu0.iew.exec_rate 0.860071 # Inst execution rate
system.cpu0.iew.wb_sent 573457881 # cumulative count of insts sent to commit
system.cpu0.iew.wb_count 572228927 # cumulative count of insts written-back
system.cpu0.iew.wb_producers 281462520 # num instructions producing a value
system.cpu0.iew.wb_consumers 488752044 # num instructions consuming a value
system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu0.iew.wb_rate 0.836081 # insts written-back per cycle
system.cpu0.iew.wb_fanout 0.575880 # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu0.commit.commitSquashedInsts 82137816 # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls 15208087 # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts 4518905 # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples 644781794 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean 0.817863 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev 1.810443 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0 449449526 69.71% 69.71% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1 97358122 15.10% 84.81% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2 33578375 5.21% 90.01% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3 14917712 2.31% 92.33% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4 10631887 1.65% 93.98% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5 6530680 1.01% 94.99% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6 5822825 0.90% 95.89% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7 3984235 0.62% 96.51% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8 22508432 3.49% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total 644781794 # Number of insts commited each cycle
system.cpu0.commit.committedInsts 448706085 # Number of instructions committed
system.cpu0.commit.committedOps 527343007 # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu0.commit.refs 160752856 # Number of memory references committed
system.cpu0.commit.loads 84181251 # Number of loads committed
system.cpu0.commit.membars 3744837 # Number of memory barriers committed
system.cpu0.commit.branches 100346754 # Number of branches committed
system.cpu0.commit.fp_insts 436641 # Number of committed floating point instructions.
system.cpu0.commit.int_insts 484032213 # Number of committed integer instructions.
system.cpu0.commit.function_calls 13338237 # Number of function calls committed.
system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IntAlu 365400890 69.29% 69.29% # Class of committed instruction
system.cpu0.commit.op_class_0::IntMult 1092025 0.21% 69.50% # Class of committed instruction
system.cpu0.commit.op_class_0::IntDiv 47793 0.01% 69.51% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.51% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.51% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.51% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.51% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.51% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.51% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.51% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.51% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.51% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.51% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.51% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.51% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.51% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.51% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.51% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.51% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.51% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 69.51% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.51% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 69.51% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 69.51% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.51% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMisc 49443 0.01% 69.52% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.52% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.52% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.52% # Class of committed instruction
system.cpu0.commit.op_class_0::MemRead 84181251 15.96% 85.48% # Class of committed instruction
system.cpu0.commit.op_class_0::MemWrite 76571605 14.52% 100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::total 527343007 # Class of committed instruction
system.cpu0.commit.bw_lim_events 22508432 # number cycles where commit BW limit reached
system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu0.rob.rob_reads 1227661689 # The number of ROB reads
system.cpu0.rob.rob_writes 1232973286 # The number of ROB writes
system.cpu0.timesIdled 4104064 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles 25643092 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles 54070741689 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts 448706085 # Number of Instructions Simulated
system.cpu0.committedOps 527343007 # Number of Ops (including micro ops) Simulated
system.cpu0.cpi 1.525315 # CPI: Cycles Per Instruction
system.cpu0.cpi_total 1.525315 # CPI: Total CPI of All Threads
system.cpu0.ipc 0.655602 # IPC: Instructions Per Cycle
system.cpu0.ipc_total 0.655602 # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads 693970255 # number of integer regfile reads
system.cpu0.int_regfile_writes 408353798 # number of integer regfile writes
system.cpu0.fp_regfile_reads 822679 # number of floating regfile reads
system.cpu0.fp_regfile_writes 492268 # number of floating regfile writes
system.cpu0.cc_regfile_reads 125884227 # number of cc regfile reads
system.cpu0.cc_regfile_writes 126919674 # number of cc regfile writes
system.cpu0.misc_regfile_reads 2342378074 # number of misc regfile reads
system.cpu0.misc_regfile_writes 15341166 # number of misc regfile writes
system.cpu0.icache.tags.replacements 16116656 # number of replacements
system.cpu0.icache.tags.tagsinuse 511.960235 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 173052626 # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs 16117168 # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs 10.737161 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 11668105000 # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst 286.930366 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu1.inst 225.029869 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.560411 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu1.inst 0.439511 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total 0.999922 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1 306 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2 81 # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses 206428941 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 206428941 # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst 86457913 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst 86594713 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 173052626 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 86457913 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst 86594713 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 173052626 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 86457913 # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst 86594713 # number of overall hits
system.cpu0.icache.overall_hits::total 173052626 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 8696178 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst 8562854 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 17259032 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 8696178 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst 8562854 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 17259032 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 8696178 # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst 8562854 # number of overall misses
system.cpu0.icache.overall_misses::total 17259032 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 115519417356 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 113985057745 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 229504475101 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst 115519417356 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst 113985057745 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 229504475101 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst 115519417356 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst 113985057745 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 229504475101 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 95154091 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst 95157567 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 190311658 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 95154091 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst 95157567 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 190311658 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 95154091 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst 95157567 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 190311658 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.091390 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.089986 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.090688 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.091390 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst 0.089986 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.090688 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.091390 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst 0.089986 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.090688 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13283.929717 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13311.573191 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 13297.644683 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13283.929717 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13311.573191 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 13297.644683 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13283.929717 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13311.573191 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 13297.644683 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 66644 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 6194 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs 10.759445 # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 579009 # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 562740 # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total 1141749 # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst 579009 # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu1.inst 562740 # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total 1141749 # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst 579009 # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu1.inst 562740 # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total 1141749 # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 8117169 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 8000114 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 16117283 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst 8117169 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst 8000114 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 16117283 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst 8117169 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst 8000114 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 16117283 # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 94378713924 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 93158518069 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 187537231993 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 94378713924 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 93158518069 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 187537231993 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 94378713924 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 93158518069 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 187537231993 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 916338250 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 595537750 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 1511876000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 916338250 # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst 595537750 # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total 1511876000 # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.085306 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.084072 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.084689 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.085306 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.084072 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.084689 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.085306 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.084072 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.084689 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11627.048042 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11644.648822 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11635.784517 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11627.048042 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11644.648822 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 11635.784517 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11627.048042 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11644.648822 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 11635.784517 # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.dcache.tags.replacements 10609337 # number of replacements
system.cpu0.dcache.tags.tagsinuse 511.983537 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 304225194 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 10609849 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 28.673848 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 1654841000 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data 299.046294 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data 212.937243 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.584075 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu1.data 0.415893 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total 0.999968 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 166 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 324 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 22 # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses 1343384056 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 1343384056 # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data 80019383 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data 80708532 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 160727915 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 67091357 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data 67952351 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 135043708 # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data 206774 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu1.data 197330 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total 404104 # number of SoftPFReq hits
system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 787450 # number of WriteInvalidateReq hits
system.cpu0.dcache.WriteInvalidateReq_hits::cpu1.data 777648 # number of WriteInvalidateReq hits
system.cpu0.dcache.WriteInvalidateReq_hits::total 1565098 # number of WriteInvalidateReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1810718 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 1758217 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 3568935 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2068647 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu1.data 2014712 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 4083359 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 147110740 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data 148660883 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 295771623 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 147317514 # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data 148858213 # number of overall hits
system.cpu0.dcache.overall_hits::total 296175727 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 6473624 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data 6388313 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 12861937 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 6626672 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data 6359050 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 12985722 # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data 668006 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu1.data 645779 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total 1313785 # number of SoftPFReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 322811 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 316162 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 638973 # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 9 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu1.data 5 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total 14 # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data 13100296 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data 12747363 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 25847659 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 13768302 # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data 13393142 # number of overall misses
system.cpu0.dcache.overall_misses::total 27161444 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 116104812410 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 112446419858 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 228551232268 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 283825834860 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 276276891882 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 560102726742 # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 4581170687 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 4543459438 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total 9124630125 # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 155503 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 103503 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total 259006 # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 399930647270 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data 388723311740 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 788653959010 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 399930647270 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data 388723311740 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 788653959010 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 86493007 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data 87096845 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 173589852 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 73718029 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data 74311401 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 148029430 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 874780 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 843109 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total 1717889 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 787450 # number of WriteInvalidateReq accesses(hits+misses)
system.cpu0.dcache.WriteInvalidateReq_accesses::cpu1.data 777648 # number of WriteInvalidateReq accesses(hits+misses)
system.cpu0.dcache.WriteInvalidateReq_accesses::total 1565098 # number of WriteInvalidateReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2133529 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 2074379 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 4207908 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2068656 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 2014717 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 4083373 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 160211036 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data 161408246 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 321619282 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 161085816 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data 162251355 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 323337171 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.074846 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.073347 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.074094 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.089892 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.085573 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.087724 # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.763627 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.765950 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total 0.764767 # miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.151304 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.152413 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.151851 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000004 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000002 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000003 # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.081769 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data 0.078976 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.080367 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.085472 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data 0.082546 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.084003 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 17935.056532 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 17601.895815 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 17769.581072 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 42830.825920 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 43446.252488 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 43132.197558 # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14191.494983 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14370.668955 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14280.149748 # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 17278.111111 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 20700.600000 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 18500.428571 # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 30528.367242 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 30494.409843 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 30511.620376 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 29047.201846 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 29024.056621 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 29035.789077 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 69133267 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 73151 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 4037000 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 1206 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 17.124911 # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets 60.655887 # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 1565098 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks 7101304 # number of writebacks
system.cpu0.dcache.writebacks::total 7101304 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3596643 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 3569355 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total 7165998 # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 5504075 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 5281537 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total 10785612 # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 195820 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 191080 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 386900 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data 9100718 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu1.data 8850892 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total 17951610 # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data 9100718 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu1.data 8850892 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total 17951610 # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2876981 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 2818958 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 5695939 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1110111 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 1065853 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 2175964 # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 660985 # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 639380 # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total 1300365 # number of SoftPFReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 126991 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 125082 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 252073 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 9 # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 5 # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total 14 # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data 3987092 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data 3884811 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 7871903 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data 4648077 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data 4524191 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 9172268 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 44486434450 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 43558695911 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 88045130361 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 45021160958 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 43869767531 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 88890928489 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 13293961502 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 12330781777 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 25624743279 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 29043542969 # number of WriteInvalidateReq MSHR miss cycles
system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 28669048764 # number of WriteInvalidateReq MSHR miss cycles
system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 57712591733 # number of WriteInvalidateReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1626539446 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1632214456 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 3258753902 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 137497 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 93497 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 230994 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 89507595408 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 87428463442 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 176936058850 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 102801556910 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 99759245219 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 202560802129 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3260677254 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2455829253 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5716506507 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 3279198543 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2300797457 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5579996000 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6539875797 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 4756626710 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11296502507 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033263 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.032366 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.032813 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.015059 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014343 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.014700 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.755601 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.758360 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.756955 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059522 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.060299 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059905 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000004 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000002 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000003 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.024887 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.024068 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.024476 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028855 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.027884 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.028368 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15462.887815 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15452.055657 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15457.526908 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 40555.548912 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 41159.303892 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 40851.286367 # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 20112.349754 # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 19285.529383 # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 19705.808199 # average SoftPFReq mshr miss latency
system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data inf # average WriteInvalidateReq mshr miss latency
system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data inf # average WriteInvalidateReq mshr miss latency
system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12808.304888 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13049.155402 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12927.818140 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 15277.444444 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 18699.400000 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 16499.571429 # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22449.342881 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 22505.203842 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 22476.910456 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22117.008154 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 22050.184269 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22084.047493 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.branchPred.lookups 132695624 # Number of BP lookups
system.cpu1.branchPred.condPredicted 90331188 # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect 5850625 # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups 91191115 # Number of BTB lookups
system.cpu1.branchPred.BTBHits 65101533 # Number of BTB hits
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct 71.390215 # BTB Hit Percentage
system.cpu1.branchPred.usedRAS 17167330 # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect 185817 # Number of incorrect RAS predictions.
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
system.cpu1.dtb.read_hits 106438912 # DTB read hits
system.cpu1.dtb.read_misses 617019 # DTB read misses
system.cpu1.dtb.write_hits 81859907 # DTB write hits
system.cpu1.dtb.write_misses 262953 # DTB write misses
system.cpu1.dtb.flush_tlb 1095 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 21187 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 524 # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries 54609 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 175 # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults 8788 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults 55422 # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses 107055931 # DTB read accesses
system.cpu1.dtb.write_accesses 82122860 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
system.cpu1.dtb.hits 188298819 # DTB hits
system.cpu1.dtb.misses 879972 # DTB misses
system.cpu1.dtb.accesses 189178791 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu1.itb.inst_hits 95390425 # ITB inst hits
system.cpu1.itb.inst_misses 103002 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.flush_tlb 1095 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid 21187 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 524 # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries 40480 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults 202732 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
system.cpu1.itb.inst_accesses 95493427 # ITB inst accesses
system.cpu1.itb.hits 95390425 # DTB hits
system.cpu1.itb.misses 103002 # DTB misses
system.cpu1.itb.accesses 95493427 # DTB accesses
system.cpu1.numCycles 672741965 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.fetch.icacheStallCycles 246640136 # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts 590780429 # Number of instructions fetch has processed
system.cpu1.fetch.Branches 132695624 # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches 82268863 # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles 386429410 # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles 13305333 # Number of cycles fetch has spent squashing
system.cpu1.fetch.TlbCycles 2543340 # Number of cycles fetch has spent waiting for tlb
system.cpu1.fetch.MiscStallCycles 19984 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingDrainCycles 4103 # Number of cycles fetch has spent waiting on pipes to drain
system.cpu1.fetch.PendingTrapStallCycles 5378147 # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles 163710 # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles 1900 # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines 95165721 # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes 3597908 # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.ItlbSquashes 39974 # Number of outstanding ITLB misses that were squashed
system.cpu1.fetch.rateDist::samples 647833125 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean 1.067316 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev 2.314702 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0 501796172 77.46% 77.46% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1 18436133 2.85% 80.30% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2 18485753 2.85% 83.16% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3 13501389 2.08% 85.24% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4 28566375 4.41% 89.65% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5 9032490 1.39% 91.04% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6 9749840 1.50% 92.55% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7 8516033 1.31% 93.86% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8 39748940 6.14% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total 647833125 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate 0.197246 # Number of branch fetches per cycle
system.cpu1.fetch.rate 0.878168 # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles 200194473 # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles 322668892 # Number of cycles decode is blocked
system.cpu1.decode.RunCycles 105843727 # Number of cycles decode is running
system.cpu1.decode.UnblockCycles 13827399 # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles 5296426 # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved 19681907 # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred 1375410 # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts 644487824 # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts 4238266 # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles 5296426 # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles 207887374 # Number of cycles rename is idle
system.cpu1.rename.BlockCycles 28633275 # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles 252987067 # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles 111782593 # Number of cycles rename is running
system.cpu1.rename.UnblockCycles 41244065 # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts 628972841 # Number of instructions processed by rename
system.cpu1.rename.ROBFullEvents 101309 # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents 2336709 # Number of times rename has blocked due to IQ full
system.cpu1.rename.LQFullEvents 1765264 # Number of times rename has blocked due to LQ full
system.cpu1.rename.SQFullEvents 21471594 # Number of times rename has blocked due to SQ full
system.cpu1.rename.FullRegisterEvents 4932 # Number of times there has been no free registers
system.cpu1.rename.RenamedOperands 601986706 # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups 968135800 # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups 743741537 # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups 921788 # Number of floating rename lookups
system.cpu1.rename.CommittedMaps 504541868 # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps 97444838 # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts 15091316 # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts 13114684 # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts 77880403 # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads 101483347 # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores 86159667 # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads 13596196 # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores 14436334 # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded 596800589 # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded 15137564 # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued 597335702 # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued 820098 # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined 76624490 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined 53348640 # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved 353802 # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples 647833125 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean 0.922052 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev 1.644482 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0 412924221 63.74% 63.74% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1 99304245 15.33% 79.07% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2 43461350 6.71% 85.78% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3 31157407 4.81% 90.59% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4 23474401 3.62% 94.21% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5 16043027 2.48% 96.69% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6 10934122 1.69% 98.37% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7 6355751 0.98% 99.35% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8 4178601 0.65% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total 647833125 # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu 3005947 25.29% 25.29% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult 24266 0.20% 25.49% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv 2049 0.02% 25.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd 0 0.00% 25.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp 0 0.00% 25.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt 0 0.00% 25.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult 0 0.00% 25.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv 0 0.00% 25.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 25.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd 0 0.00% 25.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 25.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu 0 0.00% 25.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp 0 0.00% 25.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt 0 0.00% 25.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc 0 0.00% 25.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult 0 0.00% 25.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 25.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift 0 0.00% 25.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 25.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 25.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 25.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 25.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 25.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 25.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 25.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc 4 0.00% 25.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 25.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 25.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead 4972015 41.83% 67.34% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite 3881824 32.66% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass 1 0.00% 0.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu 404183986 67.66% 67.66% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult 1499549 0.25% 67.92% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv 69544 0.01% 67.93% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd 173 0.00% 67.93% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 67.93% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 67.93% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 67.93% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 67.93% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 67.93% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 67.93% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 67.93% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 67.93% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 67.93% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 67.93% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 67.93% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 67.93% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 67.93% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 67.93% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.93% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 67.93% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd 9 0.00% 67.93% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.93% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp 16 0.00% 67.93% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt 24 0.00% 67.93% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.93% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc 70359 0.01% 67.94% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 67.94% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.94% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.94% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead 108574781 18.18% 86.12% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite 82937260 13.88% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total 597335702 # Type of FU issued
system.cpu1.iq.rate 0.887912 # Inst issue rate
system.cpu1.iq.fu_busy_cnt 11886105 # FU busy when requested
system.cpu1.iq.fu_busy_rate 0.019899 # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads 1854102856 # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes 688730877 # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses 574087973 # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads 1107876 # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes 525044 # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses 478100 # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses 608629489 # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses 592317 # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads 4742542 # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads 16809176 # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses 22821 # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation 704571 # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores 9065130 # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads 3904838 # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked 9464363 # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles 5296426 # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles 15503911 # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles 11248845 # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts 612073318 # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts 1785807 # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts 101483347 # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts 86159667 # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts 12828539 # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents 251466 # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents 10878256 # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents 704571 # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect 2684400 # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect 2302903 # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts 4987303 # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts 590552056 # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts 106426998 # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts 5916414 # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp 0 # number of swp insts executed
system.cpu1.iew.exec_nop 135165 # number of nop insts executed
system.cpu1.iew.exec_refs 188286771 # number of memory reference insts executed
system.cpu1.iew.exec_branches 109138667 # Number of branches executed
system.cpu1.iew.exec_stores 81859773 # Number of stores executed
system.cpu1.iew.exec_rate 0.877828 # Inst execution rate
system.cpu1.iew.wb_sent 575751009 # cumulative count of insts sent to commit
system.cpu1.iew.wb_count 574566073 # cumulative count of insts written-back
system.cpu1.iew.wb_producers 283200911 # num instructions producing a value
system.cpu1.iew.wb_consumers 491579029 # num instructions consuming a value
system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu1.iew.wb_rate 0.854066 # insts written-back per cycle
system.cpu1.iew.wb_fanout 0.576105 # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu1.commit.commitSquashedInsts 82275122 # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls 14783762 # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts 4494113 # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples 633863514 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean 0.835692 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev 1.830647 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0 439265925 69.30% 69.30% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1 95913161 15.13% 84.43% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2 33589452 5.30% 89.73% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3 15187737 2.40% 92.13% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4 10634281 1.68% 93.80% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5 6553980 1.03% 94.84% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6 5971917 0.94% 95.78% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7 4055542 0.64% 96.42% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8 22691519 3.58% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total 633863514 # Number of insts commited each cycle
system.cpu1.commit.committedInsts 450820499 # Number of instructions committed
system.cpu1.commit.committedOps 529714748 # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu1.commit.refs 161768708 # Number of memory references committed
system.cpu1.commit.loads 84674171 # Number of loads committed
system.cpu1.commit.membars 3651509 # Number of memory barriers committed
system.cpu1.commit.branches 100548022 # Number of branches committed
system.cpu1.commit.fp_insts 459048 # Number of committed floating point instructions.
system.cpu1.commit.int_insts 486295386 # Number of committed integer instructions.
system.cpu1.commit.function_calls 13182426 # Number of function calls committed.
system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IntAlu 366696799 69.23% 69.23% # Class of committed instruction
system.cpu1.commit.op_class_0::IntMult 1136926 0.21% 69.44% # Class of committed instruction
system.cpu1.commit.op_class_0::IntDiv 51579 0.01% 69.45% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.45% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.45% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.45% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.45% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.45% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.45% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.45% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.45% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.45% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.45% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.45% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.45% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.45% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.45% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.45% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.45% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.45% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAdd 8 0.00% 69.45% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.45% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCmp 13 0.00% 69.45% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCvt 21 0.00% 69.45% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.45% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMisc 60694 0.01% 69.46% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.46% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.46% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.46% # Class of committed instruction
system.cpu1.commit.op_class_0::MemRead 84674171 15.98% 85.45% # Class of committed instruction
system.cpu1.commit.op_class_0::MemWrite 77094537 14.55% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::total 529714748 # Class of committed instruction
system.cpu1.commit.bw_lim_events 22691519 # number cycles where commit BW limit reached
system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu1.rob.rob_reads 1219313535 # The number of ROB reads
system.cpu1.rob.rob_writes 1237971918 # The number of ROB writes
system.cpu1.timesIdled 4075861 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles 24908840 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles 47205322910 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts 450820499 # Number of Instructions Simulated
system.cpu1.committedOps 529714748 # Number of Ops (including micro ops) Simulated
system.cpu1.cpi 1.492261 # CPI: Cycles Per Instruction
system.cpu1.cpi_total 1.492261 # CPI: Total CPI of All Threads
system.cpu1.ipc 0.670124 # IPC: Instructions Per Cycle
system.cpu1.ipc_total 0.670124 # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads 696110289 # number of integer regfile reads
system.cpu1.int_regfile_writes 410149745 # number of integer regfile writes
system.cpu1.fp_regfile_reads 853704 # number of floating regfile reads
system.cpu1.fp_regfile_writes 525664 # number of floating regfile writes
system.cpu1.cc_regfile_reads 126283635 # number of cc regfile reads
system.cpu1.cc_regfile_writes 127381072 # number of cc regfile writes
system.cpu1.misc_regfile_reads 2332819849 # number of misc regfile reads
system.cpu1.misc_regfile_writes 14911197 # number of misc regfile writes
system.iocache.tags.replacements 115453 # number of replacements
system.iocache.tags.tagsinuse 10.425607 # Cycle average of tags in use
system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 115469 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle 13088656983000 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet 3.544416 # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide 6.881191 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet 0.221526 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide 0.430074 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.651600 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses 1041134 # Number of tag accesses
system.iocache.tags.data_accesses 1041134 # Number of data accesses
system.iocache.WriteInvalidateReq_hits::realview.ide 106664 # number of WriteInvalidateReq hits
system.iocache.WriteInvalidateReq_hits::total 106664 # number of WriteInvalidateReq hits
system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
system.iocache.ReadReq_misses::realview.ide 8809 # number of ReadReq misses
system.iocache.ReadReq_misses::total 8846 # number of ReadReq misses
system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
system.iocache.WriteInvalidateReq_misses::realview.ide 190 # number of WriteInvalidateReq misses
system.iocache.WriteInvalidateReq_misses::total 190 # number of WriteInvalidateReq misses
system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
system.iocache.demand_misses::realview.ide 8809 # number of demand (read+write) misses
system.iocache.demand_misses::total 8849 # number of demand (read+write) misses
system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
system.iocache.overall_misses::realview.ide 8809 # number of overall misses
system.iocache.overall_misses::total 8849 # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ethernet 5533000 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::realview.ide 1914739091 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 1920272091 # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::realview.ethernet 339000 # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total 339000 # number of WriteReq miss cycles
system.iocache.demand_miss_latency::realview.ethernet 5872000 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::realview.ide 1914739091 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 1920611091 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ethernet 5872000 # number of overall miss cycles
system.iocache.overall_miss_latency::realview.ide 1914739091 # number of overall miss cycles
system.iocache.overall_miss_latency::total 1920611091 # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::realview.ide 8809 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 8846 # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::realview.ide 106854 # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::total 106854 # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
system.iocache.demand_accesses::realview.ide 8809 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 8849 # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
system.iocache.overall_accesses::realview.ide 8809 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 8849 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.001778 # miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_miss_rate::total 0.001778 # miss rate for WriteInvalidateReq accesses
system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ethernet 149540.540541 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::realview.ide 217361.685889 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 217078.011644 # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::realview.ethernet 113000 # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 113000 # average WriteReq miss latency
system.iocache.demand_avg_miss_latency::realview.ethernet 146800 # average overall miss latency
system.iocache.demand_avg_miss_latency::realview.ide 217361.685889 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 217042.726975 # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ethernet 146800 # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 217361.685889 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 217042.726975 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 52653 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 5490 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs 9.590710 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 106664 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::realview.ide 8809 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 8846 # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses
system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::realview.ide 8809 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 8849 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses
system.iocache.overall_mshr_misses::realview.ide 8809 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 8849 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3609000 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::realview.ide 1456535121 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 1460144121 # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 183000 # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total 183000 # number of WriteReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 6643047696 # number of WriteInvalidateReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6643047696 # number of WriteInvalidateReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ethernet 3792000 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide 1456535121 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 1460327121 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ethernet 3792000 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide 1456535121 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 1460327121 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 97540.540541 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 165346.250539 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 165062.640855 # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 61000 # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 94800 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 165346.250539 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 165027.361397 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 94800 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 165346.250539 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 165027.361397 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 16389 # number of quiesce instructions executed
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
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