2009-05-11 19:38:43 +02:00
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/*
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* Copyright (c) 1999-2005 Mark D. Hill and David A. Wood
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* $Id: MOESI_CMP_token-dir.sm 1.6 05/01/19 15:48:35-06:00 mikem@royal16.cs.wisc.edu $
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*/
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2009-07-07 00:49:47 +02:00
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// This file is copied from Yasuko Watanabe's prefetch / memory protocol
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// Copied here by aep 12/14/07
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2009-05-11 19:38:43 +02:00
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2009-07-07 00:49:47 +02:00
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machine(Directory, "MESI_CMP_filter_directory protocol") : LATENCY_MEMORY_LATENCY LATENCY_TO_MEM_CTRL_LATENCY {
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2009-05-11 19:38:43 +02:00
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MessageBuffer requestToDir, network="From", virtual_network="2", ordered="false";
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MessageBuffer responseToDir, network="From", virtual_network="3", ordered="false";
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MessageBuffer responseFromDir, network="To", virtual_network="3", ordered="false";
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2009-07-07 00:49:47 +02:00
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MessageBuffer dmaRequestFromDir, network="To", virtual_network="4", ordered="true", no_vector="true";
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MessageBuffer dmaRequestToDir, network="From", virtual_network="5", ordered="true", no_vector="true";
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2009-05-11 19:38:43 +02:00
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// STATES
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enumeration(State, desc="Directory states", default="Directory_State_I") {
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// Base states
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I, desc="Owner";
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2009-07-07 00:49:47 +02:00
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ID, desc="Intermediate state for DMA_READ when in I";
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ID_W, desc="Intermediate state for DMA_WRITE when in I";
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2009-05-11 19:38:43 +02:00
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}
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// Events
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enumeration(Event, desc="Directory events") {
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2009-07-07 00:49:47 +02:00
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Fetch, desc="A memory fetch arrives";
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Data, desc="writeback data arrives";
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Memory_Data, desc="Fetched data from memory arrives";
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Memory_Ack, desc="Writeback Ack from memory arrives";
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//added by SS for dma
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DMA_READ, desc="A DMA Read memory request";
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DMA_WRITE, desc="A DMA Write memory request";
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2009-05-11 19:38:43 +02:00
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}
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// TYPES
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// DirectoryEntry
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structure(Entry, desc="...") {
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DataBlock DataBlk, desc="data for the block";
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}
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external_type(DirectoryMemory) {
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Entry lookup(Address);
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bool isPresent(Address);
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}
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2009-07-07 00:49:47 +02:00
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// to simulate detailed DRAM
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external_type(MemoryControl, inport="yes", outport="yes") {
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}
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2009-05-11 19:38:43 +02:00
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// ** OBJECTS **
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2009-07-07 00:49:47 +02:00
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// DirectoryMemory directory, constructor_hack="i";
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// MemoryControl memBuffer, constructor_hack="i";
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DirectoryMemory directory, factory='RubySystem::getDirectory(m_cfg["directory_name"])';
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MemoryControl memBuffer, factory='RubySystem::getMemoryControl(m_cfg["memory_controller_name"])';
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2009-05-11 19:38:43 +02:00
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State getState(Address addr) {
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return State:I;
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}
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void setState(Address addr, State state) {
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}
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2009-07-07 00:49:47 +02:00
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bool isGETRequest(CoherenceRequestType type) {
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return (type == CoherenceRequestType:GETS) ||
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(type == CoherenceRequestType:GET_INSTR) ||
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(type == CoherenceRequestType:GETX);
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}
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2009-05-11 19:38:43 +02:00
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// ** OUT_PORTS **
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out_port(responseNetwork_out, ResponseMsg, responseFromDir);
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2009-07-07 00:49:47 +02:00
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out_port(memQueue_out, MemoryMsg, memBuffer);
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out_port(dmaResponseNetwork_out, DMAResponseMsg, dmaRequestFromDir);
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2009-05-11 19:38:43 +02:00
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// ** IN_PORTS **
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2009-07-07 00:49:47 +02:00
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//added by SS for dma
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in_port(dmaRequestQueue_in, DMARequestMsg, dmaRequestToDir) {
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if (dmaRequestQueue_in.isReady()) {
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peek(dmaRequestQueue_in, DMARequestMsg) {
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if (in_msg.Type == DMARequestType:READ) {
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trigger(Event:DMA_READ, in_msg.PhysicalAddress);
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} else if (in_msg.Type == DMARequestType:WRITE) {
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trigger(Event:DMA_WRITE, in_msg.PhysicalAddress);
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} else {
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error("Invalid message");
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}
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}
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}
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}
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2009-05-11 19:38:43 +02:00
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in_port(requestNetwork_in, RequestMsg, requestToDir) {
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if (requestNetwork_in.isReady()) {
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peek(requestNetwork_in, RequestMsg) {
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assert(in_msg.Destination.isElement(machineID));
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2009-07-07 00:49:47 +02:00
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if (isGETRequest(in_msg.Type)) {
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2009-05-11 19:38:43 +02:00
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trigger(Event:Fetch, in_msg.Address);
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} else {
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2009-07-07 00:49:47 +02:00
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DEBUG_EXPR(in_msg);
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2009-05-11 19:38:43 +02:00
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error("Invalid message");
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}
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}
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}
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}
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in_port(responseNetwork_in, ResponseMsg, responseToDir) {
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if (responseNetwork_in.isReady()) {
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peek(responseNetwork_in, ResponseMsg) {
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assert(in_msg.Destination.isElement(machineID));
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if (in_msg.Type == CoherenceResponseType:MEMORY_DATA) {
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trigger(Event:Data, in_msg.Address);
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} else {
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DEBUG_EXPR(in_msg.Type);
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error("Invalid message");
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}
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}
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}
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}
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2009-07-07 00:49:47 +02:00
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// off-chip memory request/response is done
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in_port(memQueue_in, MemoryMsg, memBuffer) {
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if (memQueue_in.isReady()) {
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peek(memQueue_in, MemoryMsg) {
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if (in_msg.Type == MemoryRequestType:MEMORY_READ) {
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trigger(Event:Memory_Data, in_msg.Address);
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} else if (in_msg.Type == MemoryRequestType:MEMORY_WB) {
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trigger(Event:Memory_Ack, in_msg.Address);
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} else {
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DEBUG_EXPR(in_msg.Type);
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error("Invalid message");
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}
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}
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}
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}
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2009-05-11 19:38:43 +02:00
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// Actions
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action(a_sendAck, "a", desc="Send ack to L2") {
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2009-07-07 00:49:47 +02:00
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peek(memQueue_in, MemoryMsg) {
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enqueue(responseNetwork_out, ResponseMsg, latency="TO_MEM_CTRL_LATENCY") {
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2009-05-11 19:38:43 +02:00
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out_msg.Address := address;
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out_msg.Type := CoherenceResponseType:MEMORY_ACK;
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out_msg.Sender := machineID;
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2009-07-07 00:49:47 +02:00
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out_msg.Destination.add(in_msg.OriginalRequestorMachId);
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2009-05-11 19:38:43 +02:00
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out_msg.MessageSize := MessageSizeType:Response_Control;
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}
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}
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}
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action(d_sendData, "d", desc="Send data to requestor") {
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2009-07-07 00:49:47 +02:00
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peek(memQueue_in, MemoryMsg) {
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enqueue(responseNetwork_out, ResponseMsg, latency="TO_MEM_CTRL_LATENCY") {
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2009-05-11 19:38:43 +02:00
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out_msg.Address := address;
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out_msg.Type := CoherenceResponseType:MEMORY_DATA;
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out_msg.Sender := machineID;
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2009-07-07 00:49:47 +02:00
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out_msg.Destination.add(in_msg.OriginalRequestorMachId);
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out_msg.DataBlk := in_msg.DataBlk;
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2009-05-11 19:38:43 +02:00
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out_msg.Dirty := false;
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out_msg.MessageSize := MessageSizeType:Response_Data;
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}
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}
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}
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action(j_popIncomingRequestQueue, "j", desc="Pop incoming request queue") {
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requestNetwork_in.dequeue();
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}
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action(k_popIncomingResponseQueue, "k", desc="Pop incoming request queue") {
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responseNetwork_in.dequeue();
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}
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2009-07-07 00:49:47 +02:00
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action(l_popMemQueue, "q", desc="Pop off-chip request queue") {
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memQueue_in.dequeue();
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}
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action(qf_queueMemoryFetchRequest, "qf", desc="Queue off-chip fetch request") {
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peek(requestNetwork_in, RequestMsg) {
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enqueue(memQueue_out, MemoryMsg, latency="TO_MEM_CTRL_LATENCY") {
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out_msg.Address := address;
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out_msg.Type := MemoryRequestType:MEMORY_READ;
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out_msg.Sender := machineID;
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out_msg.OriginalRequestorMachId := in_msg.Requestor;
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out_msg.MessageSize := in_msg.MessageSize;
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out_msg.Prefetch := in_msg.Prefetch;
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out_msg.DataBlk := directory[in_msg.Address].DataBlk;
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DEBUG_EXPR(out_msg);
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}
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}
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}
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action(qw_queueMemoryWBRequest, "qw", desc="Queue off-chip writeback request") {
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peek(responseNetwork_in, ResponseMsg) {
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enqueue(memQueue_out, MemoryMsg, latency="TO_MEM_CTRL_LATENCY") {
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out_msg.Address := address;
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out_msg.Type := MemoryRequestType:MEMORY_WB;
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out_msg.Sender := machineID;
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out_msg.OriginalRequestorMachId := in_msg.Sender;
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out_msg.DataBlk := in_msg.DataBlk;
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out_msg.MessageSize := in_msg.MessageSize;
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//out_msg.Prefetch := in_msg.Prefetch;
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DEBUG_EXPR(out_msg);
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}
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}
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}
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2009-05-11 19:38:43 +02:00
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action(m_writeDataToMemory, "m", desc="Write dirty writeback to memory") {
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peek(responseNetwork_in, ResponseMsg) {
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directory[in_msg.Address].DataBlk := in_msg.DataBlk;
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DEBUG_EXPR(in_msg.Address);
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DEBUG_EXPR(in_msg.DataBlk);
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}
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}
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2009-07-07 00:49:47 +02:00
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//added by SS for dma
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action(qf_queueMemoryFetchRequestDMA, "qfd", desc="Queue off-chip fetch request") {
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peek(dmaRequestQueue_in, DMARequestMsg) {
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enqueue(memQueue_out, MemoryMsg, latency="TO_MEM_CTRL_LATENCY") {
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out_msg.Address := address;
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out_msg.Type := MemoryRequestType:MEMORY_READ;
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out_msg.Sender := machineID;
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out_msg.OriginalRequestorMachId := machineID;
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out_msg.MessageSize := in_msg.MessageSize;
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out_msg.DataBlk := directory[address].DataBlk;
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DEBUG_EXPR(out_msg);
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}
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}
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}
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action(p_popIncomingDMARequestQueue, "p", desc="Pop incoming DMA queue") {
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dmaRequestQueue_in.dequeue();
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}
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action(dr_sendDMAData, "dr", desc="Send Data to DMA controller from directory") {
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peek(memQueue_in, MemoryMsg) {
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enqueue(dmaResponseNetwork_out, DMAResponseMsg, latency="MEMORY_LATENCY") {
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out_msg.PhysicalAddress := address;
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out_msg.Type := DMAResponseType:DATA;
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out_msg.DataBlk := in_msg.DataBlk; // we send the entire data block and rely on the dma controller to split it up if need be
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out_msg.Destination.add(map_Address_to_DMA(address));
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out_msg.MessageSize := MessageSizeType:Response_Data;
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}
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}
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}
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action(dw_writeDMAData, "dw", desc="DMA Write data to memory") {
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peek(dmaRequestQueue_in, DMARequestMsg) {
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directory[in_msg.PhysicalAddress].DataBlk.copyPartial(in_msg.DataBlk, in_msg.Offset, in_msg.Len);
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}
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}
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action(qw_queueMemoryWBRequest_partial, "qwp", desc="Queue off-chip writeback request") {
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peek(dmaRequestQueue_in, DMARequestMsg) {
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enqueue(memQueue_out, MemoryMsg, latency="TO_MEM_CTRL_LATENCY") {
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out_msg.Address := address;
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out_msg.Type := MemoryRequestType:MEMORY_WB;
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out_msg.OriginalRequestorMachId := machineID;
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//out_msg.DataBlk := in_msg.DataBlk;
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out_msg.DataBlk.copyPartial(in_msg.DataBlk, in_msg.Offset, in_msg.Len);
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out_msg.MessageSize := in_msg.MessageSize;
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//out_msg.Prefetch := in_msg.Prefetch;
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DEBUG_EXPR(out_msg);
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}
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}
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}
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action(da_sendDMAAck, "da", desc="Send Ack to DMA controller") {
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enqueue(dmaResponseNetwork_out, DMAResponseMsg, latency="MEMORY_LATENCY") {
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out_msg.PhysicalAddress := address;
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out_msg.Type := DMAResponseType:ACK;
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out_msg.Destination.add(map_Address_to_DMA(address));
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out_msg.MessageSize := MessageSizeType:Writeback_Control;
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}
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}
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action(z_recycleRequestQueue, "z", desc="recycle request queue") {
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requestNetwork_in.dequeue();
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}
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2009-05-11 19:38:43 +02:00
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// TRANSITIONS
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transition(I, Fetch) {
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2009-07-07 00:49:47 +02:00
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//d_sendData;
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qf_queueMemoryFetchRequest;
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2009-05-11 19:38:43 +02:00
|
|
|
j_popIncomingRequestQueue;
|
|
|
|
}
|
|
|
|
|
|
|
|
transition(I, Data) {
|
|
|
|
m_writeDataToMemory;
|
2009-07-07 00:49:47 +02:00
|
|
|
//a_sendAck;
|
|
|
|
qw_queueMemoryWBRequest;
|
2009-05-11 19:38:43 +02:00
|
|
|
k_popIncomingResponseQueue;
|
|
|
|
}
|
2009-07-07 00:49:47 +02:00
|
|
|
|
|
|
|
transition(I, Memory_Data) {
|
|
|
|
d_sendData;
|
|
|
|
l_popMemQueue;
|
|
|
|
}
|
|
|
|
|
|
|
|
transition(I, Memory_Ack) {
|
|
|
|
a_sendAck;
|
|
|
|
l_popMemQueue;
|
|
|
|
}
|
|
|
|
|
|
|
|
//added by SS for dma support
|
|
|
|
transition(I, DMA_READ, ID) {
|
|
|
|
qf_queueMemoryFetchRequestDMA;
|
|
|
|
p_popIncomingDMARequestQueue;
|
|
|
|
}
|
|
|
|
|
|
|
|
transition(ID, Memory_Data, I) {
|
|
|
|
dr_sendDMAData;
|
|
|
|
l_popMemQueue;
|
|
|
|
}
|
|
|
|
|
|
|
|
transition(I, DMA_WRITE, ID_W) {
|
|
|
|
dw_writeDMAData;
|
|
|
|
qw_queueMemoryWBRequest_partial;
|
|
|
|
p_popIncomingDMARequestQueue;
|
|
|
|
}
|
|
|
|
|
|
|
|
transition(ID_W, Memory_Ack, I) {
|
|
|
|
da_sendDMAAck;
|
|
|
|
l_popMemQueue;
|
|
|
|
}
|
|
|
|
|
|
|
|
transition({ID, ID_W}, {Fetch, Data} ) {
|
|
|
|
z_recycleRequestQueue;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2009-05-11 19:38:43 +02:00
|
|
|
}
|