2007-03-11 08:00:54 +01:00
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# -*- mode:python -*-
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# Copyright (c) 2006 The Regents of The University of Michigan
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Nathan Binkert
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Import('*')
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2007-05-28 04:21:17 +02:00
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SimObject('Bridge.py')
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SimObject('Bus.py')
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SimObject('MemObject.py')
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2009-05-11 19:38:46 +02:00
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SimObject('PhysicalMemory.py')
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2009-05-11 19:38:46 +02:00
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2007-03-11 08:00:54 +01:00
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Source('bridge.cc')
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Source('bus.cc')
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Source('dram.cc')
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Source('mem_object.cc')
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Source('packet.cc')
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Source('physical.cc')
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Source('port.cc')
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Source('tport.cc')
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2008-10-12 21:08:51 +02:00
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Source('mport.cc')
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2009-05-11 19:38:46 +02:00
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2007-03-11 08:00:54 +01:00
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if env['FULL_SYSTEM']:
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Source('vport.cc')
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else:
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Source('page_table.cc')
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Source('translating_port.cc')
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2007-10-31 06:21:54 +01:00
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TraceFlag('Bus')
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TraceFlag('BusAddrRanges')
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TraceFlag('BusBridge')
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TraceFlag('LLSC')
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TraceFlag('MMU')
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TraceFlag('MemoryAccess')
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2009-11-18 22:55:58 +01:00
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TraceFlag('Ruby')
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