169 lines
5.3 KiB
C++
169 lines
5.3 KiB
C++
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/*
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* Copyright (c) 2012-2013, 2015-2016 ARM Limited
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* All rights reserved.
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2002-2005 The Regents of The University of Michigan
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* Copyright (c) 2010 Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Erik Hallnor
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* Dave Greene
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* Andreas Hansson
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*/
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/**
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* @file
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* Miss Status and Handling Register (WriteQueueEntry) definitions.
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*/
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#include "mem/cache/write_queue_entry.hh"
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#include <algorithm>
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#include <cassert>
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#include <string>
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#include <vector>
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#include "base/misc.hh"
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#include "base/types.hh"
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#include "debug/Cache.hh"
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#include "mem/cache/cache.hh"
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#include "sim/core.hh"
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using namespace std;
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inline void
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WriteQueueEntry::TargetList::add(PacketPtr pkt, Tick readyTime,
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Counter order)
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{
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emplace_back(pkt, readyTime, order);
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}
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bool
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WriteQueueEntry::TargetList::checkFunctional(PacketPtr pkt)
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{
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for (auto& t : *this) {
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if (pkt->checkFunctional(t.pkt)) {
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return true;
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}
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}
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return false;
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}
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void
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WriteQueueEntry::TargetList::print(std::ostream &os, int verbosity,
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const std::string &prefix) const
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{
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for (auto& t : *this) {
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ccprintf(os, "%sFromCPU: ", prefix);
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t.pkt->print(os, verbosity, "");
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}
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}
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void
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WriteQueueEntry::allocate(Addr blk_addr, unsigned blk_size, PacketPtr target,
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Tick when_ready, Counter _order)
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{
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blkAddr = blk_addr;
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blkSize = blk_size;
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isSecure = target->isSecure();
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readyTime = when_ready;
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order = _order;
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assert(target);
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_isUncacheable = target->req->isUncacheable();
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inService = false;
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// we should never have more than a single target for cacheable
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// writes (writebacks and clean evictions)
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panic_if(!_isUncacheable && !targets.empty(),
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"Write queue entry %#llx should never have more than one "
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"cacheable target", blkAddr);
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panic_if(!((target->isWrite() && _isUncacheable) ||
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(target->isEviction() && !_isUncacheable)),
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"Write queue entry %#llx should either be uncacheable write or "
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"a cacheable eviction");
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targets.add(target, when_ready, _order);
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}
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void
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WriteQueueEntry::deallocate()
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{
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assert(targets.empty());
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inService = false;
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}
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bool
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WriteQueueEntry::checkFunctional(PacketPtr pkt)
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{
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// For printing, we treat the WriteQueueEntry as a whole as single
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// entity. For other requests, we iterate over the individual
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// targets since that's where the actual data lies.
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if (pkt->isPrint()) {
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pkt->checkFunctional(this, blkAddr, isSecure, blkSize, NULL);
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return false;
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} else {
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return targets.checkFunctional(pkt);
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}
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}
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bool
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WriteQueueEntry::sendPacket(Cache &cache)
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{
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return cache.sendWriteQueuePacket(this);
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}
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void
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WriteQueueEntry::print(std::ostream &os, int verbosity,
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const std::string &prefix) const
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{
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ccprintf(os, "%s[%#llx:%#llx](%s) %s %s %s state: %s %s %s %s %s\n",
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prefix, blkAddr, blkAddr + blkSize - 1,
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isSecure ? "s" : "ns",
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_isUncacheable ? "Unc" : "",
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inService ? "InSvc" : "");
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ccprintf(os, "%s Targets:\n", prefix);
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targets.print(os, verbosity, prefix + " ");
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}
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std::string
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WriteQueueEntry::print() const
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{
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ostringstream str;
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print(str);
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return str.str();
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}
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