2006-07-01 01:52:08 +02:00
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# -*- mode:python -*-
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# Copyright (c) 2006 The Regents of The University of Michigan
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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2007-03-11 08:00:54 +01:00
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# Authors: Nathan Binkert
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2006-07-01 01:52:08 +02:00
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import sys
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2007-03-11 08:00:54 +01:00
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Import('*')
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2006-07-01 01:52:08 +02:00
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2007-03-11 08:00:54 +01:00
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if 'O3CPU' in env['CPU_MODELS']:
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2007-05-28 04:21:17 +02:00
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SimObject('FUPool.py')
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SimObject('FuncUnitConfig.py')
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SimObject('O3CPU.py')
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2007-03-11 08:00:54 +01:00
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Source('base_dyn_inst.cc')
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Source('bpred_unit.cc')
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Source('commit.cc')
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Source('cpu.cc')
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Source('decode.cc')
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Source('fetch.cc')
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Source('free_list.cc')
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Source('fu_pool.cc')
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Source('iew.cc')
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Source('inst_queue.cc')
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Source('lsq.cc')
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Source('lsq_unit.cc')
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Source('mem_dep_unit.cc')
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Source('rename.cc')
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Source('rename_map.cc')
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Source('rob.cc')
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Source('scoreboard.cc')
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Source('store_set.cc')
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2006-07-01 01:52:08 +02:00
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2007-03-11 08:00:54 +01:00
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if env['TARGET_ISA'] == 'alpha':
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Source('alpha/cpu.cc')
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Source('alpha/cpu_builder.cc')
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Source('alpha/dyn_inst.cc')
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Source('alpha/thread_context.cc')
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elif env['TARGET_ISA'] == 'mips':
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Source('mips/cpu.cc')
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Source('mips/cpu_builder.cc')
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Source('mips/dyn_inst.cc')
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Source('mips/thread_context.cc')
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elif env['TARGET_ISA'] == 'sparc':
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Source('sparc/cpu.cc')
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Source('sparc/cpu_builder.cc')
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Source('sparc/dyn_inst.cc')
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Source('sparc/thread_context.cc')
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else:
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sys.exit('O3 CPU does not support the \'%s\' ISA' % env['TARGET_ISA'])
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2006-07-01 01:52:08 +02:00
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2007-03-11 08:00:54 +01:00
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if env['USE_CHECKER']:
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2007-05-31 02:19:20 +02:00
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SimObject('O3Checker.py')
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2007-03-11 08:00:54 +01:00
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Source('checker_builder.cc')
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2006-07-01 01:52:08 +02:00
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2007-03-11 08:00:54 +01:00
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if 'O3CPU' in env['CPU_MODELS'] or 'OzoneCPU' in env['CPU_MODELS']:
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Source('2bit_local_pred.cc')
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Source('btb.cc')
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Source('ras.cc')
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Source('tournament_pred.cc')
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2006-07-01 01:52:08 +02:00
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