1416 lines
166 KiB
Text
1416 lines
166 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 51.781056 # Number of seconds simulated
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sim_ticks 51781056074000 # Number of ticks simulated
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final_tick 51781056074000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 717486 # Simulator instruction rate (inst/s)
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host_op_rate 843154 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 44175728553 # Simulator tick rate (ticks/s)
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host_mem_usage 650840 # Number of bytes of host memory used
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host_seconds 1172.16 # Real time elapsed on the host
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sim_insts 841009423 # Number of instructions simulated
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sim_ops 988312418 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::realview.ide 385216 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.dtb.walker 437760 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.itb.walker 790272 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.inst 4324596 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 53060296 # Number of bytes read from this memory
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system.physmem.bytes_read::total 58998140 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 4324596 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 4324596 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 30687936 # Number of bytes written to this memory
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system.physmem.bytes_written::realview.ide 6826496 # Number of bytes written to this memory
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system.physmem.bytes_written::cpu.data 99485540 # Number of bytes written to this memory
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system.physmem.bytes_written::total 136999972 # Number of bytes written to this memory
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system.physmem.num_reads::realview.ide 6019 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.dtb.walker 6840 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.itb.walker 12348 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.inst 107979 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 829080 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 962266 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 479499 # Number of write requests responded to by this memory
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system.physmem.num_writes::realview.ide 106664 # Number of write requests responded to by this memory
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system.physmem.num_writes::cpu.data 1556713 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 2142876 # Number of write requests responded to by this memory
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system.physmem.bw_read::realview.ide 7439 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.dtb.walker 8454 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.itb.walker 15262 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.inst 83517 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 1024705 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 1139377 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 83517 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 83517 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 592648 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::realview.ide 131834 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu.data 1921273 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 2645755 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 592648 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::realview.ide 139273 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.dtb.walker 8454 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.itb.walker 15262 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 83517 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 2945978 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 3785132 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 962266 # Number of read requests accepted
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system.physmem.writeReqs 2142876 # Number of write requests accepted
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system.physmem.readBursts 962266 # Number of DRAM read bursts, including those serviced by the write queue
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system.physmem.writeBursts 2142876 # Number of DRAM write bursts, including those merged in the write queue
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system.physmem.bytesReadDRAM 61369728 # Total number of bytes read from DRAM
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system.physmem.bytesReadWrQ 215296 # Total number of bytes read from write queue
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system.physmem.bytesWritten 132432768 # Total number of bytes written to DRAM
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system.physmem.bytesReadSys 58998140 # Total read bytes from the system interface side
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system.physmem.bytesWrittenSys 136999972 # Total written bytes from the system interface side
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system.physmem.servicedByWrQ 3364 # Number of DRAM read bursts serviced by the write queue
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system.physmem.mergedWrBursts 73592 # Number of DRAM write bursts merged with an existing one
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system.physmem.neitherReadNorWriteReqs 33443 # Number of requests that are neither read nor write
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system.physmem.perBankRdBursts::0 65026 # Per bank write bursts
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system.physmem.perBankRdBursts::1 59757 # Per bank write bursts
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system.physmem.perBankRdBursts::2 57697 # Per bank write bursts
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system.physmem.perBankRdBursts::3 55201 # Per bank write bursts
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system.physmem.perBankRdBursts::4 59686 # Per bank write bursts
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system.physmem.perBankRdBursts::5 66424 # Per bank write bursts
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system.physmem.perBankRdBursts::6 54909 # Per bank write bursts
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system.physmem.perBankRdBursts::7 46752 # Per bank write bursts
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system.physmem.perBankRdBursts::8 56185 # Per bank write bursts
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system.physmem.perBankRdBursts::9 105428 # Per bank write bursts
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system.physmem.perBankRdBursts::10 56738 # Per bank write bursts
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system.physmem.perBankRdBursts::11 56925 # Per bank write bursts
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system.physmem.perBankRdBursts::12 52656 # Per bank write bursts
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system.physmem.perBankRdBursts::13 52461 # Per bank write bursts
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system.physmem.perBankRdBursts::14 54958 # Per bank write bursts
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system.physmem.perBankRdBursts::15 58099 # Per bank write bursts
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system.physmem.perBankWrBursts::0 127089 # Per bank write bursts
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system.physmem.perBankWrBursts::1 113639 # Per bank write bursts
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system.physmem.perBankWrBursts::2 227284 # Per bank write bursts
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system.physmem.perBankWrBursts::3 120346 # Per bank write bursts
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system.physmem.perBankWrBursts::4 128596 # Per bank write bursts
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system.physmem.perBankWrBursts::5 124885 # Per bank write bursts
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system.physmem.perBankWrBursts::6 105979 # Per bank write bursts
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system.physmem.perBankWrBursts::7 88244 # Per bank write bursts
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system.physmem.perBankWrBursts::8 113178 # Per bank write bursts
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system.physmem.perBankWrBursts::9 146103 # Per bank write bursts
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system.physmem.perBankWrBursts::10 105873 # Per bank write bursts
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system.physmem.perBankWrBursts::11 119118 # Per bank write bursts
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system.physmem.perBankWrBursts::12 106014 # Per bank write bursts
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system.physmem.perBankWrBursts::13 144894 # Per bank write bursts
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system.physmem.perBankWrBursts::14 168059 # Per bank write bursts
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system.physmem.perBankWrBursts::15 129961 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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system.physmem.numWrRetry 15 # Number of times write queue was full causing retry
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system.physmem.totGap 51781053518000 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 43101 # Read request sizes (log2)
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system.physmem.readPktSize::3 13 # Read request sizes (log2)
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system.physmem.readPktSize::4 2 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.readPktSize::6 919150 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::2 1 # Write request sizes (log2)
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system.physmem.writePktSize::3 2572 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.writePktSize::6 2140303 # Write request sizes (log2)
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system.physmem.rdQLenPdf::0 916619 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 36737 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 2160 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 554 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 703 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 360 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 332 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 262 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 188 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 124 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 116 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 110 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 103 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 99 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 93 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 91 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 80 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 78 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 50 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 40 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 3 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 84352 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 107983 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::17 131098 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 115210 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 123261 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 119542 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 117814 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 132602 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 122703 # What write queue length does an incoming req see
|
||
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system.physmem.wrQLenPdf::24 125765 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 114111 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 113634 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 111086 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 110215 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 107145 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 106644 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 107279 # What write queue length does an incoming req see
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||
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system.physmem.wrQLenPdf::32 104685 # What write queue length does an incoming req see
|
||
|
|
system.physmem.wrQLenPdf::33 2704 # What write queue length does an incoming req see
|
||
|
|
system.physmem.wrQLenPdf::34 2147 # What write queue length does an incoming req see
|
||
|
|
system.physmem.wrQLenPdf::35 1714 # What write queue length does an incoming req see
|
||
|
|
system.physmem.wrQLenPdf::36 1256 # What write queue length does an incoming req see
|
||
|
|
system.physmem.wrQLenPdf::37 957 # What write queue length does an incoming req see
|
||
|
|
system.physmem.wrQLenPdf::38 643 # What write queue length does an incoming req see
|
||
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system.physmem.wrQLenPdf::39 439 # What write queue length does an incoming req see
|
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|
system.physmem.wrQLenPdf::40 337 # What write queue length does an incoming req see
|
||
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|
system.physmem.wrQLenPdf::41 303 # What write queue length does an incoming req see
|
||
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|
system.physmem.wrQLenPdf::42 280 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::43 299 # What write queue length does an incoming req see
|
||
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system.physmem.wrQLenPdf::44 327 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::45 330 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::46 302 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::47 285 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::48 261 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::49 233 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::50 208 # What write queue length does an incoming req see
|
||
|
|
system.physmem.wrQLenPdf::51 161 # What write queue length does an incoming req see
|
||
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|
system.physmem.wrQLenPdf::52 140 # What write queue length does an incoming req see
|
||
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system.physmem.wrQLenPdf::53 123 # What write queue length does an incoming req see
|
||
|
|
system.physmem.wrQLenPdf::54 107 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::55 97 # What write queue length does an incoming req see
|
||
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|
system.physmem.wrQLenPdf::56 89 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::57 80 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::58 65 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::59 65 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::60 55 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::61 53 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::62 37 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::63 43 # What write queue length does an incoming req see
|
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system.physmem.bytesPerActivate::samples 577071 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 335.837219 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 186.071808 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 364.354794 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::0-127 225600 39.09% 39.09% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128-255 129681 22.47% 61.57% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::256-383 48337 8.38% 69.94% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::384-511 25344 4.39% 74.33% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::512-639 16032 2.78% 77.11% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::640-767 12773 2.21% 79.33% # Bytes accessed per row activation
|
||
|
|
system.physmem.bytesPerActivate::768-895 9903 1.72% 81.04% # Bytes accessed per row activation
|
||
|
|
system.physmem.bytesPerActivate::896-1023 10527 1.82% 82.87% # Bytes accessed per row activation
|
||
|
|
system.physmem.bytesPerActivate::1024-1151 98874 17.13% 100.00% # Bytes accessed per row activation
|
||
|
|
system.physmem.bytesPerActivate::total 577071 # Bytes accessed per row activation
|
||
|
|
system.physmem.rdPerTurnAround::samples 103651 # Reads before turning the bus around for writes
|
||
|
|
system.physmem.rdPerTurnAround::mean 9.251131 # Reads before turning the bus around for writes
|
||
|
|
system.physmem.rdPerTurnAround::stdev 174.136795 # Reads before turning the bus around for writes
|
||
|
|
system.physmem.rdPerTurnAround::0-2047 103646 100.00% 100.00% # Reads before turning the bus around for writes
|
||
|
|
system.physmem.rdPerTurnAround::2048-4095 1 0.00% 100.00% # Reads before turning the bus around for writes
|
||
|
|
system.physmem.rdPerTurnAround::4096-6143 1 0.00% 100.00% # Reads before turning the bus around for writes
|
||
|
|
system.physmem.rdPerTurnAround::20480-22527 1 0.00% 100.00% # Reads before turning the bus around for writes
|
||
|
|
system.physmem.rdPerTurnAround::22528-24575 1 0.00% 100.00% # Reads before turning the bus around for writes
|
||
|
|
system.physmem.rdPerTurnAround::43008-45055 1 0.00% 100.00% # Reads before turning the bus around for writes
|
||
|
|
system.physmem.rdPerTurnAround::total 103651 # Reads before turning the bus around for writes
|
||
|
|
system.physmem.wrPerTurnAround::samples 103651 # Writes before turning the bus around for reads
|
||
|
|
system.physmem.wrPerTurnAround::mean 19.963744 # Writes before turning the bus around for reads
|
||
|
|
system.physmem.wrPerTurnAround::gmean 19.612401 # Writes before turning the bus around for reads
|
||
|
|
system.physmem.wrPerTurnAround::stdev 5.068688 # Writes before turning the bus around for reads
|
||
|
|
system.physmem.wrPerTurnAround::16-19 47209 45.55% 45.55% # Writes before turning the bus around for reads
|
||
|
|
system.physmem.wrPerTurnAround::20-23 51400 49.59% 95.14% # Writes before turning the bus around for reads
|
||
|
|
system.physmem.wrPerTurnAround::24-27 1703 1.64% 96.78% # Writes before turning the bus around for reads
|
||
|
|
system.physmem.wrPerTurnAround::28-31 1371 1.32% 98.10% # Writes before turning the bus around for reads
|
||
|
|
system.physmem.wrPerTurnAround::32-35 882 0.85% 98.95% # Writes before turning the bus around for reads
|
||
|
|
system.physmem.wrPerTurnAround::36-39 145 0.14% 99.09% # Writes before turning the bus around for reads
|
||
|
|
system.physmem.wrPerTurnAround::40-43 167 0.16% 99.25% # Writes before turning the bus around for reads
|
||
|
|
system.physmem.wrPerTurnAround::44-47 75 0.07% 99.33% # Writes before turning the bus around for reads
|
||
|
|
system.physmem.wrPerTurnAround::48-51 86 0.08% 99.41% # Writes before turning the bus around for reads
|
||
|
|
system.physmem.wrPerTurnAround::52-55 15 0.01% 99.42% # Writes before turning the bus around for reads
|
||
|
|
system.physmem.wrPerTurnAround::56-59 11 0.01% 99.43% # Writes before turning the bus around for reads
|
||
|
|
system.physmem.wrPerTurnAround::60-63 14 0.01% 99.45% # Writes before turning the bus around for reads
|
||
|
|
system.physmem.wrPerTurnAround::64-67 393 0.38% 99.83% # Writes before turning the bus around for reads
|
||
|
|
system.physmem.wrPerTurnAround::68-71 31 0.03% 99.86% # Writes before turning the bus around for reads
|
||
|
|
system.physmem.wrPerTurnAround::72-75 40 0.04% 99.89% # Writes before turning the bus around for reads
|
||
|
|
system.physmem.wrPerTurnAround::76-79 32 0.03% 99.93% # Writes before turning the bus around for reads
|
||
|
|
system.physmem.wrPerTurnAround::80-83 31 0.03% 99.96% # Writes before turning the bus around for reads
|
||
|
|
system.physmem.wrPerTurnAround::84-87 1 0.00% 99.96% # Writes before turning the bus around for reads
|
||
|
|
system.physmem.wrPerTurnAround::88-91 1 0.00% 99.96% # Writes before turning the bus around for reads
|
||
|
|
system.physmem.wrPerTurnAround::92-95 1 0.00% 99.96% # Writes before turning the bus around for reads
|
||
|
|
system.physmem.wrPerTurnAround::96-99 13 0.01% 99.97% # Writes before turning the bus around for reads
|
||
|
|
system.physmem.wrPerTurnAround::108-111 2 0.00% 99.97% # Writes before turning the bus around for reads
|
||
|
|
system.physmem.wrPerTurnAround::112-115 2 0.00% 99.97% # Writes before turning the bus around for reads
|
||
|
|
system.physmem.wrPerTurnAround::116-119 2 0.00% 99.98% # Writes before turning the bus around for reads
|
||
|
|
system.physmem.wrPerTurnAround::120-123 1 0.00% 99.98% # Writes before turning the bus around for reads
|
||
|
|
system.physmem.wrPerTurnAround::124-127 1 0.00% 99.98% # Writes before turning the bus around for reads
|
||
|
|
system.physmem.wrPerTurnAround::128-131 17 0.02% 100.00% # Writes before turning the bus around for reads
|
||
|
|
system.physmem.wrPerTurnAround::132-135 3 0.00% 100.00% # Writes before turning the bus around for reads
|
||
|
|
system.physmem.wrPerTurnAround::140-143 2 0.00% 100.00% # Writes before turning the bus around for reads
|
||
|
|
system.physmem.wrPerTurnAround::total 103651 # Writes before turning the bus around for reads
|
||
|
|
system.physmem.totQLat 10497513500 # Total ticks spent queuing
|
||
|
|
system.physmem.totMemAccLat 28476926000 # Total ticks spent from burst creation until serviced by the DRAM
|
||
|
|
system.physmem.totBusLat 4794510000 # Total ticks spent in databus transfers
|
||
|
|
system.physmem.avgQLat 10947.43 # Average queueing delay per DRAM burst
|
||
|
|
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||
|
|
system.physmem.avgMemAccLat 29697.43 # Average memory access latency per DRAM burst
|
||
|
|
system.physmem.avgRdBW 1.19 # Average DRAM read bandwidth in MiByte/s
|
||
|
|
system.physmem.avgWrBW 2.56 # Average achieved write bandwidth in MiByte/s
|
||
|
|
system.physmem.avgRdBWSys 1.14 # Average system read bandwidth in MiByte/s
|
||
|
|
system.physmem.avgWrBWSys 2.65 # Average system write bandwidth in MiByte/s
|
||
|
|
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
||
|
|
system.physmem.busUtil 0.03 # Data bus utilization in percentage
|
||
|
|
system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
|
||
|
|
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
|
||
|
|
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
|
||
|
|
system.physmem.avgWrQLen 24.00 # Average write queue length when enqueuing
|
||
|
|
system.physmem.readRowHits 723659 # Number of row buffer hits during reads
|
||
|
|
system.physmem.writeRowHits 1727431 # Number of row buffer hits during writes
|
||
|
|
system.physmem.readRowHitRate 75.47 # Row buffer hit rate for reads
|
||
|
|
system.physmem.writeRowHitRate 83.48 # Row buffer hit rate for writes
|
||
|
|
system.physmem.avgGap 16675905.17 # Average gap between requests
|
||
|
|
system.physmem.pageHitRate 80.94 # Row buffer hit rate, read and write combined
|
||
|
|
system.physmem.memoryStateTime::IDLE 49473510377000 # Time in different power states
|
||
|
|
system.physmem.memoryStateTime::REF 1729083200000 # Time in different power states
|
||
|
|
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||
|
|
system.physmem.memoryStateTime::ACT 578461163500 # Time in different power states
|
||
|
|
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||
|
|
system.physmem.actEnergy::0 2226745080 # Energy for activate commands per rank (pJ)
|
||
|
|
system.physmem.actEnergy::1 2135911680 # Energy for activate commands per rank (pJ)
|
||
|
|
system.physmem.preEnergy::0 1214989875 # Energy for precharge commands per rank (pJ)
|
||
|
|
system.physmem.preEnergy::1 1165428000 # Energy for precharge commands per rank (pJ)
|
||
|
|
system.physmem.readEnergy::0 3630494400 # Energy for read commands per rank (pJ)
|
||
|
|
system.physmem.readEnergy::1 3848871000 # Energy for read commands per rank (pJ)
|
||
|
|
system.physmem.writeEnergy::0 6713681760 # Energy for write commands per rank (pJ)
|
||
|
|
system.physmem.writeEnergy::1 6695136000 # Energy for write commands per rank (pJ)
|
||
|
|
system.physmem.refreshEnergy::0 3382086739200 # Energy for refresh commands per rank (pJ)
|
||
|
|
system.physmem.refreshEnergy::1 3382086739200 # Energy for refresh commands per rank (pJ)
|
||
|
|
system.physmem.actBackEnergy::0 1381227557085 # Energy for active background per rank (pJ)
|
||
|
|
system.physmem.actBackEnergy::1 1374892031880 # Energy for active background per rank (pJ)
|
||
|
|
system.physmem.preBackEnergy::0 29857029495750 # Energy for precharge background per rank (pJ)
|
||
|
|
system.physmem.preBackEnergy::1 29862586974000 # Energy for precharge background per rank (pJ)
|
||
|
|
system.physmem.totalEnergy::0 34634129703150 # Total energy per rank (pJ)
|
||
|
|
system.physmem.totalEnergy::1 34633411091760 # Total energy per rank (pJ)
|
||
|
|
system.physmem.averagePower::0 668.857174 # Core power per rank (mW)
|
||
|
|
system.physmem.averagePower::1 668.843296 # Core power per rank (mW)
|
||
|
|
system.realview.nvmem.bytes_read::cpu.inst 96 # Number of bytes read from this memory
|
||
|
|
system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory
|
||
|
|
system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory
|
||
|
|
system.realview.nvmem.bytes_inst_read::cpu.inst 96 # Number of instructions bytes read from this memory
|
||
|
|
system.realview.nvmem.bytes_inst_read::total 96 # Number of instructions bytes read from this memory
|
||
|
|
system.realview.nvmem.num_reads::cpu.inst 24 # Number of read requests responded to by this memory
|
||
|
|
system.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory
|
||
|
|
system.realview.nvmem.num_reads::total 29 # Number of read requests responded to by this memory
|
||
|
|
system.realview.nvmem.bw_read::cpu.inst 2 # Total read bandwidth from this memory (bytes/s)
|
||
|
|
system.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s)
|
||
|
|
system.realview.nvmem.bw_read::total 3 # Total read bandwidth from this memory (bytes/s)
|
||
|
|
system.realview.nvmem.bw_inst_read::cpu.inst 2 # Instruction read bandwidth from this memory (bytes/s)
|
||
|
|
system.realview.nvmem.bw_inst_read::total 2 # Instruction read bandwidth from this memory (bytes/s)
|
||
|
|
system.realview.nvmem.bw_total::cpu.inst 2 # Total bandwidth to/from this memory (bytes/s)
|
||
|
|
system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s)
|
||
|
|
system.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s)
|
||
|
|
system.membus.trans_dist::ReadReq 445419 # Transaction distribution
|
||
|
|
system.membus.trans_dist::ReadResp 445419 # Transaction distribution
|
||
|
|
system.membus.trans_dist::WriteReq 33871 # Transaction distribution
|
||
|
|
system.membus.trans_dist::WriteResp 33871 # Transaction distribution
|
||
|
|
system.membus.trans_dist::Writeback 479499 # Transaction distribution
|
||
|
|
system.membus.trans_dist::WriteInvalidateReq 1660804 # Transaction distribution
|
||
|
|
system.membus.trans_dist::WriteInvalidateResp 1660804 # Transaction distribution
|
||
|
|
system.membus.trans_dist::UpgradeReq 33447 # Transaction distribution
|
||
|
|
system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
|
||
|
|
system.membus.trans_dist::UpgradeResp 33449 # Transaction distribution
|
||
|
|
system.membus.trans_dist::ReadExReq 553497 # Transaction distribution
|
||
|
|
system.membus.trans_dist::ReadExResp 553497 # Transaction distribution
|
||
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 123190 # Packet count per connected master and slave (bytes)
|
||
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes)
|
||
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6936 # Packet count per connected master and slave (bytes)
|
||
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5572311 # Packet count per connected master and slave (bytes)
|
||
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5702495 # Packet count per connected master and slave (bytes)
|
||
|
|
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 228222 # Packet count per connected master and slave (bytes)
|
||
|
|
system.membus.pkt_count_system.iocache.mem_side::total 228222 # Packet count per connected master and slave (bytes)
|
||
|
|
system.membus.pkt_count::total 5930717 # Packet count per connected master and slave (bytes)
|
||
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 156320 # Cumulative packet size per connected master and slave (bytes)
|
||
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes)
|
||
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13872 # Cumulative packet size per connected master and slave (bytes)
|
||
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 188786400 # Cumulative packet size per connected master and slave (bytes)
|
||
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 188956724 # Cumulative packet size per connected master and slave (bytes)
|
||
|
|
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7211712 # Cumulative packet size per connected master and slave (bytes)
|
||
|
|
system.membus.pkt_size_system.iocache.mem_side::total 7211712 # Cumulative packet size per connected master and slave (bytes)
|
||
|
|
system.membus.pkt_size::total 196168436 # Cumulative packet size per connected master and slave (bytes)
|
||
|
|
system.membus.snoops 2862 # Total snoops (count)
|
||
|
|
system.membus.snoop_fanout::samples 3095773 # Request fanout histogram
|
||
|
|
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
||
|
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||
|
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||
|
|
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||
|
|
system.membus.snoop_fanout::1 3095773 100.00% 100.00% # Request fanout histogram
|
||
|
|
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||
|
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||
|
|
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
||
|
|
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||
|
|
system.membus.snoop_fanout::total 3095773 # Request fanout histogram
|
||
|
|
system.membus.reqLayer0.occupancy 106099500 # Layer occupancy (ticks)
|
||
|
|
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||
|
|
system.membus.reqLayer1.occupancy 31000 # Layer occupancy (ticks)
|
||
|
|
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
|
||
|
|
system.membus.reqLayer2.occupancy 5682499 # Layer occupancy (ticks)
|
||
|
|
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
||
|
|
system.membus.reqLayer5.occupancy 21134514240 # Layer occupancy (ticks)
|
||
|
|
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
|
||
|
|
system.membus.respLayer2.occupancy 11065598028 # Layer occupancy (ticks)
|
||
|
|
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
|
||
|
|
system.membus.respLayer3.occupancy 186599963 # Layer occupancy (ticks)
|
||
|
|
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
|
||
|
|
system.realview.ethernet.txBytes 966 # Bytes Transmitted
|
||
|
|
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
|
||
|
|
system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
|
||
|
|
system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
|
||
|
|
system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
|
||
|
|
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
|
||
|
|
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
|
||
|
|
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
|
||
|
|
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
|
||
|
|
system.realview.ethernet.totBandwidth 149 # Total Bandwidth (bits/s)
|
||
|
|
system.realview.ethernet.totPackets 3 # Total Packets
|
||
|
|
system.realview.ethernet.totBytes 966 # Total Bytes
|
||
|
|
system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
|
||
|
|
system.realview.ethernet.txBandwidth 149 # Transmit Bandwidth (bits/s)
|
||
|
|
system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
|
||
|
|
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
|
||
|
|
system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
|
||
|
|
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
|
||
|
|
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
|
||
|
|
system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
|
||
|
|
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
|
||
|
|
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
|
||
|
|
system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
|
||
|
|
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
|
||
|
|
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
|
||
|
|
system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
|
||
|
|
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
|
||
|
|
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
|
||
|
|
system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
|
||
|
|
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
|
||
|
|
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
|
||
|
|
system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
|
||
|
|
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
|
||
|
|
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
|
||
|
|
system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
|
||
|
|
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
|
||
|
|
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
|
||
|
|
system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
|
||
|
|
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
|
||
|
|
system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
|
||
|
|
system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
|
||
|
|
system.realview.ethernet.droppedPackets 0 # number of packets dropped
|
||
|
|
system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
|
||
|
|
system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
|
||
|
|
system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
|
||
|
|
system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes.
|
||
|
|
system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes.
|
||
|
|
system.cf0.dma_write_txs 1669 # Number of DMA write transactions.
|
||
|
|
system.iobus.trans_dist::ReadReq 40401 # Transaction distribution
|
||
|
|
system.iobus.trans_dist::ReadResp 40401 # Transaction distribution
|
||
|
|
system.iobus.trans_dist::WriteReq 136730 # Transaction distribution
|
||
|
|
system.iobus.trans_dist::WriteResp 136733 # Transaction distribution
|
||
|
|
system.iobus.trans_dist::WriteInvalidateReq 3 # Transaction distribution
|
||
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48308 # Packet count per connected master and slave (bytes)
|
||
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
|
||
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
|
||
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
|
||
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
|
||
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
|
||
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
|
||
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
|
||
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
|
||
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
|
||
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes)
|
||
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
|
||
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
|
||
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
|
||
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
|
||
|
|
system.iobus.pkt_count_system.bridge.master::total 123190 # Packet count per connected master and slave (bytes)
|
||
|
|
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230998 # Packet count per connected master and slave (bytes)
|
||
|
|
system.iobus.pkt_count_system.realview.ide.dma::total 230998 # Packet count per connected master and slave (bytes)
|
||
|
|
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
|
||
|
|
system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
|
||
|
|
system.iobus.pkt_count::total 354268 # Packet count per connected master and slave (bytes)
|
||
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48328 # Cumulative packet size per connected master and slave (bytes)
|
||
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
|
||
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
||
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
||
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
||
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
||
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
||
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
||
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
|
||
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
||
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes)
|
||
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes)
|
||
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
|
||
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes)
|
||
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
|
||
|
|
system.iobus.pkt_size_system.bridge.master::total 156320 # Cumulative packet size per connected master and slave (bytes)
|
||
|
|
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334424 # Cumulative packet size per connected master and slave (bytes)
|
||
|
|
system.iobus.pkt_size_system.realview.ide.dma::total 7334424 # Cumulative packet size per connected master and slave (bytes)
|
||
|
|
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
|
||
|
|
system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
|
||
|
|
system.iobus.pkt_size::total 7492830 # Cumulative packet size per connected master and slave (bytes)
|
||
|
|
system.iobus.reqLayer0.occupancy 36706000 # Layer occupancy (ticks)
|
||
|
|
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||
|
|
system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks)
|
||
|
|
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
|
||
|
|
system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks)
|
||
|
|
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
||
|
|
system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks)
|
||
|
|
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
|
||
|
|
system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
|
||
|
|
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
|
||
|
|
system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
|
||
|
|
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
|
||
|
|
system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
|
||
|
|
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
|
||
|
|
system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
|
||
|
|
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
|
||
|
|
system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks)
|
||
|
|
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
|
||
|
|
system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
|
||
|
|
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
|
||
|
|
system.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks)
|
||
|
|
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
|
||
|
|
system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks)
|
||
|
|
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
|
||
|
|
system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks)
|
||
|
|
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
|
||
|
|
system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks)
|
||
|
|
system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
|
||
|
|
system.iobus.reqLayer27.occupancy 981107027 # Layer occupancy (ticks)
|
||
|
|
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
|
||
|
|
system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
|
||
|
|
system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
|
||
|
|
system.iobus.respLayer0.occupancy 93124000 # Layer occupancy (ticks)
|
||
|
|
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||
|
|
system.iobus.respLayer3.occupancy 179038037 # Layer occupancy (ticks)
|
||
|
|
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
|
||
|
|
system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks)
|
||
|
|
system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
|
||
|
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
||
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
||
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
||
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
||
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
||
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
||
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
||
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||
|
|
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||
|
|
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||
|
|
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||
|
|
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
||
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
||
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
||
|
|
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
||
|
|
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
||
|
|
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
||
|
|
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
||
|
|
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
||
|
|
system.cpu.dtb.read_hits 158219223 # DTB read hits
|
||
|
|
system.cpu.dtb.read_misses 140465 # DTB read misses
|
||
|
|
system.cpu.dtb.write_hits 143634632 # DTB write hits
|
||
|
|
system.cpu.dtb.write_misses 49220 # DTB write misses
|
||
|
|
system.cpu.dtb.flush_tlb 10 # Number of times complete TLB was flushed
|
||
|
|
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||
|
|
system.cpu.dtb.flush_tlb_mva_asid 38918 # Number of times TLB was flushed by MVA & ASID
|
||
|
|
system.cpu.dtb.flush_tlb_asid 1015 # Number of times TLB was flushed by ASID
|
||
|
|
system.cpu.dtb.flush_entries 71391 # Number of entries that have been flushed from TLB
|
||
|
|
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||
|
|
system.cpu.dtb.prefetch_faults 7071 # Number of TLB faults due to prefetch
|
||
|
|
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||
|
|
system.cpu.dtb.perms_faults 18891 # Number of TLB faults due to permissions restrictions
|
||
|
|
system.cpu.dtb.read_accesses 158359688 # DTB read accesses
|
||
|
|
system.cpu.dtb.write_accesses 143683852 # DTB write accesses
|
||
|
|
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
||
|
|
system.cpu.dtb.hits 301853855 # DTB hits
|
||
|
|
system.cpu.dtb.misses 189685 # DTB misses
|
||
|
|
system.cpu.dtb.accesses 302043540 # DTB accesses
|
||
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
||
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
||
|
|
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
||
|
|
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
||
|
|
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
||
|
|
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
||
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
||
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
||
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
||
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
||
|
|
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||
|
|
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||
|
|
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||
|
|
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||
|
|
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
||
|
|
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
||
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
||
|
|
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
||
|
|
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
||
|
|
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
||
|
|
system.cpu.itb.inst_hits 841528845 # ITB inst hits
|
||
|
|
system.cpu.itb.inst_misses 119634 # ITB inst misses
|
||
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
||
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
||
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
||
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
||
|
|
system.cpu.itb.flush_tlb 10 # Number of times complete TLB was flushed
|
||
|
|
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||
|
|
system.cpu.itb.flush_tlb_mva_asid 38918 # Number of times TLB was flushed by MVA & ASID
|
||
|
|
system.cpu.itb.flush_tlb_asid 1015 # Number of times TLB was flushed by ASID
|
||
|
|
system.cpu.itb.flush_entries 51154 # Number of entries that have been flushed from TLB
|
||
|
|
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||
|
|
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
||
|
|
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||
|
|
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||
|
|
system.cpu.itb.inst_accesses 841648479 # ITB inst accesses
|
||
|
|
system.cpu.itb.hits 841528845 # DTB hits
|
||
|
|
system.cpu.itb.misses 119634 # DTB misses
|
||
|
|
system.cpu.itb.accesses 841648479 # DTB accesses
|
||
|
|
system.cpu.numCycles 103562112148 # number of cpu cycles simulated
|
||
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||
|
|
system.cpu.committedInsts 841009423 # Number of instructions committed
|
||
|
|
system.cpu.committedOps 988312418 # Number of ops (including micro ops) committed
|
||
|
|
system.cpu.num_int_alu_accesses 908272324 # Number of integer alu accesses
|
||
|
|
system.cpu.num_fp_alu_accesses 899019 # Number of float alu accesses
|
||
|
|
system.cpu.num_func_calls 50313277 # number of times a function call or return occured
|
||
|
|
system.cpu.num_conditional_control_insts 127741607 # number of instructions that are conditional controls
|
||
|
|
system.cpu.num_int_insts 908272324 # number of integer instructions
|
||
|
|
system.cpu.num_fp_insts 899019 # number of float instructions
|
||
|
|
system.cpu.num_int_register_reads 1317064952 # number of times the integer registers were read
|
||
|
|
system.cpu.num_int_register_writes 720072212 # number of times the integer registers were written
|
||
|
|
system.cpu.num_fp_register_reads 1450897 # number of times the floating registers were read
|
||
|
|
system.cpu.num_fp_register_writes 759632 # number of times the floating registers were written
|
||
|
|
system.cpu.num_cc_register_reads 218662872 # number of times the CC registers were read
|
||
|
|
system.cpu.num_cc_register_writes 218058310 # number of times the CC registers were written
|
||
|
|
system.cpu.num_mem_refs 301832909 # number of memory refs
|
||
|
|
system.cpu.num_load_insts 158209551 # Number of load instructions
|
||
|
|
system.cpu.num_store_insts 143623358 # Number of store instructions
|
||
|
|
system.cpu.num_idle_cycles 100527171614.894058 # Number of idle cycles
|
||
|
|
system.cpu.num_busy_cycles 3034940533.105942 # Number of busy cycles
|
||
|
|
system.cpu.not_idle_fraction 0.029306 # Percentage of non-idle cycles
|
||
|
|
system.cpu.idle_fraction 0.970694 # Percentage of idle cycles
|
||
|
|
system.cpu.Branches 187669847 # Number of branches fetched
|
||
|
|
system.cpu.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction
|
||
|
|
system.cpu.op_class::IntAlu 684692132 69.24% 69.24% # Class of executed instruction
|
||
|
|
system.cpu.op_class::IntMult 2140683 0.22% 69.46% # Class of executed instruction
|
||
|
|
system.cpu.op_class::IntDiv 96951 0.01% 69.47% # Class of executed instruction
|
||
|
|
system.cpu.op_class::FloatAdd 0 0.00% 69.47% # Class of executed instruction
|
||
|
|
system.cpu.op_class::FloatCmp 0 0.00% 69.47% # Class of executed instruction
|
||
|
|
system.cpu.op_class::FloatCvt 0 0.00% 69.47% # Class of executed instruction
|
||
|
|
system.cpu.op_class::FloatMult 0 0.00% 69.47% # Class of executed instruction
|
||
|
|
system.cpu.op_class::FloatDiv 0 0.00% 69.47% # Class of executed instruction
|
||
|
|
system.cpu.op_class::FloatSqrt 0 0.00% 69.47% # Class of executed instruction
|
||
|
|
system.cpu.op_class::SimdAdd 0 0.00% 69.47% # Class of executed instruction
|
||
|
|
system.cpu.op_class::SimdAddAcc 0 0.00% 69.47% # Class of executed instruction
|
||
|
|
system.cpu.op_class::SimdAlu 0 0.00% 69.47% # Class of executed instruction
|
||
|
|
system.cpu.op_class::SimdCmp 0 0.00% 69.47% # Class of executed instruction
|
||
|
|
system.cpu.op_class::SimdCvt 0 0.00% 69.47% # Class of executed instruction
|
||
|
|
system.cpu.op_class::SimdMisc 0 0.00% 69.47% # Class of executed instruction
|
||
|
|
system.cpu.op_class::SimdMult 0 0.00% 69.47% # Class of executed instruction
|
||
|
|
system.cpu.op_class::SimdMultAcc 0 0.00% 69.47% # Class of executed instruction
|
||
|
|
system.cpu.op_class::SimdShift 0 0.00% 69.47% # Class of executed instruction
|
||
|
|
system.cpu.op_class::SimdShiftAcc 0 0.00% 69.47% # Class of executed instruction
|
||
|
|
system.cpu.op_class::SimdSqrt 0 0.00% 69.47% # Class of executed instruction
|
||
|
|
system.cpu.op_class::SimdFloatAdd 8 0.00% 69.47% # Class of executed instruction
|
||
|
|
system.cpu.op_class::SimdFloatAlu 0 0.00% 69.47% # Class of executed instruction
|
||
|
|
system.cpu.op_class::SimdFloatCmp 13 0.00% 69.47% # Class of executed instruction
|
||
|
|
system.cpu.op_class::SimdFloatCvt 21 0.00% 69.47% # Class of executed instruction
|
||
|
|
system.cpu.op_class::SimdFloatDiv 0 0.00% 69.47% # Class of executed instruction
|
||
|
|
system.cpu.op_class::SimdFloatMisc 112246 0.01% 69.48% # Class of executed instruction
|
||
|
|
system.cpu.op_class::SimdFloatMult 0 0.00% 69.48% # Class of executed instruction
|
||
|
|
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 69.48% # Class of executed instruction
|
||
|
|
system.cpu.op_class::SimdFloatSqrt 0 0.00% 69.48% # Class of executed instruction
|
||
|
|
system.cpu.op_class::MemRead 158209551 16.00% 85.48% # Class of executed instruction
|
||
|
|
system.cpu.op_class::MemWrite 143623358 14.52% 100.00% # Class of executed instruction
|
||
|
|
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||
|
|
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||
|
|
system.cpu.op_class::total 988874964 # Class of executed instruction
|
||
|
|
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
||
|
|
system.cpu.kern.inst.quiesce 16062 # number of quiesce instructions executed
|
||
|
|
system.cpu.icache.tags.replacements 13492469 # number of replacements
|
||
|
|
system.cpu.icache.tags.tagsinuse 511.894753 # Cycle average of tags in use
|
||
|
|
system.cpu.icache.tags.total_refs 828035859 # Total number of references to valid blocks.
|
||
|
|
system.cpu.icache.tags.sampled_refs 13492981 # Sample count of references to valid blocks.
|
||
|
|
system.cpu.icache.tags.avg_refs 61.367896 # Average number of references to valid blocks.
|
||
|
|
system.cpu.icache.tags.warmup_cycle 31319075250 # Cycle when the warmup percentage was hit.
|
||
|
|
system.cpu.icache.tags.occ_blocks::cpu.inst 511.894753 # Average occupied blocks per requestor
|
||
|
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.999794 # Average percentage of cache occupancy
|
||
|
|
system.cpu.icache.tags.occ_percent::total 0.999794 # Average percentage of cache occupancy
|
||
|
|
system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
||
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::0 69 # Occupied blocks per task id
|
||
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::1 242 # Occupied blocks per task id
|
||
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::2 197 # Occupied blocks per task id
|
||
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id
|
||
|
|
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||
|
|
system.cpu.icache.tags.tag_accesses 855021831 # Number of tag accesses
|
||
|
|
system.cpu.icache.tags.data_accesses 855021831 # Number of data accesses
|
||
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 828035859 # number of ReadReq hits
|
||
|
|
system.cpu.icache.ReadReq_hits::total 828035859 # number of ReadReq hits
|
||
|
|
system.cpu.icache.demand_hits::cpu.inst 828035859 # number of demand (read+write) hits
|
||
|
|
system.cpu.icache.demand_hits::total 828035859 # number of demand (read+write) hits
|
||
|
|
system.cpu.icache.overall_hits::cpu.inst 828035859 # number of overall hits
|
||
|
|
system.cpu.icache.overall_hits::total 828035859 # number of overall hits
|
||
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 13492986 # number of ReadReq misses
|
||
|
|
system.cpu.icache.ReadReq_misses::total 13492986 # number of ReadReq misses
|
||
|
|
system.cpu.icache.demand_misses::cpu.inst 13492986 # number of demand (read+write) misses
|
||
|
|
system.cpu.icache.demand_misses::total 13492986 # number of demand (read+write) misses
|
||
|
|
system.cpu.icache.overall_misses::cpu.inst 13492986 # number of overall misses
|
||
|
|
system.cpu.icache.overall_misses::total 13492986 # number of overall misses
|
||
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 179568208714 # number of ReadReq miss cycles
|
||
|
|
system.cpu.icache.ReadReq_miss_latency::total 179568208714 # number of ReadReq miss cycles
|
||
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 179568208714 # number of demand (read+write) miss cycles
|
||
|
|
system.cpu.icache.demand_miss_latency::total 179568208714 # number of demand (read+write) miss cycles
|
||
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 179568208714 # number of overall miss cycles
|
||
|
|
system.cpu.icache.overall_miss_latency::total 179568208714 # number of overall miss cycles
|
||
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 841528845 # number of ReadReq accesses(hits+misses)
|
||
|
|
system.cpu.icache.ReadReq_accesses::total 841528845 # number of ReadReq accesses(hits+misses)
|
||
|
|
system.cpu.icache.demand_accesses::cpu.inst 841528845 # number of demand (read+write) accesses
|
||
|
|
system.cpu.icache.demand_accesses::total 841528845 # number of demand (read+write) accesses
|
||
|
|
system.cpu.icache.overall_accesses::cpu.inst 841528845 # number of overall (read+write) accesses
|
||
|
|
system.cpu.icache.overall_accesses::total 841528845 # number of overall (read+write) accesses
|
||
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016034 # miss rate for ReadReq accesses
|
||
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.016034 # miss rate for ReadReq accesses
|
||
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.016034 # miss rate for demand accesses
|
||
|
|
system.cpu.icache.demand_miss_rate::total 0.016034 # miss rate for demand accesses
|
||
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.016034 # miss rate for overall accesses
|
||
|
|
system.cpu.icache.overall_miss_rate::total 0.016034 # miss rate for overall accesses
|
||
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13308.263176 # average ReadReq miss latency
|
||
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 13308.263176 # average ReadReq miss latency
|
||
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13308.263176 # average overall miss latency
|
||
|
|
system.cpu.icache.demand_avg_miss_latency::total 13308.263176 # average overall miss latency
|
||
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13308.263176 # average overall miss latency
|
||
|
|
system.cpu.icache.overall_avg_miss_latency::total 13308.263176 # average overall miss latency
|
||
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
||
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 13492986 # number of ReadReq MSHR misses
|
||
|
|
system.cpu.icache.ReadReq_mshr_misses::total 13492986 # number of ReadReq MSHR misses
|
||
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 13492986 # number of demand (read+write) MSHR misses
|
||
|
|
system.cpu.icache.demand_mshr_misses::total 13492986 # number of demand (read+write) MSHR misses
|
||
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 13492986 # number of overall MSHR misses
|
||
|
|
system.cpu.icache.overall_mshr_misses::total 13492986 # number of overall MSHR misses
|
||
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 152559106286 # number of ReadReq MSHR miss cycles
|
||
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 152559106286 # number of ReadReq MSHR miss cycles
|
||
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 152559106286 # number of demand (read+write) MSHR miss cycles
|
||
|
|
system.cpu.icache.demand_mshr_miss_latency::total 152559106286 # number of demand (read+write) MSHR miss cycles
|
||
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 152559106286 # number of overall MSHR miss cycles
|
||
|
|
system.cpu.icache.overall_mshr_miss_latency::total 152559106286 # number of overall MSHR miss cycles
|
||
|
|
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 2831639000 # number of ReadReq MSHR uncacheable cycles
|
||
|
|
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 2831639000 # number of ReadReq MSHR uncacheable cycles
|
||
|
|
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 2831639000 # number of overall MSHR uncacheable cycles
|
||
|
|
system.cpu.icache.overall_mshr_uncacheable_latency::total 2831639000 # number of overall MSHR uncacheable cycles
|
||
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016034 # mshr miss rate for ReadReq accesses
|
||
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016034 # mshr miss rate for ReadReq accesses
|
||
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016034 # mshr miss rate for demand accesses
|
||
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.016034 # mshr miss rate for demand accesses
|
||
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016034 # mshr miss rate for overall accesses
|
||
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.016034 # mshr miss rate for overall accesses
|
||
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11306.548920 # average ReadReq mshr miss latency
|
||
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11306.548920 # average ReadReq mshr miss latency
|
||
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11306.548920 # average overall mshr miss latency
|
||
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 11306.548920 # average overall mshr miss latency
|
||
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11306.548920 # average overall mshr miss latency
|
||
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 11306.548920 # average overall mshr miss latency
|
||
|
|
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
|
||
|
|
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
||
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
|
||
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
||
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||
|
|
system.cpu.l2cache.tags.replacements 628827 # number of replacements
|
||
|
|
system.cpu.l2cache.tags.tagsinuse 64292.510551 # Cycle average of tags in use
|
||
|
|
system.cpu.l2cache.tags.total_refs 25964475 # Total number of references to valid blocks.
|
||
|
|
system.cpu.l2cache.tags.sampled_refs 690318 # Sample count of references to valid blocks.
|
||
|
|
system.cpu.l2cache.tags.avg_refs 37.612340 # Average number of references to valid blocks.
|
||
|
|
system.cpu.l2cache.tags.warmup_cycle 13963583388500 # Cycle when the warmup percentage was hit.
|
||
|
|
system.cpu.l2cache.tags.occ_blocks::writebacks 36090.515742 # Average occupied blocks per requestor
|
||
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 282.968665 # Average occupied blocks per requestor
|
||
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 462.557574 # Average occupied blocks per requestor
|
||
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 8120.436200 # Average occupied blocks per requestor
|
||
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.data 19336.032370 # Average occupied blocks per requestor
|
||
|
|
system.cpu.l2cache.tags.occ_percent::writebacks 0.550698 # Average percentage of cache occupancy
|
||
|
|
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.004318 # Average percentage of cache occupancy
|
||
|
|
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.007058 # Average percentage of cache occupancy
|
||
|
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.123908 # Average percentage of cache occupancy
|
||
|
|
system.cpu.l2cache.tags.occ_percent::cpu.data 0.295044 # Average percentage of cache occupancy
|
||
|
|
system.cpu.l2cache.tags.occ_percent::total 0.981026 # Average percentage of cache occupancy
|
||
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1023 448 # Occupied blocks per task id
|
||
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1024 61043 # Occupied blocks per task id
|
||
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id
|
||
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1023::1 2 # Occupied blocks per task id
|
||
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1023::2 9 # Occupied blocks per task id
|
||
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1023::4 436 # Occupied blocks per task id
|
||
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 17 # Occupied blocks per task id
|
||
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 162 # Occupied blocks per task id
|
||
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1832 # Occupied blocks per task id
|
||
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5248 # Occupied blocks per task id
|
||
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 53784 # Occupied blocks per task id
|
||
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1023 0.006836 # Percentage of cache occupancy per task id
|
||
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.931442 # Percentage of cache occupancy per task id
|
||
|
|
system.cpu.l2cache.tags.tag_accesses 245315088 # Number of tag accesses
|
||
|
|
system.cpu.l2cache.tags.data_accesses 245315088 # Number of data accesses
|
||
|
|
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 312683 # number of ReadReq hits
|
||
|
|
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 231444 # number of ReadReq hits
|
||
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 13428108 # number of ReadReq hits
|
||
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 5994715 # number of ReadReq hits
|
||
|
|
system.cpu.l2cache.ReadReq_hits::total 19966950 # number of ReadReq hits
|
||
|
|
system.cpu.l2cache.Writeback_hits::writebacks 6407423 # number of Writeback hits
|
||
|
|
system.cpu.l2cache.Writeback_hits::total 6407423 # number of Writeback hits
|
||
|
|
system.cpu.l2cache.UpgradeReq_hits::cpu.data 9635 # number of UpgradeReq hits
|
||
|
|
system.cpu.l2cache.UpgradeReq_hits::total 9635 # number of UpgradeReq hits
|
||
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 1398626 # number of ReadExReq hits
|
||
|
|
system.cpu.l2cache.ReadExReq_hits::total 1398626 # number of ReadExReq hits
|
||
|
|
system.cpu.l2cache.demand_hits::cpu.dtb.walker 312683 # number of demand (read+write) hits
|
||
|
|
system.cpu.l2cache.demand_hits::cpu.itb.walker 231444 # number of demand (read+write) hits
|
||
|
|
system.cpu.l2cache.demand_hits::cpu.inst 13428108 # number of demand (read+write) hits
|
||
|
|
system.cpu.l2cache.demand_hits::cpu.data 7393341 # number of demand (read+write) hits
|
||
|
|
system.cpu.l2cache.demand_hits::total 21365576 # number of demand (read+write) hits
|
||
|
|
system.cpu.l2cache.overall_hits::cpu.dtb.walker 312683 # number of overall hits
|
||
|
|
system.cpu.l2cache.overall_hits::cpu.itb.walker 231444 # number of overall hits
|
||
|
|
system.cpu.l2cache.overall_hits::cpu.inst 13428108 # number of overall hits
|
||
|
|
system.cpu.l2cache.overall_hits::cpu.data 7393341 # number of overall hits
|
||
|
|
system.cpu.l2cache.overall_hits::total 21365576 # number of overall hits
|
||
|
|
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 6840 # number of ReadReq misses
|
||
|
|
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 12348 # number of ReadReq misses
|
||
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 64878 # number of ReadReq misses
|
||
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 275571 # number of ReadReq misses
|
||
|
|
system.cpu.l2cache.ReadReq_misses::total 359637 # number of ReadReq misses
|
||
|
|
system.cpu.l2cache.UpgradeReq_misses::cpu.data 32886 # number of UpgradeReq misses
|
||
|
|
system.cpu.l2cache.UpgradeReq_misses::total 32886 # number of UpgradeReq misses
|
||
|
|
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses
|
||
|
|
system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses
|
||
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 554055 # number of ReadExReq misses
|
||
|
|
system.cpu.l2cache.ReadExReq_misses::total 554055 # number of ReadExReq misses
|
||
|
|
system.cpu.l2cache.demand_misses::cpu.dtb.walker 6840 # number of demand (read+write) misses
|
||
|
|
system.cpu.l2cache.demand_misses::cpu.itb.walker 12348 # number of demand (read+write) misses
|
||
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|
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|
||
|
|
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|
||
|
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|
||
|
|
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|
||
|
|
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|
||
|
|
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|
||
|
|
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|
||
|
|
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|
||
|
|
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|
||
|
|
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|
||
|
|
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|
||
|
|
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|
||
|
|
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|
||
|
|
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|
||
|
|
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|
||
|
|
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|
||
|
|
system.cpu.l2cache.SCUpgradeReq_miss_latency::total 46998 # number of SCUpgradeReq miss cycles
|
||
|
|
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|
||
|
|
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|
||
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|
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|
||
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|
||
|
|
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|
||
|
|
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|
||
|
|
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|
||
|
|
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|
||
|
|
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|
||
|
|
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|
||
|
|
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|
||
|
|
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|
||
|
|
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|
||
|
|
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|
||
|
|
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|
||
|
|
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|
||
|
|
system.cpu.l2cache.ReadReq_accesses::total 20326587 # number of ReadReq accesses(hits+misses)
|
||
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 6407423 # number of Writeback accesses(hits+misses)
|
||
|
|
system.cpu.l2cache.Writeback_accesses::total 6407423 # number of Writeback accesses(hits+misses)
|
||
|
|
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 42521 # number of UpgradeReq accesses(hits+misses)
|
||
|
|
system.cpu.l2cache.UpgradeReq_accesses::total 42521 # number of UpgradeReq accesses(hits+misses)
|
||
|
|
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses)
|
||
|
|
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|
||
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1952681 # number of ReadExReq accesses(hits+misses)
|
||
|
|
system.cpu.l2cache.ReadExReq_accesses::total 1952681 # number of ReadExReq accesses(hits+misses)
|
||
|
|
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 319523 # number of demand (read+write) accesses
|
||
|
|
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|
||
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 13492986 # number of demand (read+write) accesses
|
||
|
|
system.cpu.l2cache.demand_accesses::cpu.data 8222967 # number of demand (read+write) accesses
|
||
|
|
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|
||
|
|
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 319523 # number of overall (read+write) accesses
|
||
|
|
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|
||
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 13492986 # number of overall (read+write) accesses
|
||
|
|
system.cpu.l2cache.overall_accesses::cpu.data 8222967 # number of overall (read+write) accesses
|
||
|
|
system.cpu.l2cache.overall_accesses::total 22279268 # number of overall (read+write) accesses
|
||
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.021407 # miss rate for ReadReq accesses
|
||
|
|
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|
||
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.004808 # miss rate for ReadReq accesses
|
||
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.043949 # miss rate for ReadReq accesses
|
||
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.017693 # miss rate for ReadReq accesses
|
||
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.773406 # miss rate for UpgradeReq accesses
|
||
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.773406 # miss rate for UpgradeReq accesses
|
||
|
|
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses
|
||
|
|
system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
|
||
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.283741 # miss rate for ReadExReq accesses
|
||
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.283741 # miss rate for ReadExReq accesses
|
||
|
|
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.021407 # miss rate for demand accesses
|
||
|
|
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.050650 # miss rate for demand accesses
|
||
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.004808 # miss rate for demand accesses
|
||
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.100891 # miss rate for demand accesses
|
||
|
|
system.cpu.l2cache.demand_miss_rate::total 0.041011 # miss rate for demand accesses
|
||
|
|
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.021407 # miss rate for overall accesses
|
||
|
|
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.050650 # miss rate for overall accesses
|
||
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.004808 # miss rate for overall accesses
|
||
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.100891 # miss rate for overall accesses
|
||
|
|
system.cpu.l2cache.overall_miss_rate::total 0.041011 # miss rate for overall accesses
|
||
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 76629.678363 # average ReadReq miss latency
|
||
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 78198.048267 # average ReadReq miss latency
|
||
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73748.223358 # average ReadReq miss latency
|
||
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74156.951374 # average ReadReq miss latency
|
||
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 74268.996188 # average ReadReq miss latency
|
||
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 12163.501247 # average UpgradeReq miss latency
|
||
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 12163.501247 # average UpgradeReq miss latency
|
||
|
|
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 23499 # average SCUpgradeReq miss latency
|
||
|
|
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 23499 # average SCUpgradeReq miss latency
|
||
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71126.901555 # average ReadExReq miss latency
|
||
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71126.901555 # average ReadExReq miss latency
|
||
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 76629.678363 # average overall miss latency
|
||
|
|
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|
||
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73748.223358 # average overall miss latency
|
||
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72133.371770 # average overall miss latency
|
||
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 72363.656925 # average overall miss latency
|
||
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 76629.678363 # average overall miss latency
|
||
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 78198.048267 # average overall miss latency
|
||
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73748.223358 # average overall miss latency
|
||
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72133.371770 # average overall miss latency
|
||
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 72363.656925 # average overall miss latency
|
||
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
||
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||
|
|
system.cpu.l2cache.writebacks::writebacks 479499 # number of writebacks
|
||
|
|
system.cpu.l2cache.writebacks::total 479499 # number of writebacks
|
||
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 6840 # number of ReadReq MSHR misses
|
||
|
|
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|
||
|
|
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|
||
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 275571 # number of ReadReq MSHR misses
|
||
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 359637 # number of ReadReq MSHR misses
|
||
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 32886 # number of UpgradeReq MSHR misses
|
||
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::total 32886 # number of UpgradeReq MSHR misses
|
||
|
|
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|
||
|
|
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|
||
|
|
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|
||
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 554055 # number of ReadExReq MSHR misses
|
||
|
|
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|
||
|
|
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|
||
|
|
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|
||
|
|
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|
||
|
|
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|
||
|
|
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|
||
|
|
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|
||
|
|
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|
||
|
|
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|
||
|
|
system.cpu.l2cache.overall_mshr_misses::total 913692 # number of overall MSHR misses
|
||
|
|
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|
||
|
|
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|
||
|
|
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|
||
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16987487753 # number of ReadReq MSHR miss cycles
|
||
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 22213192518 # number of ReadReq MSHR miss cycles
|
||
|
|
system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu.data 31086027509 # number of WriteInvalidateReq MSHR miss cycles
|
||
|
|
system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::total 31086027509 # number of WriteInvalidateReq MSHR miss cycles
|
||
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 329042883 # number of UpgradeReq MSHR miss cycles
|
||
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 329042883 # number of UpgradeReq MSHR miss cycles
|
||
|
|
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 20002 # number of SCUpgradeReq MSHR miss cycles
|
||
|
|
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 20002 # number of SCUpgradeReq MSHR miss cycles
|
||
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 32500124059 # number of ReadExReq MSHR miss cycles
|
||
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 32500124059 # number of ReadExReq MSHR miss cycles
|
||
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 439737000 # number of demand (read+write) MSHR miss cycles
|
||
|
|
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|
||
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 3973034765 # number of demand (read+write) MSHR miss cycles
|
||
|
|
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|
||
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 54713316577 # number of demand (read+write) MSHR miss cycles
|
||
|
|
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|
||
|
|
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|
||
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 3973034765 # number of overall MSHR miss cycles
|
||
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 49487611812 # number of overall MSHR miss cycles
|
||
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 54713316577 # number of overall MSHR miss cycles
|
||
|
|
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 2248902500 # number of ReadReq MSHR uncacheable cycles
|
||
|
|
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5288238001 # number of ReadReq MSHR uncacheable cycles
|
||
|
|
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 7537140501 # number of ReadReq MSHR uncacheable cycles
|
||
|
|
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 5166002500 # number of WriteReq MSHR uncacheable cycles
|
||
|
|
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 5166002500 # number of WriteReq MSHR uncacheable cycles
|
||
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 2248902500 # number of overall MSHR uncacheable cycles
|
||
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10454240501 # number of overall MSHR uncacheable cycles
|
||
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 12703143001 # number of overall MSHR uncacheable cycles
|
||
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.021407 # mshr miss rate for ReadReq accesses
|
||
|
|
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|
||
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.004808 # mshr miss rate for ReadReq accesses
|
||
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.043949 # mshr miss rate for ReadReq accesses
|
||
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.017693 # mshr miss rate for ReadReq accesses
|
||
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.773406 # mshr miss rate for UpgradeReq accesses
|
||
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.773406 # mshr miss rate for UpgradeReq accesses
|
||
|
|
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses
|
||
|
|
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
|
||
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.283741 # mshr miss rate for ReadExReq accesses
|
||
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.283741 # mshr miss rate for ReadExReq accesses
|
||
|
|
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|
||
|
|
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|
||
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.004808 # mshr miss rate for demand accesses
|
||
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.100891 # mshr miss rate for demand accesses
|
||
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.041011 # mshr miss rate for demand accesses
|
||
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.021407 # mshr miss rate for overall accesses
|
||
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.050650 # mshr miss rate for overall accesses
|
||
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.004808 # mshr miss rate for overall accesses
|
||
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.100891 # mshr miss rate for overall accesses
|
||
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.041011 # mshr miss rate for overall accesses
|
||
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 64289.035088 # average ReadReq mshr miss latency
|
||
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 65835.195983 # average ReadReq mshr miss latency
|
||
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61238.551820 # average ReadReq mshr miss latency
|
||
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61644.685954 # average ReadReq mshr miss latency
|
||
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61765.592856 # average ReadReq mshr miss latency
|
||
|
|
system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data inf # average WriteInvalidateReq mshr miss latency
|
||
|
|
system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency
|
||
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10005.561120 # average UpgradeReq mshr miss latency
|
||
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10005.561120 # average UpgradeReq mshr miss latency
|
||
|
|
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency
|
||
|
|
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency
|
||
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58658.660348 # average ReadExReq mshr miss latency
|
||
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58658.660348 # average ReadExReq mshr miss latency
|
||
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 64289.035088 # average overall mshr miss latency
|
||
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 65835.195983 # average overall mshr miss latency
|
||
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61238.551820 # average overall mshr miss latency
|
||
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59650.507352 # average overall mshr miss latency
|
||
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59881.575604 # average overall mshr miss latency
|
||
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 64289.035088 # average overall mshr miss latency
|
||
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 65835.195983 # average overall mshr miss latency
|
||
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61238.551820 # average overall mshr miss latency
|
||
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59650.507352 # average overall mshr miss latency
|
||
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59881.575604 # average overall mshr miss latency
|
||
|
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
|
||
|
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
||
|
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
||
|
|
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
||
|
|
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
||
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
|
||
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
||
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
||
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||
|
|
system.cpu.dcache.tags.replacements 9444412 # number of replacements
|
||
|
|
system.cpu.dcache.tags.tagsinuse 511.969639 # Cycle average of tags in use
|
||
|
|
system.cpu.dcache.tags.total_refs 292228081 # Total number of references to valid blocks.
|
||
|
|
system.cpu.dcache.tags.sampled_refs 9444924 # Sample count of references to valid blocks.
|
||
|
|
system.cpu.dcache.tags.avg_refs 30.940226 # Average number of references to valid blocks.
|
||
|
|
system.cpu.dcache.tags.warmup_cycle 3093156250 # Cycle when the warmup percentage was hit.
|
||
|
|
system.cpu.dcache.tags.occ_blocks::cpu.data 511.969639 # Average occupied blocks per requestor
|
||
|
|
system.cpu.dcache.tags.occ_percent::cpu.data 0.999941 # Average percentage of cache occupancy
|
||
|
|
system.cpu.dcache.tags.occ_percent::total 0.999941 # Average percentage of cache occupancy
|
||
|
|
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
||
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id
|
||
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::1 381 # Occupied blocks per task id
|
||
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::2 84 # Occupied blocks per task id
|
||
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
|
||
|
|
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||
|
|
system.cpu.dcache.tags.tag_accesses 1216524124 # Number of tag accesses
|
||
|
|
system.cpu.dcache.tags.data_accesses 1216524124 # Number of data accesses
|
||
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 148096939 # number of ReadReq hits
|
||
|
|
system.cpu.dcache.ReadReq_hits::total 148096939 # number of ReadReq hits
|
||
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 136359357 # number of WriteReq hits
|
||
|
|
system.cpu.dcache.WriteReq_hits::total 136359357 # number of WriteReq hits
|
||
|
|
system.cpu.dcache.SoftPFReq_hits::cpu.data 375583 # number of SoftPFReq hits
|
||
|
|
system.cpu.dcache.SoftPFReq_hits::total 375583 # number of SoftPFReq hits
|
||
|
|
system.cpu.dcache.WriteInvalidateReq_hits::cpu.data 1554140 # number of WriteInvalidateReq hits
|
||
|
|
system.cpu.dcache.WriteInvalidateReq_hits::total 1554140 # number of WriteInvalidateReq hits
|
||
|
|
system.cpu.dcache.LoadLockedReq_hits::cpu.data 3367107 # number of LoadLockedReq hits
|
||
|
|
system.cpu.dcache.LoadLockedReq_hits::total 3367107 # number of LoadLockedReq hits
|
||
|
|
system.cpu.dcache.StoreCondReq_hits::cpu.data 3654437 # number of StoreCondReq hits
|
||
|
|
system.cpu.dcache.StoreCondReq_hits::total 3654437 # number of StoreCondReq hits
|
||
|
|
system.cpu.dcache.demand_hits::cpu.data 284456296 # number of demand (read+write) hits
|
||
|
|
system.cpu.dcache.demand_hits::total 284456296 # number of demand (read+write) hits
|
||
|
|
system.cpu.dcache.overall_hits::cpu.data 284831879 # number of overall hits
|
||
|
|
system.cpu.dcache.overall_hits::total 284831879 # number of overall hits
|
||
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 4902764 # number of ReadReq misses
|
||
|
|
system.cpu.dcache.ReadReq_misses::total 4902764 # number of ReadReq misses
|
||
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 2016394 # number of WriteReq misses
|
||
|
|
system.cpu.dcache.WriteReq_misses::total 2016394 # number of WriteReq misses
|
||
|
|
system.cpu.dcache.SoftPFReq_misses::cpu.data 1154103 # number of SoftPFReq misses
|
||
|
|
system.cpu.dcache.SoftPFReq_misses::total 1154103 # number of SoftPFReq misses
|
||
|
|
system.cpu.dcache.LoadLockedReq_misses::cpu.data 288962 # number of LoadLockedReq misses
|
||
|
|
system.cpu.dcache.LoadLockedReq_misses::total 288962 # number of LoadLockedReq misses
|
||
|
|
system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses
|
||
|
|
system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses
|
||
|
|
system.cpu.dcache.demand_misses::cpu.data 6919158 # number of demand (read+write) misses
|
||
|
|
system.cpu.dcache.demand_misses::total 6919158 # number of demand (read+write) misses
|
||
|
|
system.cpu.dcache.overall_misses::cpu.data 8073261 # number of overall misses
|
||
|
|
system.cpu.dcache.overall_misses::total 8073261 # number of overall misses
|
||
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 76779469503 # number of ReadReq miss cycles
|
||
|
|
system.cpu.dcache.ReadReq_miss_latency::total 76779469503 # number of ReadReq miss cycles
|
||
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 60928492192 # number of WriteReq miss cycles
|
||
|
|
system.cpu.dcache.WriteReq_miss_latency::total 60928492192 # number of WriteReq miss cycles
|
||
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 4073605250 # number of LoadLockedReq miss cycles
|
||
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::total 4073605250 # number of LoadLockedReq miss cycles
|
||
|
|
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 53002 # number of StoreCondReq miss cycles
|
||
|
|
system.cpu.dcache.StoreCondReq_miss_latency::total 53002 # number of StoreCondReq miss cycles
|
||
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 137707961695 # number of demand (read+write) miss cycles
|
||
|
|
system.cpu.dcache.demand_miss_latency::total 137707961695 # number of demand (read+write) miss cycles
|
||
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 137707961695 # number of overall miss cycles
|
||
|
|
system.cpu.dcache.overall_miss_latency::total 137707961695 # number of overall miss cycles
|
||
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 152999703 # number of ReadReq accesses(hits+misses)
|
||
|
|
system.cpu.dcache.ReadReq_accesses::total 152999703 # number of ReadReq accesses(hits+misses)
|
||
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 138375751 # number of WriteReq accesses(hits+misses)
|
||
|
|
system.cpu.dcache.WriteReq_accesses::total 138375751 # number of WriteReq accesses(hits+misses)
|
||
|
|
system.cpu.dcache.SoftPFReq_accesses::cpu.data 1529686 # number of SoftPFReq accesses(hits+misses)
|
||
|
|
system.cpu.dcache.SoftPFReq_accesses::total 1529686 # number of SoftPFReq accesses(hits+misses)
|
||
|
|
system.cpu.dcache.WriteInvalidateReq_accesses::cpu.data 1554140 # number of WriteInvalidateReq accesses(hits+misses)
|
||
|
|
system.cpu.dcache.WriteInvalidateReq_accesses::total 1554140 # number of WriteInvalidateReq accesses(hits+misses)
|
||
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3656069 # number of LoadLockedReq accesses(hits+misses)
|
||
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 3656069 # number of LoadLockedReq accesses(hits+misses)
|
||
|
|
system.cpu.dcache.StoreCondReq_accesses::cpu.data 3654439 # number of StoreCondReq accesses(hits+misses)
|
||
|
|
system.cpu.dcache.StoreCondReq_accesses::total 3654439 # number of StoreCondReq accesses(hits+misses)
|
||
|
|
system.cpu.dcache.demand_accesses::cpu.data 291375454 # number of demand (read+write) accesses
|
||
|
|
system.cpu.dcache.demand_accesses::total 291375454 # number of demand (read+write) accesses
|
||
|
|
system.cpu.dcache.overall_accesses::cpu.data 292905140 # number of overall (read+write) accesses
|
||
|
|
system.cpu.dcache.overall_accesses::total 292905140 # number of overall (read+write) accesses
|
||
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.032044 # miss rate for ReadReq accesses
|
||
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.032044 # miss rate for ReadReq accesses
|
||
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.014572 # miss rate for WriteReq accesses
|
||
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.014572 # miss rate for WriteReq accesses
|
||
|
|
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.754471 # miss rate for SoftPFReq accesses
|
||
|
|
system.cpu.dcache.SoftPFReq_miss_rate::total 0.754471 # miss rate for SoftPFReq accesses
|
||
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.079036 # miss rate for LoadLockedReq accesses
|
||
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.079036 # miss rate for LoadLockedReq accesses
|
||
|
|
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000001 # miss rate for StoreCondReq accesses
|
||
|
|
system.cpu.dcache.StoreCondReq_miss_rate::total 0.000001 # miss rate for StoreCondReq accesses
|
||
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.023747 # miss rate for demand accesses
|
||
|
|
system.cpu.dcache.demand_miss_rate::total 0.023747 # miss rate for demand accesses
|
||
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.027563 # miss rate for overall accesses
|
||
|
|
system.cpu.dcache.overall_miss_rate::total 0.027563 # miss rate for overall accesses
|
||
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15660.445721 # average ReadReq miss latency
|
||
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 15660.445721 # average ReadReq miss latency
|
||
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30216.560946 # average WriteReq miss latency
|
||
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 30216.560946 # average WriteReq miss latency
|
||
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14097.373530 # average LoadLockedReq miss latency
|
||
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14097.373530 # average LoadLockedReq miss latency
|
||
|
|
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 26501 # average StoreCondReq miss latency
|
||
|
|
system.cpu.dcache.StoreCondReq_avg_miss_latency::total 26501 # average StoreCondReq miss latency
|
||
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 19902.416117 # average overall miss latency
|
||
|
|
system.cpu.dcache.demand_avg_miss_latency::total 19902.416117 # average overall miss latency
|
||
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 17057.290938 # average overall miss latency
|
||
|
|
system.cpu.dcache.overall_avg_miss_latency::total 17057.290938 # average overall miss latency
|
||
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||
|
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||
|
|
system.cpu.dcache.fast_writes 1554140 # number of fast writes performed
|
||
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||
|
|
system.cpu.dcache.writebacks::writebacks 6407423 # number of writebacks
|
||
|
|
system.cpu.dcache.writebacks::total 6407423 # number of writebacks
|
||
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5098 # number of ReadReq MSHR hits
|
||
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 5098 # number of ReadReq MSHR hits
|
||
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 21192 # number of WriteReq MSHR hits
|
||
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 21192 # number of WriteReq MSHR hits
|
||
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 69202 # number of LoadLockedReq MSHR hits
|
||
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::total 69202 # number of LoadLockedReq MSHR hits
|
||
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 26290 # number of demand (read+write) MSHR hits
|
||
|
|
system.cpu.dcache.demand_mshr_hits::total 26290 # number of demand (read+write) MSHR hits
|
||
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 26290 # number of overall MSHR hits
|
||
|
|
system.cpu.dcache.overall_mshr_hits::total 26290 # number of overall MSHR hits
|
||
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 4897666 # number of ReadReq MSHR misses
|
||
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 4897666 # number of ReadReq MSHR misses
|
||
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1995202 # number of WriteReq MSHR misses
|
||
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 1995202 # number of WriteReq MSHR misses
|
||
|
|
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1152860 # number of SoftPFReq MSHR misses
|
||
|
|
system.cpu.dcache.SoftPFReq_mshr_misses::total 1152860 # number of SoftPFReq MSHR misses
|
||
|
|
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 219760 # number of LoadLockedReq MSHR misses
|
||
|
|
system.cpu.dcache.LoadLockedReq_mshr_misses::total 219760 # number of LoadLockedReq MSHR misses
|
||
|
|
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses
|
||
|
|
system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses
|
||
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 6892868 # number of demand (read+write) MSHR misses
|
||
|
|
system.cpu.dcache.demand_mshr_misses::total 6892868 # number of demand (read+write) MSHR misses
|
||
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 8045728 # number of overall MSHR misses
|
||
|
|
system.cpu.dcache.overall_mshr_misses::total 8045728 # number of overall MSHR misses
|
||
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 66593476247 # number of ReadReq MSHR miss cycles
|
||
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 66593476247 # number of ReadReq MSHR miss cycles
|
||
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 56238194808 # number of WriteReq MSHR miss cycles
|
||
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 56238194808 # number of WriteReq MSHR miss cycles
|
||
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 17420344250 # number of SoftPFReq MSHR miss cycles
|
||
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 17420344250 # number of SoftPFReq MSHR miss cycles
|
||
|
|
system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::cpu.data 50499536991 # number of WriteInvalidateReq MSHR miss cycles
|
||
|
|
system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::total 50499536991 # number of WriteInvalidateReq MSHR miss cycles
|
||
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 2639848250 # number of LoadLockedReq MSHR miss cycles
|
||
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 2639848250 # number of LoadLockedReq MSHR miss cycles
|
||
|
|
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 48998 # number of StoreCondReq MSHR miss cycles
|
||
|
|
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 48998 # number of StoreCondReq MSHR miss cycles
|
||
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 122831671055 # number of demand (read+write) MSHR miss cycles
|
||
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 122831671055 # number of demand (read+write) MSHR miss cycles
|
||
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 140252015305 # number of overall MSHR miss cycles
|
||
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 140252015305 # number of overall MSHR miss cycles
|
||
|
|
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5728170249 # number of ReadReq MSHR uncacheable cycles
|
||
|
|
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5728170249 # number of ReadReq MSHR uncacheable cycles
|
||
|
|
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5573361000 # number of WriteReq MSHR uncacheable cycles
|
||
|
|
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5573361000 # number of WriteReq MSHR uncacheable cycles
|
||
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11301531249 # number of overall MSHR uncacheable cycles
|
||
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency::total 11301531249 # number of overall MSHR uncacheable cycles
|
||
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032011 # mshr miss rate for ReadReq accesses
|
||
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032011 # mshr miss rate for ReadReq accesses
|
||
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014419 # mshr miss rate for WriteReq accesses
|
||
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014419 # mshr miss rate for WriteReq accesses
|
||
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.753658 # mshr miss rate for SoftPFReq accesses
|
||
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.753658 # mshr miss rate for SoftPFReq accesses
|
||
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.060108 # mshr miss rate for LoadLockedReq accesses
|
||
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.060108 # mshr miss rate for LoadLockedReq accesses
|
||
|
|
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000001 # mshr miss rate for StoreCondReq accesses
|
||
|
|
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses
|
||
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.023656 # mshr miss rate for demand accesses
|
||
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.023656 # mshr miss rate for demand accesses
|
||
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027469 # mshr miss rate for overall accesses
|
||
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.027469 # mshr miss rate for overall accesses
|
||
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13596.981960 # average ReadReq mshr miss latency
|
||
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13596.981960 # average ReadReq mshr miss latency
|
||
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28186.717339 # average WriteReq mshr miss latency
|
||
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28186.717339 # average WriteReq mshr miss latency
|
||
|
|
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 15110.546163 # average SoftPFReq mshr miss latency
|
||
|
|
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 15110.546163 # average SoftPFReq mshr miss latency
|
||
|
|
system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data inf # average WriteInvalidateReq mshr miss latency
|
||
|
|
system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency
|
||
|
|
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12012.414680 # average LoadLockedReq mshr miss latency
|
||
|
|
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12012.414680 # average LoadLockedReq mshr miss latency
|
||
|
|
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 24499 # average StoreCondReq mshr miss latency
|
||
|
|
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 24499 # average StoreCondReq mshr miss latency
|
||
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17820.110737 # average overall mshr miss latency
|
||
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 17820.110737 # average overall mshr miss latency
|
||
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17431.861393 # average overall mshr miss latency
|
||
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 17431.861393 # average overall mshr miss latency
|
||
|
|
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
||
|
|
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
||
|
|
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
||
|
|
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
||
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
||
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
||
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||
|
|
system.cpu.toL2Bus.trans_dist::ReadReq 20761818 # Transaction distribution
|
||
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 20753624 # Transaction distribution
|
||
|
|
system.cpu.toL2Bus.trans_dist::WriteReq 33871 # Transaction distribution
|
||
|
|
system.cpu.toL2Bus.trans_dist::WriteResp 33871 # Transaction distribution
|
||
|
|
system.cpu.toL2Bus.trans_dist::Writeback 6407423 # Transaction distribution
|
||
|
|
system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1660819 # Transaction distribution
|
||
|
|
system.cpu.toL2Bus.trans_dist::WriteInvalidateResp 1554140 # Transaction distribution
|
||
|
|
system.cpu.toL2Bus.trans_dist::UpgradeReq 42524 # Transaction distribution
|
||
|
|
system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution
|
||
|
|
system.cpu.toL2Bus.trans_dist::UpgradeResp 42526 # Transaction distribution
|
||
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 1952681 # Transaction distribution
|
||
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 1952681 # Transaction distribution
|
||
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 27072222 # Packet count per connected master and slave (bytes)
|
||
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 26182676 # Packet count per connected master and slave (bytes)
|
||
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 601299 # Packet count per connected master and slave (bytes)
|
||
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 874780 # Packet count per connected master and slave (bytes)
|
||
|
|
system.cpu.toL2Bus.pkt_count::total 54730977 # Packet count per connected master and slave (bytes)
|
||
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 863723604 # Cumulative packet size per connected master and slave (bytes)
|
||
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1036044256 # Cumulative packet size per connected master and slave (bytes)
|
||
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 1950336 # Cumulative packet size per connected master and slave (bytes)
|
||
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2556184 # Cumulative packet size per connected master and slave (bytes)
|
||
|
|
system.cpu.toL2Bus.pkt_size::total 1904274380 # Cumulative packet size per connected master and slave (bytes)
|
||
|
|
system.cpu.toL2Bus.snoops 465684 # Total snoops (count)
|
||
|
|
system.cpu.toL2Bus.snoop_fanout::samples 30748357 # Request fanout histogram
|
||
|
|
system.cpu.toL2Bus.snoop_fanout::mean 5.003758 # Request fanout histogram
|
||
|
|
system.cpu.toL2Bus.snoop_fanout::stdev 0.061188 # Request fanout histogram
|
||
|
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||
|
|
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||
|
|
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
||
|
|
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
||
|
|
system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
|
||
|
|
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
|
||
|
|
system.cpu.toL2Bus.snoop_fanout::5 30632803 99.62% 99.62% # Request fanout histogram
|
||
|
|
system.cpu.toL2Bus.snoop_fanout::6 115554 0.38% 100.00% # Request fanout histogram
|
||
|
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||
|
|
system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
|
||
|
|
system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
|
||
|
|
system.cpu.toL2Bus.snoop_fanout::total 30748357 # Request fanout histogram
|
||
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 23350352499 # Layer occupancy (ticks)
|
||
|
|
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||
|
|
system.cpu.toL2Bus.snoopLayer0.occupancy 1018500 # Layer occupancy (ticks)
|
||
|
|
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
|
||
|
|
system.cpu.toL2Bus.respLayer0.occupancy 20304235714 # Layer occupancy (ticks)
|
||
|
|
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||
|
|
system.cpu.toL2Bus.respLayer1.occupancy 13344056707 # Layer occupancy (ticks)
|
||
|
|
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||
|
|
system.cpu.toL2Bus.respLayer2.occupancy 358207000 # Layer occupancy (ticks)
|
||
|
|
system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
|
||
|
|
system.cpu.toL2Bus.respLayer3.occupancy 555725500 # Layer occupancy (ticks)
|
||
|
|
system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
|
||
|
|
system.iocache.tags.replacements 115481 # number of replacements
|
||
|
|
system.iocache.tags.tagsinuse 10.454792 # Cycle average of tags in use
|
||
|
|
system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
|
||
|
|
system.iocache.tags.sampled_refs 115497 # Sample count of references to valid blocks.
|
||
|
|
system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
|
||
|
|
system.iocache.tags.warmup_cycle 13153677258000 # Cycle when the warmup percentage was hit.
|
||
|
|
system.iocache.tags.occ_blocks::realview.ethernet 3.509713 # Average occupied blocks per requestor
|
||
|
|
system.iocache.tags.occ_blocks::realview.ide 6.945079 # Average occupied blocks per requestor
|
||
|
|
system.iocache.tags.occ_percent::realview.ethernet 0.219357 # Average percentage of cache occupancy
|
||
|
|
system.iocache.tags.occ_percent::realview.ide 0.434067 # Average percentage of cache occupancy
|
||
|
|
system.iocache.tags.occ_percent::total 0.653424 # Average percentage of cache occupancy
|
||
|
|
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
|
||
|
|
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
|
||
|
|
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
|
||
|
|
system.iocache.tags.tag_accesses 1039872 # Number of tag accesses
|
||
|
|
system.iocache.tags.data_accesses 1039872 # Number of data accesses
|
||
|
|
system.iocache.WriteInvalidateReq_hits::realview.ide 106664 # number of WriteInvalidateReq hits
|
||
|
|
system.iocache.WriteInvalidateReq_hits::total 106664 # number of WriteInvalidateReq hits
|
||
|
|
system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
|
||
|
|
system.iocache.ReadReq_misses::realview.ide 8835 # number of ReadReq misses
|
||
|
|
system.iocache.ReadReq_misses::total 8872 # number of ReadReq misses
|
||
|
|
system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
|
||
|
|
system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
|
||
|
|
system.iocache.WriteInvalidateReq_misses::realview.ide 3 # number of WriteInvalidateReq misses
|
||
|
|
system.iocache.WriteInvalidateReq_misses::total 3 # number of WriteInvalidateReq misses
|
||
|
|
system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
|
||
|
|
system.iocache.demand_misses::realview.ide 8835 # number of demand (read+write) misses
|
||
|
|
system.iocache.demand_misses::total 8875 # number of demand (read+write) misses
|
||
|
|
system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
|
||
|
|
system.iocache.overall_misses::realview.ide 8835 # number of overall misses
|
||
|
|
system.iocache.overall_misses::total 8875 # number of overall misses
|
||
|
|
system.iocache.ReadReq_miss_latency::realview.ethernet 5485000 # number of ReadReq miss cycles
|
||
|
|
system.iocache.ReadReq_miss_latency::realview.ide 1898661362 # number of ReadReq miss cycles
|
||
|
|
system.iocache.ReadReq_miss_latency::total 1904146362 # number of ReadReq miss cycles
|
||
|
|
system.iocache.WriteReq_miss_latency::realview.ethernet 339000 # number of WriteReq miss cycles
|
||
|
|
system.iocache.WriteReq_miss_latency::total 339000 # number of WriteReq miss cycles
|
||
|
|
system.iocache.demand_miss_latency::realview.ethernet 5824000 # number of demand (read+write) miss cycles
|
||
|
|
system.iocache.demand_miss_latency::realview.ide 1898661362 # number of demand (read+write) miss cycles
|
||
|
|
system.iocache.demand_miss_latency::total 1904485362 # number of demand (read+write) miss cycles
|
||
|
|
system.iocache.overall_miss_latency::realview.ethernet 5824000 # number of overall miss cycles
|
||
|
|
system.iocache.overall_miss_latency::realview.ide 1898661362 # number of overall miss cycles
|
||
|
|
system.iocache.overall_miss_latency::total 1904485362 # number of overall miss cycles
|
||
|
|
system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
|
||
|
|
system.iocache.ReadReq_accesses::realview.ide 8835 # number of ReadReq accesses(hits+misses)
|
||
|
|
system.iocache.ReadReq_accesses::total 8872 # number of ReadReq accesses(hits+misses)
|
||
|
|
system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
|
||
|
|
system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
|
||
|
|
system.iocache.WriteInvalidateReq_accesses::realview.ide 106667 # number of WriteInvalidateReq accesses(hits+misses)
|
||
|
|
system.iocache.WriteInvalidateReq_accesses::total 106667 # number of WriteInvalidateReq accesses(hits+misses)
|
||
|
|
system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
|
||
|
|
system.iocache.demand_accesses::realview.ide 8835 # number of demand (read+write) accesses
|
||
|
|
system.iocache.demand_accesses::total 8875 # number of demand (read+write) accesses
|
||
|
|
system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
|
||
|
|
system.iocache.overall_accesses::realview.ide 8835 # number of overall (read+write) accesses
|
||
|
|
system.iocache.overall_accesses::total 8875 # number of overall (read+write) accesses
|
||
|
|
system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
|
||
|
|
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
|
||
|
|
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
||
|
|
system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
|
||
|
|
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
|
||
|
|
system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.000028 # miss rate for WriteInvalidateReq accesses
|
||
|
|
system.iocache.WriteInvalidateReq_miss_rate::total 0.000028 # miss rate for WriteInvalidateReq accesses
|
||
|
|
system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
|
||
|
|
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
|
||
|
|
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
|
||
|
|
system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
|
||
|
|
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
|
||
|
|
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
|
||
|
|
system.iocache.ReadReq_avg_miss_latency::realview.ethernet 148243.243243 # average ReadReq miss latency
|
||
|
|
system.iocache.ReadReq_avg_miss_latency::realview.ide 214902.248104 # average ReadReq miss latency
|
||
|
|
system.iocache.ReadReq_avg_miss_latency::total 214624.251803 # average ReadReq miss latency
|
||
|
|
system.iocache.WriteReq_avg_miss_latency::realview.ethernet 113000 # average WriteReq miss latency
|
||
|
|
system.iocache.WriteReq_avg_miss_latency::total 113000 # average WriteReq miss latency
|
||
|
|
system.iocache.demand_avg_miss_latency::realview.ethernet 145600 # average overall miss latency
|
||
|
|
system.iocache.demand_avg_miss_latency::realview.ide 214902.248104 # average overall miss latency
|
||
|
|
system.iocache.demand_avg_miss_latency::total 214589.899944 # average overall miss latency
|
||
|
|
system.iocache.overall_avg_miss_latency::realview.ethernet 145600 # average overall miss latency
|
||
|
|
system.iocache.overall_avg_miss_latency::realview.ide 214902.248104 # average overall miss latency
|
||
|
|
system.iocache.overall_avg_miss_latency::total 214589.899944 # average overall miss latency
|
||
|
|
system.iocache.blocked_cycles::no_mshrs 51753 # number of cycles access was blocked
|
||
|
|
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||
|
|
system.iocache.blocked::no_mshrs 5490 # number of cycles access was blocked
|
||
|
|
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
||
|
|
system.iocache.avg_blocked_cycles::no_mshrs 9.426776 # average number of cycles each access was blocked
|
||
|
|
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||
|
|
system.iocache.fast_writes 106664 # number of fast writes performed
|
||
|
|
system.iocache.cache_copies 0 # number of cache copies performed
|
||
|
|
system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses
|
||
|
|
system.iocache.ReadReq_mshr_misses::realview.ide 8835 # number of ReadReq MSHR misses
|
||
|
|
system.iocache.ReadReq_mshr_misses::total 8872 # number of ReadReq MSHR misses
|
||
|
|
system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses
|
||
|
|
system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses
|
||
|
|
system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses
|
||
|
|
system.iocache.demand_mshr_misses::realview.ide 8835 # number of demand (read+write) MSHR misses
|
||
|
|
system.iocache.demand_mshr_misses::total 8875 # number of demand (read+write) MSHR misses
|
||
|
|
system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses
|
||
|
|
system.iocache.overall_mshr_misses::realview.ide 8835 # number of overall MSHR misses
|
||
|
|
system.iocache.overall_mshr_misses::total 8875 # number of overall MSHR misses
|
||
|
|
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3561000 # number of ReadReq MSHR miss cycles
|
||
|
|
system.iocache.ReadReq_mshr_miss_latency::realview.ide 1439157862 # number of ReadReq MSHR miss cycles
|
||
|
|
system.iocache.ReadReq_mshr_miss_latency::total 1442718862 # number of ReadReq MSHR miss cycles
|
||
|
|
system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 183000 # number of WriteReq MSHR miss cycles
|
||
|
|
system.iocache.WriteReq_mshr_miss_latency::total 183000 # number of WriteReq MSHR miss cycles
|
||
|
|
system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 6525754202 # number of WriteInvalidateReq MSHR miss cycles
|
||
|
|
system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6525754202 # number of WriteInvalidateReq MSHR miss cycles
|
||
|
|
system.iocache.demand_mshr_miss_latency::realview.ethernet 3744000 # number of demand (read+write) MSHR miss cycles
|
||
|
|
system.iocache.demand_mshr_miss_latency::realview.ide 1439157862 # number of demand (read+write) MSHR miss cycles
|
||
|
|
system.iocache.demand_mshr_miss_latency::total 1442901862 # number of demand (read+write) MSHR miss cycles
|
||
|
|
system.iocache.overall_mshr_miss_latency::realview.ethernet 3744000 # number of overall MSHR miss cycles
|
||
|
|
system.iocache.overall_mshr_miss_latency::realview.ide 1439157862 # number of overall MSHR miss cycles
|
||
|
|
system.iocache.overall_mshr_miss_latency::total 1442901862 # number of overall MSHR miss cycles
|
||
|
|
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses
|
||
|
|
system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
|
||
|
|
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
|
||
|
|
system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses
|
||
|
|
system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
|
||
|
|
system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses
|
||
|
|
system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
|
||
|
|
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
|
||
|
|
system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses
|
||
|
|
system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
|
||
|
|
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
|
||
|
|
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 96243.243243 # average ReadReq mshr miss latency
|
||
|
|
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 162892.797057 # average ReadReq mshr miss latency
|
||
|
|
system.iocache.ReadReq_avg_mshr_miss_latency::total 162614.840171 # average ReadReq mshr miss latency
|
||
|
|
system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 61000 # average WriteReq mshr miss latency
|
||
|
|
system.iocache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency
|
||
|
|
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency
|
||
|
|
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency
|
||
|
|
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 93600 # average overall mshr miss latency
|
||
|
|
system.iocache.demand_avg_mshr_miss_latency::realview.ide 162892.797057 # average overall mshr miss latency
|
||
|
|
system.iocache.demand_avg_mshr_miss_latency::total 162580.491493 # average overall mshr miss latency
|
||
|
|
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 93600 # average overall mshr miss latency
|
||
|
|
system.iocache.overall_avg_mshr_miss_latency::realview.ide 162892.797057 # average overall mshr miss latency
|
||
|
|
system.iocache.overall_avg_mshr_miss_latency::total 162580.491493 # average overall mshr miss latency
|
||
|
|
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||
|
|
|
||
|
|
---------- End Simulation Statistics ----------
|